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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-17 14:48:37 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-17 07:48:37 -0700 |
| commit | 45641b316a7b2c9bdf1d7807631731457b8cc0f1 (patch) | |
| tree | 47880a839b3527358636589aa14ed0b1fed043e5 /gcc | |
| parent | 2581344df6f04d63f2662fd7b562bc6b060c557b (diff) | |
| download | gcc-45641b316a7b2c9bdf1d7807631731457b8cc0f1.zip gcc-45641b316a7b2c9bdf1d7807631731457b8cc0f1.tar.gz gcc-45641b316a7b2c9bdf1d7807631731457b8cc0f1.tar.bz2 | |
i386: Enable MMX intrinsics without SSE/SSE2/SSSE3
Since MMX intrinsics are marked with SSE/SSE2/SSSE3 for SSE emulation,
enable them without SSE/SSE2/SSSE3 if MMX is enabled.
Restore TARGET_3DNOW check, which was changed to TARGET_3DNOW_A by
revision 271235.
gcc/
PR target/90497
* config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX
intrinsics without SSE/SSE2/SSSE3.
* config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW
check.
(*mmx_uavgv8qi3): Likewise.
gcc/testsuite/
PR target/90497
* gcc.target/i386/pr90497-1.c: New test.
* gcc.target/i386/pr90497-2.c: Likewise.
From-SVN: r271328
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/i386-expand.c | 6 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr90497-1.c | 12 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr90497-2.c | 11 |
6 files changed, 44 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 16b67c4..b199185 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2019-05-17 H.J. Lu <hongjiu.lu@intel.com> + + PR target/90497 + * config/i386/i386-expand.c (ix86_expand_builtin): Enable MMX + intrinsics without SSE/SSE2/SSSE3. + * config/i386/mmx.md (mmx_uavgv8qi3): Restore TARGET_3DNOW + check. + (*mmx_uavgv8qi3): Likewise. + 2019-05-17 Richard Biener <rguenther@suse.de> * gimple-pretty-print.c (dump_ternary_rhs): Handle dumping diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index df03560..f2a82a0 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -10937,8 +10937,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when - MMX is disabled. */ - if (TARGET_MMX_WITH_SSE) + MMX is disabled. NB: Since MMX intrinsics are marked with + SSE/SSE2/SSSE3, enable them without SSE/SSE2/SSSE3 if MMX is + enabled. */ + if (TARGET_MMX || TARGET_MMX_WITH_SSE) { if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 29bcf93..adad950 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1745,7 +1745,7 @@ (const_int 1) (const_int 1)])) (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && (TARGET_SSE || TARGET_3DNOW_A)" + && (TARGET_SSE || TARGET_3DNOW)" "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);") (define_insn "*mmx_uavgv8qi3" @@ -1764,7 +1764,7 @@ (const_int 1) (const_int 1)])) (const_int 1))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && (TARGET_SSE || TARGET_3DNOW_A) + && (TARGET_SSE || TARGET_3DNOW) && ix86_binary_operator_ok (PLUS, V8QImode, operands)" { /* These two instructions have the same operation, but their encoding diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f63c04d..d60a7f4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2019-05-17 H.J. Lu <hongjiu.lu@intel.com> + + PR target/90497 + * gcc.target/i386/pr90497-1.c: New test. + * gcc.target/i386/pr90497-2.c: Likewise. + 2019-05-17 Robin Dapp <rdapp@linux.ibm.com> * gcc.target/s390/global-array-element-pic.c: Add -march=z900. diff --git a/gcc/testsuite/gcc.target/i386/pr90497-1.c b/gcc/testsuite/gcc.target/i386/pr90497-1.c new file mode 100644 index 0000000..ed6ded7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90497-1.c @@ -0,0 +1,12 @@ +/* PR target/90497 */ +/* { dg-do compile } */ +/* { dg-options "-mno-sse -mmmx" { target ia32 } } */ +/* { dg-options "-mno-mmx" { target { ! ia32 } } } */ + +typedef char __v8qi __attribute__ ((__vector_size__ (8))); + +__v8qi +foo (__v8qi x, __v8qi y) +{ + return __builtin_ia32_pcmpeqb (x, y); +} diff --git a/gcc/testsuite/gcc.target/i386/pr90497-2.c b/gcc/testsuite/gcc.target/i386/pr90497-2.c new file mode 100644 index 0000000..99ee575 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr90497-2.c @@ -0,0 +1,11 @@ +/* PR target/90497 */ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-mno-sse -m3dnow" } */ + +typedef char __v8qi __attribute__ ((__vector_size__ (8))); + +__v8qi +foo (__v8qi x, __v8qi y) +{ + return __builtin_ia32_pavgusb (x, y); +} |