Add memory barriers to the double-checked locking used for static initialization.

libstdc++:
        Add memory barriers to the double-checked locking used for static
        initialization.
        * libsupc++/guard.cc (__test_and_acquire): Define default.
        (_GLIBCXX_GUARD_TEST_AND_ACQUIRE, __set_and_release)
        (_GLIBCXX_GUARD_SET_AND_RELEASE): Likewise.
        (recursion_push, recursion_pop): New abstraction functions.
        (__cxa_guard_acquire): Use _GLIBCXX_GUARD_TEST_AND_ACQUIRE.
        (__cxa_guard_release): Use _GLIBCXX_GUARD_SET_AND_RELEASE.
        * config/cpu/generic/cxxabi_tweaks.h (_GLIBCXX_GUARD_TEST): Rename
        from _GLIBCXX_GUARD_ACQUIRE and reverse sense.
        (_GLIBCXX_GUARD_SET): Rename from _GLIBCXX_GUARD_RELEASE.
        * config/cpu/arm/cxxabi_tweaks.h: Likewise.
        * config/cpu/alpha/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER)
        (_GLIBCXX_WRITE_MEM_BARRIER): Define.
        * config/cpu/powerpc/atomic_word.h: Likewise.
        * config/cpu/sparc/atomic_word.h: Likewise.
        * config/cpu/generic/atomic_word.h: Define them, commented out.
        * include/bits/atomicity.h: Define defaults.
        * config/cpu/ia64/atomic_word.h (__test_and_acquire)
        (__set_and_release): New inlines.
        (_GLIBCXX_GUARD_TEST_AND_ACQUIRE): Define.
        (_GLIBCXX_GUARD_SET_AND_RELEASE): Define.

        * libsupc++/guard.cc (acquire_1): Use __builtin_trap instead of
        abort();

gcc:
        * doc/tm.texi (TARGET_RELAXED_ORDERING): Document.
        * target.h (struct gcc_target): Add relaxed_ordering field.
        * target-def.h (TARGET_RELAXED_ORDERING): Define default.
        (TARGET_INITIALIZER): Add it.
        * config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Define.
        * config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Define.
        * config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Define.
        * config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Define.
        * cp/decl.c (expand_static_init): Don't use shortcut if
        targetm.relaxed_ordering.

From-SVN: r92659

10 files changed, 79 insertions, 9 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8cc43d3..6c6860b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2004-12-27  Jason Merrill  <jason@redhat.com>
+
+	* doc/tm.texi (TARGET_RELAXED_ORDERING): Document.
+	* target.h (struct gcc_target): Add relaxed_ordering field.
+	* target-def.h (TARGET_RELAXED_ORDERING): Define default.
+	(TARGET_INITIALIZER): Add it.
+	* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Define.
+	* config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Define.
+	* config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Define.
+	* config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Define.
+
 2004-12-27  Roger Sayle  <roger@eyesopen.com>
 
 	PR driver/16118
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 823cdbc..042ffa6 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -9462,6 +9462,12 @@ alpha_init_libfuncs (void)
 #undef TARGET_BUILD_BUILTIN_VA_LIST
 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
 
+/* The Alpha architecture does not require sequential consistency.  See
+   http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
+   for an example of how it can be violated in practice.  */
+#undef TARGET_RELAXED_ORDERING
+#define TARGET_RELAXED_ORDERING true
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 64a4e54..332fa9b 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -420,6 +420,11 @@ static const struct attribute_spec ia64_attribute_table[] =
 #undef TARGET_SCALAR_MODE_SUPPORTED_P
 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
 
+/* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
+   in an order different from the specified program order.  */
+#undef TARGET_RELAXED_ORDERING
+#define TARGET_RELAXED_ORDERING true
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 typedef enum
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index cf7c8ee..95a7b16 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1004,6 +1004,17 @@ static const char alt_reg_names[][8] =
 #undef TARGET_VECTOR_MODE_SUPPORTED_P
 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
 
+/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
+   The PowerPC architecture requires only weak consistency among
+   processors--that is, memory accesses between processors need not be
+   sequentially consistent and memory accesses among processors can occur
+   in any order. The ability to order memory accesses weakly provides
+   opportunities for more efficient use of the system bus. Unless a
+   dependency exists, the 604e allows read operations to precede store
+   operations.  */
+#undef TARGET_RELAXED_ORDERING
+#define TARGET_RELAXED_ORDERING true
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 0eff775..dd83f54 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -494,6 +494,11 @@ enum processor_type sparc_cpu;
 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
 #endif
 
+/* The SPARC v9 architecture defines a relaxed memory ordering model (RMO)
+   which requires this if enabled, though it is never used in userspace,
+   and the Ultra3 processors don't implement it.  */
+#define TARGET_RELAXED_ORDERING TARGET_V9
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Validate and override various options, and do some machine dependent
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index a62a61e..622a001 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,8 @@
+2004-12-27  Jason Merrill  <jason@redhat.com>
+
+	* decl.c (expand_static_init): Don't use shortcut if
+	targetm.relaxed_ordering.
+
 2004-12-27  Mark Mitchell  <mark@codesourcery.com>
 
 	PR c++/19149
diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c
index 991996b..7a839d7 100644
--- a/gcc/cp/decl.c
+++ b/gcc/cp/decl.c
@@ -5313,8 +5313,8 @@ expand_static_init (tree decl, tree init)
   if (DECL_FUNCTION_SCOPE_P (decl))
     {
       /* Emit code to perform this initialization but once.  */
-      tree if_stmt, inner_if_stmt = NULL_TREE;
-      tree then_clause, inner_then_clause = NULL_TREE;
+      tree if_stmt = NULL_TREE, inner_if_stmt = NULL_TREE;
+      tree then_clause = NULL_TREE, inner_then_clause = NULL_TREE;
       tree guard, guard_addr, guard_addr_list;
       tree acquire_fn, release_fn, abort_fn;
       tree flag, begin;
@@ -5353,10 +5353,16 @@ expand_static_init (tree decl, tree init)
       /* Create the guard variable.  */
       guard = get_guard (decl);
 
-      /* Begin the conditional initialization.  */
-      if_stmt = begin_if_stmt ();
-      finish_if_stmt_cond (get_guard_cond (guard), if_stmt);
-      then_clause = begin_compound_stmt (BCS_NO_SCOPE);
+      /* This optimization isn't safe on targets with relaxed memory
+	 consistency.  On such targets we force synchronization in
+	 __cxa_guard_acquire.  */
+      if (!targetm.relaxed_ordering || !flag_threadsafe_statics)
+	{
+	  /* Begin the conditional initialization.  */
+	  if_stmt = begin_if_stmt ();
+	  finish_if_stmt_cond (get_guard_cond (guard), if_stmt);
+	  then_clause = begin_compound_stmt (BCS_NO_SCOPE);
+	}
 
       if (flag_threadsafe_statics)
 	{
@@ -5419,9 +5425,12 @@ expand_static_init (tree decl, tree init)
 	  finish_if_stmt (inner_if_stmt);
 	}
 
-      finish_compound_stmt (then_clause);
-      finish_then_clause (if_stmt);
-      finish_if_stmt (if_stmt);
+      if (!targetm.relaxed_ordering || !flag_threadsafe_statics)
+	{
+	  finish_compound_stmt (then_clause);
+	  finish_then_clause (if_stmt);
+	  finish_if_stmt (if_stmt);
+	}
     }
   else
     static_aggregates = tree_cons (init, decl, static_aggregates);
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index fb45a6c..abcf707 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -9574,6 +9574,16 @@ If defined, this macro is the number of entries in
 @code{TARGET_FORMAT_TYPES}.
 @end defmac
 
+@deftypefn {Target Hook} bool TARGET_RELAXED_ORDERING
+If set to @code{true}, means that the target's memory model does not
+guarantee that loads which do not depend on one another will access
+main memory in the order of the instruction stream; if ordering is
+important, an explicit memory barrier must be used.  This is true of
+many recent processors which implement a policy of ``relaxed,''
+``weak,'' or ``release'' memory consistency, such as Alpha, PowerPC,
+and ia64.  The default is @code{false}.
+@end deftypefn
+
 @defmac TARGET_USE_JCR_SECTION
 This macro determines whether to use the JCR section to register Java
 classes. By default, TARGET_USE_JCR_SECTION is defined to 1 if both
diff --git a/gcc/target-def.h b/gcc/target-def.h
index 75c949e..cd333c3 100644
--- a/gcc/target-def.h
+++ b/gcc/target-def.h
@@ -394,6 +394,9 @@ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
 #define TARGET_GIMPLIFY_VA_ARG_EXPR std_gimplify_va_arg_expr
 #define TARGET_PASS_BY_REFERENCE hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
+
+#define TARGET_RELAXED_ORDERING false
+
 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size_or_pad
 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_false
 
@@ -533,6 +536,7 @@ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
   TARGET_ASM_FILE_START_FILE_DIRECTIVE,		\
   TARGET_HANDLE_PRAGMA_REDEFINE_EXTNAME,	\
   TARGET_HANDLE_PRAGMA_EXTERN_PREFIX,		\
+  TARGET_RELAXED_ORDERING,			\
 }
 
 #include "hooks.h"
diff --git a/gcc/target.h b/gcc/target.h
index 4f4b49e..9ad460c 100644
--- a/gcc/target.h
+++ b/gcc/target.h
@@ -598,6 +598,10 @@ struct gcc_target
   /* True if #pragma extern_prefix is to be supported.  */
   bool handle_pragma_extern_prefix;
 
+  /* True if the target is allowed to reorder memory accesses unless
+     synchronization is explicitly requested.  */
+  bool relaxed_ordering;
+
   /* Leave the boolean fields at the end.  */
 };