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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-11-13 08:21:16 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-11-13 08:21:16 +0000 |
| commit | 441b4d0fa20992086704ebf013a4f8c3a41c96b0 (patch) | |
| tree | 3b516c242fa295288c1b96d50ba9210b64be8173 /gcc | |
| parent | 41a0d8d4c09552cf8242e30ac9137960f4ded681 (diff) | |
| download | gcc-441b4d0fa20992086704ebf013a4f8c3a41c96b0.zip gcc-441b4d0fa20992086704ebf013a4f8c3a41c96b0.tar.gz gcc-441b4d0fa20992086704ebf013a4f8c3a41c96b0.tar.bz2 | |
[AArch64] More aarch64_endian_lane_rtx
r254466 failed to update some uses of ENDIAN_LANE_N that were added after
the patch was initially written, which meant that we were treating the
mode number as an element count.
2017-11-13 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>):
Upddate call to ENDIAN_LANE_N.
(aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx.
(aarch64_<sur>dot_laneq<vsi2qi>): Likewise.
(*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N
and use aarch64_endian_lane_rtx.
(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
From-SVN: r254670
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 18 |
2 files changed, 18 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d888379..dce8e02 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-11-13 Richard Sandiford <richard.sandiford@linaro.org> + + * config/aarch64/aarch64-simd.md (aarch64_store_lane0<mode>): + Upddate call to ENDIAN_LANE_N. + (aarch64_<sur>dot_lane<vsi2qi>): Use aarch64_endian_lane_rtx. + (aarch64_<sur>dot_laneq<vsi2qi>): Likewise. + (*aarch64_simd_vec_copy_lane<mode>): Update calls to ENDIAN_LANE_N + and use aarch64_endian_lane_rtx. + (*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise. + 2017-11-12 Tom de Vries <tom@codesourcery.com> * config/riscv/riscv.h (ASM_OUTPUT_LABELREF): Wrap in do {} while (0). diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9a6da35..2ee0953 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -173,7 +173,7 @@ (vec_select:<VEL> (match_operand:VALL_F16 1 "register_operand" "w") (parallel [(match_operand 2 "const_int_operand" "n")])))] "TARGET_SIMD - && ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])) == 0" + && ENDIAN_LANE_N (<nunits>, INTVAL (operands[2])) == 0" "str\\t%<Vetype>1, %0" [(set_attr "type" "neon_store1_1reg<q>")] ) @@ -450,8 +450,7 @@ DOTPROD)))] "TARGET_DOTPROD" { - operands[4] - = GEN_INT (ENDIAN_LANE_N (V8QImode, INTVAL (operands[4]))); + operands[4] = aarch64_endian_lane_rtx (V8QImode, INTVAL (operands[4])); return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]"; } [(set_attr "type" "neon_dot")] @@ -466,8 +465,7 @@ DOTPROD)))] "TARGET_DOTPROD" { - operands[4] - = GEN_INT (ENDIAN_LANE_N (V16QImode, INTVAL (operands[4]))); + operands[4] = aarch64_endian_lane_rtx (V16QImode, INTVAL (operands[4])); return "<sur>dot\\t%0.<Vtype>, %2.<Vdottype>, %3.4b[%4]"; } [(set_attr "type" "neon_dot")] @@ -734,9 +732,9 @@ (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { - int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2]))); + int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); - operands[4] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[4]))); + operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4])); return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]"; } @@ -755,10 +753,10 @@ (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" { - int elt = ENDIAN_LANE_N (<MODE>mode, exact_log2 (INTVAL (operands[2]))); + int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); - operands[4] = GEN_INT (ENDIAN_LANE_N (<VSWAP_WIDTH>mode, - INTVAL (operands[4]))); + operands[4] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, + INTVAL (operands[4])); return "ins\t%0.<Vetype>[%p2], %3.<Vetype>[%4]"; } |