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| author | Kito Cheng <kito.cheng@sifive.com> | 2021-05-25 21:26:12 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-05-25 21:28:14 +0800 |
| commit | 3b0a7d624e64eeb81e4d5e8c62c46d86ef521857 (patch) | |
| tree | 103d29982d9a964439a2728a42da0af6c109c3ed /gcc | |
| parent | ebd5e86c0f41dc1d692f9b2b68a510b1f6835a3e (diff) | |
| download | gcc-3b0a7d624e64eeb81e4d5e8c62c46d86ef521857.zip gcc-3b0a7d624e64eeb81e4d5e8c62c46d86ef521857.tar.gz gcc-3b0a7d624e64eeb81e4d5e8c62c46d86ef521857.tar.bz2 | |
RISC-V: Pass -mno-relax to assembler
gcc/ChangeLog:
* config/riscv/riscv.h (ASM_SPEC): Pass -mno-relax.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index f3e8572..f47d5b4 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -98,6 +98,7 @@ extern const char *riscv_default_mtune (int argc, const char **argv); %{" FPIE_OR_FPIC_SPEC ":-fpic} \ %{march=*} \ %{mabi=*} \ +%{mno-relax} \ %{mbig-endian} \ %{mlittle-endian} \ %(subtarget_asm_spec)" \ |