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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-03 16:44:56 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-12-06 21:19:53 +0000 |
| commit | 3aba045882d1f589d36eaedd947a014ac6eb5ec3 (patch) | |
| tree | 363cb5cadb488eb5154576a162fa2ec8340575b2 /gcc | |
| parent | 16a05fac33ddde7a50da9cb937a9b83ea7c111f6 (diff) | |
| download | gcc-3aba045882d1f589d36eaedd947a014ac6eb5ec3.zip gcc-3aba045882d1f589d36eaedd947a014ac6eb5ec3.tar.gz gcc-3aba045882d1f589d36eaedd947a014ac6eb5ec3.tar.bz2 | |
aarch64: Add support for GCS system registers with the +gcs modifier
Given the introduction of system registers associated with the Guarded
Control Stack extension to Armv9.4-a in Binutils and their reliance on
the `+gcs' modifier, we implement the necessary changes in GCC to
allow for them to be recognized by the compiler.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (gcs): New.
* config/aarch64/aarch64.h (AARCH64_ISA_GCS): New.
(TARGET_THE): Likewise.
* doc/invoke.texi (AArch64 Options): Describe GCS.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-option-extensions.def | 2 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.h | 6 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 2 |
3 files changed, 10 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 97f0339..02fc895 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -163,4 +163,6 @@ AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128") AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the") +AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index f0af0b4..5a776df 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -265,6 +265,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) #define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128) #define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE) +#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS) /* The current function is a normal non-streaming function. */ #define TARGET_NON_STREAMING (AARCH64_ISA_SM_OFF) @@ -465,6 +466,11 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; enabled through +the. */ #define TARGET_THE (AARCH64_ISA_THE) +/* Armv9.4-A Guarded Control Stack extension system registers are + enabled through +gcs. */ +#define TARGET_GCS (AARCH64_ISA_GCS) + + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f5e5546..bff3645 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21363,6 +21363,8 @@ Enable the FEAT_SME_F64F64 extension to SME. Enable the Scalable Matrix Extension 2. This also enables SME instructions. @item d128 Enable support for 128-bit system register read/write instructions. +@item gcs +Enable support for Armv9.4-a Guarded Control Stack extension. @item the Enable support for Armv8.9-a/9.4-a translation hardening extension. |