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authorEric Botcazou <ebotcazou@adacore.com>2005-11-07 19:14:02 +0000
committerEric Botcazou <ebotcazou@gcc.gnu.org>2005-11-07 19:14:02 +0000
commit3ab997e838226a1404dcf43111c8139a4b3aef66 (patch)
tree001232e238f771969576c56eb45c370bca7b23a8 /gcc
parenta7297856af43a0c5f563ff5a71a4503f9e01f625 (diff)
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expmed.c (extract_bit_field): Do not use insv/extv/extzv patterns if the bitsize is zero.
* expmed.c (extract_bit_field): Do not use insv/extv/extzv patterns if the bitsize is zero. * doc/md.texi (Standard Pattern Names): Document it. * config/ia64/ia64.c (ia64_pass_by_reference): Delete. (TARGET_PASS_BY_REFERENCE): Likewise. From-SVN: r106605
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog9
-rw-r--r--gcc/config/ia64/ia64.c15
-rw-r--r--gcc/doc/md.texi4
-rw-r--r--gcc/expmed.c10
4 files changed, 17 insertions, 21 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 80e2f86..73635c1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2005-11-07 Eric Botcazou <ebotcazou@adacore.com>
+
+ * expmed.c (extract_bit_field): Do not use insv/extv/extzv patterns
+ if the bitsize is zero.
+ * doc/md.texi (Standard Pattern Names): Document it.
+
+ * config/ia64/ia64.c (ia64_pass_by_reference): Delete.
+ (TARGET_PASS_BY_REFERENCE): Likewise.
+
2005-11-07 Ian Lance Taylor <ian@airs.com>
PR rtl-optimization/24683
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 2e1cc19..d1003b3 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -176,8 +176,6 @@ static rtx gen_fr_restore_x (rtx, rtx, rtx);
static enum machine_mode hfa_element_mode (tree, bool);
static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
tree, int *, int);
-static bool ia64_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
- tree, bool);
static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
tree, bool);
static bool ia64_function_ok_for_sibcall (tree, tree);
@@ -349,8 +347,6 @@ static const struct attribute_spec ia64_attribute_table[] =
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
-#undef TARGET_PASS_BY_REFERENCE
-#define TARGET_PASS_BY_REFERENCE ia64_pass_by_reference
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
@@ -4221,17 +4217,6 @@ ia64_function_arg_boundary (enum machine_mode mode, tree type)
return PARM_BOUNDARY;
}
-/* Variable sized types are passed by reference. */
-/* ??? At present this is a GCC extension to the IA-64 ABI. */
-
-static bool
-ia64_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
- enum machine_mode mode ATTRIBUTE_UNUSED,
- tree type, bool named ATTRIBUTE_UNUSED)
-{
- return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
-}
-
/* True if it is OK to do sibling call optimization for the specified
call expression EXP. DECL will be the called function, or NULL if
this is an indirect call. */
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 36b0273..4fc8c3b 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3551,7 +3551,7 @@ Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
be valid for @code{word_mode}.
The RTL generation pass generates this instruction only with constants
-for operands 2 and 3.
+for operands 2 and 3 and the constant is never zero for operand 2.
The bit-field value is sign-extended to a full word integer
before it is stored in operand 0.
@@ -3569,7 +3569,7 @@ operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
Operands 1 and 2 must be valid for @code{word_mode}.
The RTL generation pass generates this instruction only with constants
-for operands 1 and 2.
+for operands 1 and 2 and the constant is never zero for operand 1.
@cindex @code{mov@var{mode}cc} instruction pattern
@item @samp{mov@var{mode}cc}
diff --git a/gcc/expmed.c b/gcc/expmed.c
index 19d972d..00172a3 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -608,8 +608,8 @@ store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
if (HAVE_insv
&& GET_MODE (value) != BLKmode
&& !(bitsize == 1 && GET_CODE (value) == CONST_INT)
- /* Ensure insv's size is wide enough for this field. */
- && (GET_MODE_BITSIZE (op_mode) >= bitsize)
+ && bitsize > 0
+ && GET_MODE_BITSIZE (op_mode) >= bitsize
&& ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
&& (bitsize + bitpos > GET_MODE_BITSIZE (op_mode))))
{
@@ -1356,7 +1356,8 @@ extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
if (unsignedp)
{
if (HAVE_extzv
- && (GET_MODE_BITSIZE (extzv_mode) >= bitsize)
+ && bitsize > 0
+ && GET_MODE_BITSIZE (extzv_mode) >= bitsize
&& ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
&& (bitsize + bitpos > GET_MODE_BITSIZE (extzv_mode))))
{
@@ -1488,7 +1489,8 @@ extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
else
{
if (HAVE_extv
- && (GET_MODE_BITSIZE (extv_mode) >= bitsize)
+ && bitsize > 0
+ && GET_MODE_BITSIZE (extv_mode) >= bitsize
&& ! ((REG_P (op0) || GET_CODE (op0) == SUBREG)
&& (bitsize + bitpos > GET_MODE_BITSIZE (extv_mode))))
{