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| author | Mike Stump <mrs@gcc.gnu.org> | 1996-07-26 17:59:49 +0000 |
|---|---|---|
| committer | Mike Stump <mrs@gcc.gnu.org> | 1996-07-26 17:59:49 +0000 |
| commit | 39950dff997d3a75c807c1339ccf7bb4991e6104 (patch) | |
| tree | 5e718e5ec8a14ac9e8720bee4a61571644134668 /gcc | |
| parent | ccbe9ffca8a6f16e5248b693d1f4307604e2ad41 (diff) | |
| download | gcc-39950dff997d3a75c807c1339ccf7bb4991e6104.zip gcc-39950dff997d3a75c807c1339ccf7bb4991e6104.tar.gz gcc-39950dff997d3a75c807c1339ccf7bb4991e6104.tar.bz2 | |
install EH code
From-SVN: r12567
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/arm.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ab9fbc1..c60f157 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1720,3 +1720,12 @@ do { \ arm_increase_location (4); \ ASM_OUTPUT_INT (FILE, XEXP (DECL_RTL (FUNCTION), 0)); \ } while (0) + +/* Used to mask out junk bits from the return address, such as + processor state, interrupt status, condition codes and the like. */ +#define MASK_RETURN_ADDR \ + /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ + in 26 bit mode, the condition codes must be masked out of the \ + return address. This does not apply to ARM6 and later processors \ + when running in 32 bit mode. */ \ + ((!TARGET_6) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff))) |