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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-21 14:54:33 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-21 16:25:11 +0800 |
| commit | 38048fc501b3d53fc38c701ae4625024cd93bd1d (patch) | |
| tree | 17a8c545e36df59cf0e0df4838589c5db0a19b4c /gcc | |
| parent | 4d80863d7f93c0a839d1fe5dc59be83153e89110 (diff) | |
| download | gcc-38048fc501b3d53fc38c701ae4625024cd93bd1d.zip gcc-38048fc501b3d53fc38c701ae4625024cd93bd1d.tar.gz gcc-38048fc501b3d53fc38c701ae4625024cd93bd1d.tar.bz2 | |
RISC-V: Fix SUBREG move of VLS mode[PR111486]
This patch fixes this bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111486
Before this patch, we can only handle (subreg:DI (reg:V8QI))
The PR ICE:
during RTL pass: reload
testcase.c: In function 'foo':
testcase.c:8:1: internal compiler error: in require, at machmode.h:313
8 | }
| ^
0xa40cd2 opt_mode<machine_mode>::require() const
/repo/gcc-trunk/gcc/machmode.h:313
0xa47091 opt_mode<machine_mode>::require() const
/repo/gcc-trunk/gcc/config/riscv/riscv.cc:2546
0xa47091 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
/repo/gcc-trunk/gcc/config/riscv/riscv.cc:2543
0x1f1df10 gen_movdi(rtx_def*, rtx_def*)
/repo/gcc-trunk/gcc/config/riscv/riscv.md:2024
0x10f1423 rtx_insn* insn_gen_fn::operator()<rtx_def*, rtx_def*>(rtx_def*, rtx_def*) const
/repo/gcc-trunk/gcc/recog.h:411
0x10f1423 emit_move_insn_1(rtx_def*, rtx_def*)
/repo/gcc-trunk/gcc/expr.cc:4164
0x10f183d emit_move_insn(rtx_def*, rtx_def*)
/repo/gcc-trunk/gcc/expr.cc:4334
0x13070ec lra_emit_move(rtx_def*, rtx_def*)
/repo/gcc-trunk/gcc/lra.cc:509
0x132295b curr_insn_transform
/repo/gcc-trunk/gcc/lra-constraints.cc:4748
0x1324335 lra_constraints(bool)
/repo/gcc-trunk/gcc/lra-constraints.cc:5488
0x130a3d4 lra(_IO_FILE*)
/repo/gcc-trunk/gcc/lra.cc:2419
0x12bb629 do_reload
/repo/gcc-trunk/gcc/ira.cc:5970
0x12bb629 execute
/repo/gcc-trunk/gcc/ira.cc:6156
Because of (subreg:DI (reg:V2QI))
PR target/111486
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Fix bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr111486.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c | 11 |
2 files changed, 13 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 29d439b..6158953 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2525,7 +2525,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) machine_mode vmode = GET_MODE (SUBREG_REG (src)); unsigned int mode_size = GET_MODE_SIZE (mode).to_constant (); unsigned int vmode_size = GET_MODE_SIZE (vmode).to_constant (); - unsigned int nunits = vmode_size / mode_size; + /* We should be able to handle both partial and paradoxical subreg. */ + unsigned int nunits = vmode_size > mode_size ? vmode_size / mode_size : 1; scalar_mode smode = as_a<scalar_mode> (mode); unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size; unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c new file mode 100644 index 0000000..2ba2a36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64iv -mabi=lp64d -O2" } */ + +typedef char __attribute__((__vector_size__ (1))) V; + +V +foo (V v, long x) +{ + x &= v[0]; + return v + (char) x; +} |