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| author | Richard Earnshaw <rearnsha@arm.com> | 2012-12-04 13:45:53 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2012-12-04 13:45:53 +0000 |
| commit | 37e33ecb8539a032b132b957c34bad2aeaf3f3e3 (patch) | |
| tree | 4355148a3b36b2c3946900b673737f2a79822b55 /gcc | |
| parent | 5c972fb605d1206903a8f448984553f2987f5834 (diff) | |
| download | gcc-37e33ecb8539a032b132b957c34bad2aeaf3f3e3.zip gcc-37e33ecb8539a032b132b957c34bad2aeaf3f3e3.tar.gz gcc-37e33ecb8539a032b132b957c34bad2aeaf3f3e3.tar.bz2 | |
arm.opt (cirrus-fix-invalid-insns): Delete option.
* arm.opt (cirrus-fix-invalid-insns): Delete option.
* invoke.texi (cirrus-fix-invalid-insns): Remove documentation.
From-SVN: r194137
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.opt | 4 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 13 |
3 files changed, 5 insertions, 17 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f1ffb241..4bd2082 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-12-04 Richard Earnshaw <rearnsha@arm.com> + + * arm.opt (cirrus-fix-invalid-insns): Delete option. + * invoke.texi (cirrus-fix-invalid-insns): Remove documentation. + 2012-12-04 Jakub Jelinek <jakub@redhat.com> * tsan.c (instrument_expr): If expr_ptr isn't a gimple val, first diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index fb12c55..61d2d2f 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -101,10 +101,6 @@ mcaller-super-interworking Target Report Mask(CALLER_INTERWORKING) Thumb: Assume function pointers may go to non-Thumb aware code -mcirrus-fix-invalid-insns -Target Report Mask(CIRRUS_FIX_INVALID_INSNS) -Cirrus: Place NOPs to avoid invalid instruction combinations - mcpu= Target RejectNegative Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none) Specify the name of the target CPU diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 51b6e85..4d917d1 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -506,7 +506,6 @@ Objective-C and Objective-C++ Dialects}. -msingle-pic-base -mno-single-pic-base @gol -mpic-register=@var{reg} @gol -mnop-fun-dllimport @gol --mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol -mpoke-function-name @gol -mthumb -marm @gol -mtpcs-frame -mtpcs-leaf-frame @gol @@ -11394,18 +11393,6 @@ before execution begins. Specify the register to be used for PIC addressing. The default is R10 unless stack-checking is enabled, when R9 is used. -@item -mcirrus-fix-invalid-insns -@opindex mcirrus-fix-invalid-insns -@opindex mno-cirrus-fix-invalid-insns -Insert NOPs into the instruction stream to in order to work around -problems with invalid Maverick instruction combinations. This option -is only valid if the @option{-mcpu=ep9312} option has been used to -enable generation of instructions for the Cirrus Maverick floating-point -co-processor. This option is not enabled by default, since the -problem is only present in older Maverick implementations. The default -can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns} -switch. - @item -mpoke-function-name @opindex mpoke-function-name Write the name of each function into the text section, directly |