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| author | Edwin Lu <ewlu@rivosinc.com> | 2023-08-21 15:20:24 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-08-21 15:20:24 -0600 |
| commit | 36788c9ff6d044210ddee23154306ba54bc3087b (patch) | |
| tree | 037269596ee8f9c6eb9ffd91d33baaa824fa38ac /gcc | |
| parent | b369f0ba87c1234722174ef0d32d873de30cb555 (diff) | |
| download | gcc-36788c9ff6d044210ddee23154306ba54bc3087b.zip gcc-36788c9ff6d044210ddee23154306ba54bc3087b.tar.gz gcc-36788c9ff6d044210ddee23154306ba54bc3087b.tar.bz2 | |
[PATCH] RISC-V: Add Types to Missing Bitmanip Instructions
This patch updates the bitmanip instructions to ensure that no insn is left
without a type attribute. Updates a total of 8 insns to have type "bitmanip"
Tested for regressions using rv32/64 multilib with newlib/linux.
gcc/Changelog:
* config/riscv/bitmanip.md: Added bitmanip type to insns
that are missing types.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index c42e7b8..0c99152 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -103,7 +103,8 @@ (match_dup 4)))] { operands[3] = GEN_INT (INTVAL (operands[3]) >> INTVAL (operands[2])); -}) +} +[(set_attr "type" "bitmanip")]) (define_insn "*shNadduw" [(set (match_operand:DI 0 "register_operand" "=r") @@ -533,7 +534,9 @@ "&& reload_completed" [(set (match_dup 3) (sign_extend:DI (match_dup 1))) (set (match_dup 4) (match_dup 2)) - (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))]) + (set (match_dup 0) (<minmax_optab>:DI (match_dup 3) (match_dup 4)))] + "" + [(set_attr "type" "bitmanip")]) ;; ZBS extension. @@ -628,7 +631,8 @@ operands[3] = GEN_INT (~bits | topbit); operands[4] = GEN_INT (~topbit); -}) +} +[(set_attr "type" "bitmanip")]) ;; In case of a paradoxical subreg, the sign bit and the high bits are ;; not allowed to be changed @@ -648,7 +652,8 @@ operands[3] = GEN_INT (~bits | topbit); operands[4] = GEN_INT (~topbit); -}) +} +[(set_attr "type" "bitmanip")]) (define_insn "*binv<mode>" [(set (match_operand:X 0 "register_operand" "=r") @@ -743,7 +748,8 @@ operands[3] = GEN_INT (bits &~ topbit); operands[4] = GEN_INT (topbit); -}) +} +[(set_attr "type" "bitmanip")]) ;; Same to use blcri + andi and blcri + bclri (define_insn_and_split "*andi<mode>_extrabit" @@ -761,7 +767,8 @@ operands[3] = GEN_INT (bits | topbit); operands[4] = GEN_INT (~topbit); -}) +} +[(set_attr "type" "bitmanip")]) ;; IF_THEN_ELSE: test for 2 bits of opposite polarity (define_insn_and_split "*branch<X:mode>_mask_twobits_equals_singlebit" @@ -803,7 +810,8 @@ operands[8] = GEN_INT (setbit); operands[9] = GEN_INT (clearbit); -}) +} +[(set_attr "type" "bitmanip")]) ;; IF_THEN_ELSE: test for (a & (1 << BIT_NO)) (define_insn_and_split "*branch<X:mode>_bext" @@ -826,7 +834,9 @@ (zero_extend:X (match_dup 3)))) (set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)]) (label_ref (match_dup 0)) - (pc)))]) + (pc)))] + "" + [(set_attr "type" "bitmanip")]) ;; ZBKC or ZBC extension (define_insn "riscv_clmul_<mode>" |