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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2015-01-19 14:03:23 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2015-01-19 14:03:23 +0000 |
| commit | 36650ec61912ff796651fa00964cb0f991c549a1 (patch) | |
| tree | db360384b9ebb2c312f5aa8bd887487889803643 /gcc | |
| parent | dfd3a76caecd5cea52ad04e0790165ba44742d59 (diff) | |
| download | gcc-36650ec61912ff796651fa00964cb0f991c549a1.zip gcc-36650ec61912ff796651fa00964cb0f991c549a1.tar.gz gcc-36650ec61912ff796651fa00964cb0f991c549a1.tar.bz2 | |
[AArch64] PR 64448: Combine ((x ^ y) & m) ^ x into bsl/bif instruction
PR target/64448
* config/aarch64/aarch64-simd.md (aarch64_simd_bsl<mode>_internal):
Match xor-and-xor RTL pattern.
From-SVN: r219843
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 15 |
2 files changed, 13 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 39758e7..605b87e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-01-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/64448 + * config/aarch64/aarch64-simd.md (aarch64_simd_bsl<mode>_internal): + Match xor-and-xor RTL pattern. + 2015-01-19 Igor Zamyatin <igor.zamyatin@intel.com> PR rtl-optimization/64081 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 968f5b2..d239884 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2008,15 +2008,14 @@ ;; bif op0, op1, mask (define_insn "aarch64_simd_bsl<mode>_internal" - [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") - (ior:VSDQ_I_DI + [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") + (xor:VSDQ_I_DI (and:VSDQ_I_DI - (not:<V_cmp_result> - (match_operand:<V_cmp_result> 1 "register_operand" " 0,w,w")) - (match_operand:VSDQ_I_DI 3 "register_operand" " w,0,w")) - (and:VSDQ_I_DI - (match_dup:<V_cmp_result> 1) - (match_operand:VSDQ_I_DI 2 "register_operand" " w,w,0")) + (xor:VSDQ_I_DI + (match_operand:<V_cmp_result> 3 "register_operand" "w,0,w") + (match_operand:VSDQ_I_DI 2 "register_operand" "w,w,0")) + (match_operand:VSDQ_I_DI 1 "register_operand" "0,w,w")) + (match_dup:<V_cmp_result> 3) ))] "TARGET_SIMD" "@ |