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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2022-10-06 12:09:28 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2022-10-06 12:09:28 +0100 |
| commit | 33b93ac3f2fb68a2da0d42fd692fe59533f7a84f (patch) | |
| tree | 3fa7370fdc7bf579f8f7c1869cd52a9636e08cbf /gcc | |
| parent | badd1ac23d24664b2258b1db4d49f37a3f60ccca (diff) | |
| download | gcc-33b93ac3f2fb68a2da0d42fd692fe59533f7a84f.zip gcc-33b93ac3f2fb68a2da0d42fd692fe59533f7a84f.tar.gz gcc-33b93ac3f2fb68a2da0d42fd692fe59533f7a84f.tar.bz2 | |
aarch64: Remove redundant zero-extends with LDAR
Like other loads in AArch64, the LDARB,LDARH,LDAR instructions clear out the top part of their
destination register and we can thus avoid having to explicitly zero-extend it.
We were missing a combine pattern that this patch adds.
For one of the examples in the testcase we generated:
load_uint8_t_ext_uint16_t:
adrp x0, .LANCHOR0
add x0, x0, :lo12:.LANCHOR0
ldarb w0, [x0]
and w0, w0, 255
ret
but now generate:
load_uint8_t_ext_uint16_t:
adrp x0, .LANCHOR0
add x0, x0, :lo12:.LANCHOR0
ldarb w0, [x0]
ret
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/ChangeLog:
* config/aarch64/atomics.md (*atomic_load<ALLX:mode>_zext<SD_HSDI:mode>):
New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ldar_2.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/atomics.md | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ldar_2.c | 27 |
2 files changed, 44 insertions, 0 deletions
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 9048700..bc95f6d 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -640,6 +640,23 @@ } ) +(define_insn "*atomic_load<ALLX:mode>_zext<SD_HSDI:mode>" + [(set (match_operand:SD_HSDI 0 "register_operand" "=r") + (zero_extend:SD_HSDI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDA)))] + "GET_MODE_SIZE (<SD_HSDI:MODE>mode) > GET_MODE_SIZE (<ALLX:MODE>mode)" + { + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model)) + return "ldr<ALLX:atomic_sfx>\t%<ALLX:w>0, %1"; + else + return "ldar<ALLX:atomic_sfx>\t%<ALLX:w>0, %1"; + } +) + (define_insn "atomic_load<mode>" [(set (match_operand:ALLI 0 "register_operand" "=r") (unspec_volatile:ALLI diff --git a/gcc/testsuite/gcc.target/aarch64/ldar_2.c b/gcc/testsuite/gcc.target/aarch64/ldar_2.c new file mode 100644 index 0000000..60b0717 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldar_2.c @@ -0,0 +1,27 @@ +/* Test that the zero-extending patterns for LDAR are used. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <stdint.h> + +uint8_t v_uint8_t; +uint16_t v_uint16_t; +uint32_t v_uint32_t; +uint64_t v_uint64_t; + +#define FUNC(FROM, TO) \ +TO \ +load_##FROM##_ext_##TO (void) \ +{ \ + return __atomic_load_n (&v_##FROM, __ATOMIC_ACQUIRE); \ +} + +FUNC (uint8_t, uint16_t) +FUNC (uint8_t, uint32_t) +FUNC (uint8_t, uint64_t) +FUNC (uint16_t, uint32_t) +FUNC (uint16_t, uint64_t) +FUNC (uint32_t, uint64_t) + +/* { dg-final { scan-assembler-not {and\tw[0-9+], w[0-9]+, 255} } } */ +/* { dg-final { scan-assembler-not {uxtw\tx[0-9+], w[0-9]+} } } */ |