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| author | Kito Cheng <kito.cheng@sifive.com> | 2021-09-16 22:19:44 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2021-10-25 17:06:46 +0800 |
| commit | 3329d892eb603fbe4e7c393f19d35739fe400a22 (patch) | |
| tree | 335547d808fdbb57a0ea443cdf4a04237f2dab0b /gcc | |
| parent | e596a283e54bdb0b4a0cebc128f9d9ac268e3916 (diff) | |
| download | gcc-3329d892eb603fbe4e7c393f19d35739fe400a22.zip gcc-3329d892eb603fbe4e7c393f19d35739fe400a22.tar.gz gcc-3329d892eb603fbe4e7c393f19d35739fe400a22.tar.bz2 | |
RISC-V: Cost model for zbb extension.
2021-10-25 Kito Cheng <kito.cheng@sifive.com>
gcc/ChangeLog:
* config/riscv/riscv.c (riscv_extend_cost): Handle cost model
for zbb extension.
(riscv_rtx_costs): Ditto.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index dec31c0..cb93e3f 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1707,6 +1707,16 @@ riscv_extend_cost (rtx op, bool unsigned_p) if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode) return COSTS_N_INSNS (1); + /* ZBB provide zext.h, sext.b and sext.h. */ + if (TARGET_ZBB) + { + if (!unsigned_p && GET_MODE (op) == QImode) + return COSTS_N_INSNS (1); + + if (GET_MODE (op) == HImode) + return COSTS_N_INSNS (1); + } + if (!unsigned_p && GET_MODE (op) == SImode) /* We can use SEXT.W. */ return COSTS_N_INSNS (1); @@ -1797,6 +1807,13 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN gcc_fallthrough (); case IOR: case XOR: + /* orn, andn and xorn pattern for zbb. */ + if (TARGET_ZBB + && GET_CODE (XEXP (x, 0)) == NOT) + { + *total = riscv_binary_cost (x, 1, 2); + return true; + } /* Double-word operations use two single-word operations. */ *total = riscv_binary_cost (x, 1, 2); return false; |