[AArch64, 4/6] Enable BTI: Add new <type> to -mbranch-protection.

This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.

This pass updates the CLI of -mbranch-protection to add "bti" as a new
type of branch protection and also add it its definition of "none" and
"standard". The option does not really do anything functional.
The functional changes are in the next patch. I am initializing the target
variable aarch64_enable_bti to 2 since I am also adding a configure option
in a later patch and a value different from 0 and 1 would help identify if its
already been updated.

*** gcc/ChangeLog ***

2018-01-09  Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Declare.
	* config/aarch64/aarch64.c (aarch64_handle_no_branch_protection):
	Disable bti for -mbranch-protection=none.
	(aarch64_handle_standard_branch_protection): Enable bti for
	-mbranch-protection=standard.
	(aarch64_handle_bti_protection): Enable bti for "bti" in the string to
	-mbranch-protection.
	(aarch64_bti_enabled): Check if bti is enabled.
	* config/aarch64/aarch64.opt: Declare target variable.
	* doc/invoke.texi: Add bti to the -mbranch-protection documentation.

From-SVN: r267768

5 files changed, 36 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bd065bc..0bc3675 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,18 @@
 2018-01-09  Sudakshina Das  <sudi.das@arm.com>
 
+	* config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Declare.
+	* config/aarch64/aarch64.c (aarch64_handle_no_branch_protection):
+	Disable bti for -mbranch-protection=none.
+	(aarch64_handle_standard_branch_protection): Enable bti for
+	-mbranch-protection=standard.
+	(aarch64_handle_bti_protection): Enable bti for "bti" in the string to
+	-mbranch-protection.
+	(aarch64_bti_enabled): Check if bti is enabled.
+	* config/aarch64/aarch64.opt: Declare target variable.
+	* doc/invoke.texi: Add bti to the -mbranch-protection documentation.
+
+2018-01-09  Sudakshina Das  <sudi.das@arm.com>
+
 	* config/aarch64/aarch64.c (aarch64_expand_prologue): Use new
 	epilogue/prologue scratch registers EP0_REGNUM and EP1_REGNUM.
 	(aarch64_expand_epilogue): Likewise.
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 209c09b..3e3ad14 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -521,6 +521,7 @@ void aarch64_register_pragmas (void);
 void aarch64_relayout_simd_types (void);
 void aarch64_reset_previous_fndecl (void);
 bool aarch64_return_address_signing_enabled (void);
+bool aarch64_bti_enabled (void);
 void aarch64_save_restore_target_globals (tree);
 void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
 				 rtx *, rtx *,
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 152875d..47569b8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1200,6 +1200,7 @@ static enum aarch64_parse_opt_result
 aarch64_handle_no_branch_protection (char* str, char* rest)
 {
   aarch64_ra_sign_scope = AARCH64_FUNCTION_NONE;
+  aarch64_enable_bti = 0;
   if (rest)
     {
       error ("unexpected %<%s%> after %<%s%>", rest, str);
@@ -1212,6 +1213,7 @@ static enum aarch64_parse_opt_result
 aarch64_handle_standard_branch_protection (char* str, char* rest)
 {
   aarch64_ra_sign_scope = AARCH64_FUNCTION_NON_LEAF;
+  aarch64_enable_bti = 1;
   if (rest)
     {
       error ("unexpected %<%s%> after %<%s%>", rest, str);
@@ -1236,6 +1238,14 @@ aarch64_handle_pac_ret_leaf (char* str ATTRIBUTE_UNUSED,
   return AARCH64_PARSE_OK;
 }
 
+static enum aarch64_parse_opt_result
+aarch64_handle_bti_protection (char* str ATTRIBUTE_UNUSED,
+				    char* rest ATTRIBUTE_UNUSED)
+{
+  aarch64_enable_bti = 1;
+  return AARCH64_PARSE_OK;
+}
+
 static const struct aarch64_branch_protect_type aarch64_pac_ret_subtypes[] = {
   { "leaf", aarch64_handle_pac_ret_leaf, NULL, 0 },
   { NULL, NULL, NULL, 0 }
@@ -1246,6 +1256,7 @@ static const struct aarch64_branch_protect_type aarch64_branch_protect_types[] =
   { "standard", aarch64_handle_standard_branch_protection, NULL, 0 },
   { "pac-ret", aarch64_handle_pac_ret_protection, aarch64_pac_ret_subtypes,
     ARRAY_SIZE (aarch64_pac_ret_subtypes) },
+  { "bti", aarch64_handle_bti_protection, NULL, 0 },
   { NULL, NULL, NULL, 0 }
 };
 
@@ -4725,6 +4736,13 @@ aarch64_return_address_signing_enabled (void)
 	      && cfun->machine->frame.reg_offset[LR_REGNUM] >= 0));
 }
 
+/* Return TRUE if Branch Target Identification Mechanism is enabled.  */
+bool
+aarch64_bti_enabled (void)
+{
+  return (aarch64_enable_bti == 1);
+}
+
 /* Emit code to save the callee-saved registers from register number START
    to LIMIT to the stack at the location starting at offset START_OFFSET,
    skipping any write-back candidates if SKIP_WB is true.  */
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 69a5103..6de7b22 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -33,6 +33,9 @@ const char *x_aarch64_override_tune_string
 TargetVariable
 unsigned long aarch64_isa_flags = 0
 
+TargetVariable
+unsigned aarch64_enable_bti = 2
+
 ; The TLS dialect names to use with -mtls-dialect.
 
 Enum
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c7c80f7..56649bf 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -15757,6 +15757,7 @@ level: signing functions that save the return address to memory (non-leaf
 functions will practically always do this) using the a-key.  The optional
 argument @samp{leaf} can be used to extend the signing to include leaf
 functions.
+@samp{bti} turns on branch target identification mechanism.
 
 @item -msve-vector-bits=@var{bits}
 @opindex msve-vector-bits