Fix PR target/43154

From-SVN: r157074

7 files changed, 91 insertions, 19 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e586327..307b0a8 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2010-02-25  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/43154
+	* config/rs6000/vector.md (VEC_64): New iterator for V2DF, V2DI.
+	(vec_interleave_high<mode>): Rename from vec_interleave_highv2df
+	and support both V2DF and V2DI modes.
+	(vec_interleave_low<mode>): Rename from vec_interleave_lowv2df and
+	support both V2DF and V2DI modes.
+	(general): Delete trailing whitespace from a few patterns.
+
+	* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
+	V2DF/V2DI interleave high/low builtins.
+
+	* config/rs6000/rs6000-builtin.def (VSX_BUILTIN_VEC_MERGE*): Add
+	new VSX builtins.
+
+	* config/rs6000/rs6000.c (bdesc_2arg): Add support for V2DF/V2DI
+	interleave high/low functions.
+
 2010-02-25  Gerald Pfeifer  <gerald@pfeifer.com>
 
 	* doc/extend.texi (Symbol-Renaming Pragmas): Fix spelling of
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index f5ad348..e66e8c4 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -955,6 +955,10 @@ RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DF,		RS6000_BTC_CONST)
 RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DI,		RS6000_BTC_CONST)
 RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DF,		RS6000_BTC_CONST)
 RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DI,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DF,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DI,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DF,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DI,		RS6000_BTC_CONST)
 
 /* VSX overloaded builtins, add the overloaded functions not present in
    Altivec.  */
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index da5a360..3bb6049 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1372,6 +1372,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
@@ -1416,6 +1420,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index af26bf1..7bcc086 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8950,6 +8950,10 @@ static struct builtin_description bdesc_2arg[] =
   { MASK_VSX, CODE_FOR_vsx_xxmrghw_v4si, "__builtin_vsx_xxmrghw_4si", VSX_BUILTIN_XXMRGHW_4SI },
   { MASK_VSX, CODE_FOR_vsx_xxmrglw_v4sf, "__builtin_vsx_xxmrglw", VSX_BUILTIN_XXMRGLW_4SF },
   { MASK_VSX, CODE_FOR_vsx_xxmrglw_v4si, "__builtin_vsx_xxmrglw_4si", VSX_BUILTIN_XXMRGLW_4SI },
+  { MASK_VSX, CODE_FOR_vec_interleave_lowv2df, "__builtin_vsx_mergel_2df", VSX_BUILTIN_VEC_MERGEL_V2DF },
+  { MASK_VSX, CODE_FOR_vec_interleave_lowv2di, "__builtin_vsx_mergel_2di", VSX_BUILTIN_VEC_MERGEL_V2DI },
+  { MASK_VSX, CODE_FOR_vec_interleave_highv2df, "__builtin_vsx_mergeh_2df", VSX_BUILTIN_VEC_MERGEH_V2DF },
+  { MASK_VSX, CODE_FOR_vec_interleave_highv2di, "__builtin_vsx_mergeh_2di", VSX_BUILTIN_VEC_MERGEH_V2DI },
 
   { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
   { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index d078597..d66f141 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -51,6 +51,9 @@
 ;; Vector init/extract modes
 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
 
+;; Vector modes for 64-bit base types
+(define_mode_iterator VEC_64 [V2DI V2DF])
+
 ;; Vector reload iterator
 (define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
 
@@ -480,7 +483,7 @@
 	(eq:SI (reg:CC 74)
 	       (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
-  "")	
+  "")
 
 (define_expand "cr6_test_for_zero_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -533,7 +536,7 @@
         (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
   "")
-  
+
 (define_expand "nor<mode>3"
   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
         (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
@@ -668,24 +671,24 @@
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
   "")
 
-(define_expand "vec_interleave_highv2df"
-  [(set (match_operand:V2DF 0 "vfloat_operand" "")
-	(vec_concat:V2DF
-	 (vec_select:DF (match_operand:V2DF 1 "vfloat_operand" "")
-			(parallel [(const_int 0)]))
-	 (vec_select:DF (match_operand:V2DF 2 "vfloat_operand" "")
-			(parallel [(const_int 0)]))))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
+(define_expand "vec_interleave_high<mode>"
+  [(set (match_operand:VEC_64 0 "vfloat_operand" "")
+	(vec_concat:VEC_64
+	 (vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
+				(parallel [(const_int 0)]))
+	 (vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
+				(parallel [(const_int 0)]))))]
+  "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "")
 
-(define_expand "vec_interleave_lowv2df"
-  [(set (match_operand:V2DF 0 "vfloat_operand" "")
-	(vec_concat:V2DF
-	 (vec_select:DF (match_operand:V2DF 1 "vfloat_operand" "")
-			(parallel [(const_int 1)]))
-	 (vec_select:DF (match_operand:V2DF 2 "vfloat_operand" "")
-			(parallel [(const_int 1)]))))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
+(define_expand "vec_interleave_low<mode>"
+  [(set (match_operand:VEC_64 0 "vfloat_operand" "")
+	(vec_concat:VEC_64
+	 (vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
+				(parallel [(const_int 1)]))
+	 (vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
+				(parallel [(const_int 1)]))))]
+  "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "")
 
 
@@ -889,7 +892,7 @@
   rtx insn;
   HOST_WIDE_INT bitshift_val;
   HOST_WIDE_INT byteshift_val;
- 
+
   if (! CONSTANT_P (bitshift))
     FAIL;
   bitshift_val = INTVAL (bitshift);
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c3fbe66..d65d0e0 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2010-02-25  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	PR target/43154
+	* gcc.target/powerpc/pr43154.c: New file.
+
 2010-02-25  Jakub Jelinek  <jakub@redhat.com>
 
 	PR debug/43166
diff --git a/gcc/testsuite/gcc.target/powerpc/pr43154.c b/gcc/testsuite/gcc.target/powerpc/pr43154.c
new file mode 100644
index 0000000..d083e97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr43154.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Make sure that vec_mergel and vec_mergeh are supported for V2DF/V2DI types.  */
+/* { dg-final { scan-assembler-times "xxpermdi" 4 } } */
+
+#include <altivec.h>
+
+void vec_high_v2df (vector double *a, vector double *b, vector double *c)
+{
+  *a = vec_mergeh (*b, *c);
+}
+
+void vec_low_v2df (vector double *a, vector double *b, vector double *c)
+{
+  *a = vec_mergel (*b, *c);
+}
+
+void vec_high_v2di (vector long long *a, vector long long *b, vector long long *c)
+{
+  *a = vec_mergeh (*b, *c);
+}
+
+void vec_low_v2di (vector long long *a, vector long long *b, vector long long *c)
+{
+  *a = vec_mergel (*b, *c);
+}