RISC-V: Implement ZBKB, ZBKC and ZBKX extensions

This patch supports Zkbk, Zbkc and Zkbx extension.
It includes instruction's machine description and built-in funtions.
It is worth mentioning that this patch only adds instructions in Zbkb but no
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code
generator instead of built-in functions.

gcc/ChangeLog:

	* config/riscv/bitmanip.md: Add ZBKB's instructions.
	* config/riscv/riscv-builtins.cc (AVAIL): Add new.
	* config/riscv/riscv.md: Add new type for crypto instructions.
	* config/riscv/crypto.md: Add Scalar Cryptography extension's machine
	description file.
	* config/riscv/riscv-scalar-crypto.def: Add Scalar Cryptography
	extension's built-in function file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbkb32.c: New test.
	* gcc.target/riscv/zbkb64.c: New test.
	* gcc.target/riscv/zbkc32.c: New test.
	* gcc.target/riscv/zbkc64.c: New test.
	* gcc.target/riscv/zbkx32.c: New test.
	* gcc.target/riscv/zbkx64.c: New test.

Co-Authored-By: SiYu Wu <siyu@isrc.iscas.ac.cn>

11 files changed, 327 insertions, 11 deletions

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index cfdb9eb..ff9ecb4 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
                             (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "<insn>n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -203,7 +203,7 @@
 			       (const_int 0)))
 		(match_operand:DI 2 "register_operand")))
    (clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
    (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
                       (match_operand:X 2 "register_operand" "r"))))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "ror%i2\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -293,7 +293,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 				     (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rorw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -301,7 +301,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rol%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -309,7 +309,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotate:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rol\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -317,7 +317,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
 				   (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rolw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -332,7 +332,7 @@
 (define_insn "bswap<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bswap:X (match_operand:X 1 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rev8\t%0,%1"
   [(set_attr "type" "bitmanip")])
 
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 0000000..a270036
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,128 @@
+;; Machine description for RISC-V Scalar Cryptography extensions.
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+    ;; Zbkb unspecs
+    UNSPEC_BREV8
+    UNSPEC_ZIP
+    UNSPEC_UNZIP
+    UNSPEC_PACK
+    UNSPEC_PACKH
+    UNSPEC_PACKW
+
+    ;; Zbkc unspecs
+    UNSPEC_CLMUL
+    UNSPEC_CLMULH
+
+    ;; Zbkx unspecs
+    UNSPEC_XPERM8
+    UNSPEC_XPERM4
+])
+
+;; ZBKB extension
+(define_insn "riscv_brev8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_BREV8))]
+  "TARGET_ZBKB"
+  "brev8\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_zip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_ZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "zip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_unzip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_UNZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "unzip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_pack_<X:mode><HISI:mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:HISI 1 "register_operand" "r")
+                  (match_operand:HISI 2 "register_operand" "r")]
+                  UNSPEC_PACK))]
+  "TARGET_ZBKB"
+  "pack\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:QI 1 "register_operand" "r")
+                  (match_operand:QI 2 "register_operand" "r")]
+                  UNSPEC_PACKH))]
+  "TARGET_ZBKB"
+  "packh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:HI 1 "register_operand" "r")
+                  (match_operand:HI 2 "register_operand" "r")]
+                  UNSPEC_PACKW))]
+  "TARGET_ZBKB && TARGET_64BIT"
+  "packw\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKC extension
+
+(define_insn "riscv_clmul_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMUL))]
+  "TARGET_ZBKC"
+  "clmul\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_clmulh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMULH))]
+  "TARGET_ZBKC"
+  "clmulh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKX extension
+
+(define_insn "riscv_xperm4_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM4))]
+  "TARGET_ZBKX"
+  "xperm4\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_xperm8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM8))]
+  "TARGET_ZBKX"
+  "xperm8\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index ded91e1..f0d6070 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -100,6 +100,12 @@ AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
+AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
+AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
+AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
+AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
+AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
@@ -153,6 +159,7 @@ AVAIL (always,     (!0))
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
+  #include "riscv-scalar-crypto.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
new file mode 100644
index 0000000..e4c97ac
--- /dev/null
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -0,0 +1,45 @@
+/* Builtin functions for RISC-V Scalar Cryptography extensions.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+// ZBKB
+RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32),
+RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64),
+
+RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32),
+RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64),
+
+RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64),
+
+RISCV_BUILTIN (zip, "zip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (unzip, "unzip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+
+RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64),
+
+// ZBKC
+RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+
+// ZBKX
+RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 20697b8..6c31760 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -242,6 +242,7 @@
 ;; bitmanip	bit manipulation instructions
 ;; rotate   rotation instructions
 ;; atomic   atomic instructions
+;; crypto cryptography instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
 ;; rdvlenb     vector byte length vlenb csrr read
 ;; rdvl        vector length vl csrr read
@@ -338,7 +339,7 @@
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
-   atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
    vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
@@ -3092,6 +3093,7 @@
 )
 
 (include "bitmanip.md")
+(include "crypto.md")
 (include "sync.md")
 (include "peephole.md")
 (include "pic.md")
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c
new file mode 100644
index 0000000..dd45b8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint-gcc.h>
+
+int32_t foo1(int16_t rs1, int16_t rs2)
+{
+    return __builtin_riscv_pack(rs1, rs2);
+}
+
+int32_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __builtin_riscv_packh(rs1, rs2);
+}
+
+int32_t foo3(int32_t rs1)
+{
+    return __builtin_riscv_brev8(rs1);
+}
+
+int32_t foo4(int32_t rs1)
+{
+    return __builtin_riscv_zip(rs1);
+}
+
+int32_t foo5(int32_t rs1)
+{
+    return __builtin_riscv_unzip(rs1);
+}
+
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "\tzip\t" 1 } } */
+/* { dg-final { scan-assembler-times "unzip" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c
new file mode 100644
index 0000000..960a2ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include <stdint-gcc.h>
+
+int64_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_pack(rs1, rs2);
+}
+
+int64_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __builtin_riscv_packh(rs1, rs2);
+}
+
+int64_t foo3(int16_t rs1, int16_t rs2)
+{
+    return __builtin_riscv_packw(rs1, rs2);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_brev8(rs1);
+}
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "packw" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c
new file mode 100644
index 0000000..a8e2920
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include <stdint-gcc.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_clmul(rs1, rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c
new file mode 100644
index 0000000..728f8ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include <stdint-gcc.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_clmul(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c
new file mode 100644
index 0000000..bd95524
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint-gcc.h>
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c
new file mode 100644
index 0000000..2a04a94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint-gcc.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */