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| author | Ian Bolton <ian.bolton@arm.com> | 2013-10-03 09:50:21 +0000 |
|---|---|---|
| committer | Marcus Shawcroft <mshawcroft@gcc.gnu.org> | 2013-10-03 09:50:21 +0000 |
| commit | 2ab8f063e9957882ce55f8585694a140486eae03 (patch) | |
| tree | 8c0c1ea1f730ced6af571ea1425fb3f1bb590526 /gcc | |
| parent | 79221839a3c9c0e8a4cf5ea130bcf24062ee3995 (diff) | |
| download | gcc-2ab8f063e9957882ce55f8585694a140486eae03.zip gcc-2ab8f063e9957882ce55f8585694a140486eae03.tar.gz gcc-2ab8f063e9957882ce55f8585694a140486eae03.tar.bz2 | |
[AArch64] Remove un-necessary secondary reload for addition to SP.
From-SVN: r203156
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 14 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 32 |
3 files changed, 6 insertions, 46 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1a3aff5..002b761 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-10-03 Ian Bolton <ian.bolton@arm.com> + + * config/aarch64/aarch64.c (aarch64_secondary_reload): Remove legacy + code. + * config/aarch64/aarch64.md (reload_sp_immediate): Likewise. + 2013-10-02 Teresa Johnson <tejohnson@google.com> * predict.c (probably_never_executed): New function. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ff61cd4..f6f587a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4028,20 +4028,6 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, enum machine_mode mode, secondary_reload_info *sri) { - /* Address expressions of the form PLUS (SP, large_offset) need two - scratch registers, one for the constant, and one for holding a - copy of SP, since SP cannot be used on the RHS of an add-reg - instruction. */ - if (mode == DImode - && GET_CODE (x) == PLUS - && XEXP (x, 0) == stack_pointer_rtx - && CONST_INT_P (XEXP (x, 1)) - && !aarch64_uimm12_shift (INTVAL (XEXP (x, 1)))) - { - sri->icode = CODE_FOR_reload_sp_immediate; - return NO_REGS; - } - /* Without the TARGET_SIMD instructions we cannot move a Q register to a Q register directly. We need a scratch. */ if (REG_P (x) && (mode == TFmode || mode == TImode) && mode == GET_MODE (x) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 797c9f4..830bbee 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3955,38 +3955,6 @@ ;; Reload support ;; ------------------------------------------------------------------- -;; Reload SP+imm where imm cannot be handled by a single ADD instruction. -;; Must load imm into a scratch register and copy SP to the dest reg before -;; adding, since SP cannot be used as a source register in an ADD -;; instruction. -(define_expand "reload_sp_immediate" - [(parallel [(set (match_operand:DI 0 "register_operand" "=r") - (match_operand:DI 1 "" "")) - (clobber (match_operand:TI 2 "register_operand" "=&r"))])] - "" - { - rtx sp = XEXP (operands[1], 0); - rtx val = XEXP (operands[1], 1); - unsigned regno = REGNO (operands[2]); - rtx scratch = operands[1]; - gcc_assert (GET_CODE (operands[1]) == PLUS); - gcc_assert (sp == stack_pointer_rtx); - gcc_assert (CONST_INT_P (val)); - - /* It is possible that one of the registers we got for operands[2] - might coincide with that of operands[0] (which is why we made - it TImode). Pick the other one to use as our scratch. */ - if (regno == REGNO (operands[0])) - regno++; - scratch = gen_rtx_REG (DImode, regno); - - emit_move_insn (scratch, val); - emit_move_insn (operands[0], sp); - emit_insn (gen_adddi3 (operands[0], operands[0], scratch)); - DONE; - } -) - (define_expand "aarch64_reload_mov<mode>" [(set (match_operand:TX 0 "register_operand" "=w") (match_operand:TX 1 "register_operand" "w")) |