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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-10-13 13:45:19 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-10-13 14:03:31 +0800 |
| commit | 2a89656a03282c0fe80c5467c6891c067ae0007a (patch) | |
| tree | 7ee49fa75678e52d9852018f649950444d11592b /gcc | |
| parent | d53d20a940efe4262f18ac3da870eb972dcf84f0 (diff) | |
| download | gcc-2a89656a03282c0fe80c5467c6891c067ae0007a.zip gcc-2a89656a03282c0fe80c5467c6891c067ae0007a.tar.gz gcc-2a89656a03282c0fe80c5467c6891c067ae0007a.tar.bz2 | |
RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV
Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index b348526..f63b42a 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2) /* Disable for SVE because for long or variable-length vectors we don't get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD, because there we can vectorize the epilogue using mixed vector sizes. - Likewise for AMD GCN. */ -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */ + Likewise for AMD GCN and RVV. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */ |