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| author | H.J. Lu <hongjiu.lu@intel.com> | 2010-11-03 21:16:36 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2010-11-03 14:16:36 -0700 |
| commit | 27835a8a5c5105350bd88cdb8eaa391638622264 (patch) | |
| tree | 1f335722cb977dc011454ea6940a31930e4d369f /gcc | |
| parent | 576e00858c8b8d6d9477fd44e8b210ab25b6de69 (diff) | |
| download | gcc-27835a8a5c5105350bd88cdb8eaa391638622264.zip gcc-27835a8a5c5105350bd88cdb8eaa391638622264.tar.gz gcc-27835a8a5c5105350bd88cdb8eaa391638622264.tar.bz2 | |
Set use_avx256_p if 256bit AVX register is used in vector move.
gcc/
2010-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR target/46295
* config/i386/i386.c (ix86_expand_vector_move): Set use_avx256_p
if 256bit AVX register is used.
gcc/testsuite/
2010-11-03 H.J. Lu <hongjiu.lu@intel.com>
PR target/46295
* gcc.target/i386/pr46295.c: New.
From-SVN: r166277
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr46295.c | 15 |
4 files changed, 29 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5c6387e..87d9bc4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2010-11-03 H.J. Lu <hongjiu.lu@intel.com> + + PR target/46295 + * config/i386/i386.c (ix86_expand_vector_move): Set use_avx256_p + if 256bit AVX register is used. + 2010-11-03 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support to use diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index ba1e4fc..3558899 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15144,6 +15144,9 @@ ix86_expand_vector_move (enum machine_mode mode, rtx operands[]) rtx op0 = operands[0], op1 = operands[1]; unsigned int align = GET_MODE_ALIGNMENT (mode); + if (use_avx256_p (mode, NULL_TREE)) + cfun->machine->use_avx256_p = true; + /* Force constants other than zero into memory. We do not know how the instructions used to build constants modify the upper 64 bits of the register, once we have that information we may be able diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 206798d..a602ecf 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2010-11-03 H.J. Lu <hongjiu.lu@intel.com> + + PR target/46295 + * gcc.target/i386/pr46295.c: New. + 2010-11-03 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/vsx-sfminmax.c: New test for using double diff --git a/gcc/testsuite/gcc.target/i386/pr46295.c b/gcc/testsuite/gcc.target/i386/pr46295.c new file mode 100644 index 0000000..219f34e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr46295.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mtune=generic -dp" } */ + +typedef double EXPRESS[5]; +void Parse_Rel_Factor (EXPRESS Express,int *Terms); +void Parse_Vector () +{ + EXPRESS Express; + int Terms; + for (Terms = 0; Terms < 5; Terms++) + Express[Terms] = 0.0; + Parse_Rel_Factor(Express,&Terms); +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ |