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| author | John David Anglin <danglin@gcc.gnu.org> | 2024-02-03 15:43:00 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2024-02-03 15:44:29 +0000 |
| commit | 266354012e0aa42e0d1639ee7708595f316cc36b (patch) | |
| tree | b0555e71ee01d304a7fc5ec0a89b4077bbf1211a /gcc | |
| parent | 78005c648921899a674d1e561b49b05ccabedfe0 (diff) | |
| download | gcc-266354012e0aa42e0d1639ee7708595f316cc36b.zip gcc-266354012e0aa42e0d1639ee7708595f316cc36b.tar.gz gcc-266354012e0aa42e0d1639ee7708595f316cc36b.tar.bz2 | |
libatomic: Provide FPU exception defines for __hppa__
The exception defines in <fenv.h> do not match the exception bits
in the FPU status register on hppa-linux and hppa64-hpux11.11. On
linux, they match the trap enable bits. On 64-bit hpux, they match
the exception bits for IA64. The IA64 bits are in a different
order and location than HPPA. HP uses table look ups to reorder
the bits in code to test and raise exceptions.
All the architectures that I looked at just pass the FPU status
register to __atomic_feraiseexcept(). The simplest approach for
hppa is to define FE_INEXACT, etc, to match the status register
and not include <fenv.h>..
2024-02-03 John David Anglin <danglin@gcc.gnu.org>
libatomic/ChangeLog:
PR target/59778
* configure.tgt (hppa*): Set ARCH.
* config/pa/fenv.c: New file.
Diffstat (limited to 'gcc')
0 files changed, 0 insertions, 0 deletions