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| author | Vladimir Makarov <vmakarov@redhat.com> | 2004-07-07 15:11:42 +0000 |
|---|---|---|
| committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 2004-07-07 15:11:42 +0000 |
| commit | 25069b4269e2fd8ca3ec7fc14fe9552ec97c0f42 (patch) | |
| tree | f250ae8d0b2110f5451c60e43dfb4fbb39b1156f /gcc | |
| parent | 767dec6b106a8c3f99826670bd2429c71728bfea (diff) | |
| download | gcc-25069b4269e2fd8ca3ec7fc14fe9552ec97c0f42.zip gcc-25069b4269e2fd8ca3ec7fc14fe9552ec97c0f42.tar.gz gcc-25069b4269e2fd8ca3ec7fc14fe9552ec97c0f42.tar.bz2 | |
re PR target/16130 (Gcc 3.4 ICE on valid code)
2004-07-07 Vladimir Makarov <vmakarov@redhat.com>
PR target/16130
PR target/16142
PR target/16143
* config/ia64/ia64.c (ia64_dfa_new_cycle): Reset DFA state for asm
insn.
From-SVN: r84202
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.c | 14 |
2 files changed, 18 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 35a65f6..e563543 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2004-07-07 Vladimir Makarov <vmakarov@redhat.com> + + PR target/16130 + PR target/16142 + PR target/16143 + * config/ia64/ia64.c (ia64_dfa_new_cycle): Reset DFA state for asm + insn. + 2004-07-06 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> PR target/1679. diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 3195422..b8e3345 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -6326,10 +6326,16 @@ ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock, } else if (reload_completed) setup_clocks_p = TRUE; - memcpy (curr_state, prev_cycle_state, dfa_state_size); - state_transition (curr_state, dfa_stop_insn); - state_transition (curr_state, dfa_pre_cycle_insn); - state_transition (curr_state, NULL); + if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT + || asm_noperands (PATTERN (last_scheduled_insn)) >= 0) + state_reset (curr_state); + else + { + memcpy (curr_state, prev_cycle_state, dfa_state_size); + state_transition (curr_state, dfa_stop_insn); + state_transition (curr_state, dfa_pre_cycle_insn); + state_transition (curr_state, NULL); + } } else if (reload_completed) setup_clocks_p = TRUE; |