diff options
| author | liuhongt <hongtao.liu@intel.com> | 2021-09-13 10:27:51 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-09-15 16:38:14 +0800 |
| commit | 243e0a5b1942879bc005bf150a744e69a4fcdc87 (patch) | |
| tree | f3db1a05a53f0d5fb8564a2490812ea8fa84735f /gcc | |
| parent | 8b69c481fc86e04c6c83f3a49eef2760c175a8f2 (diff) | |
| download | gcc-243e0a5b1942879bc005bf150a744e69a4fcdc87.zip gcc-243e0a5b1942879bc005bf150a744e69a4fcdc87.tar.gz gcc-243e0a5b1942879bc005bf150a744e69a4fcdc87.tar.bz2 | |
Output vextract{i,f}{32x4,64x2} for (vec_select:(reg:Vmode) idx) when byte_offset of idx % 16 == 0.
2020-09-13 Hongtao Liu <hongtao.liu@intel.com>
Peter Cordes <peter@cordes.ca>
gcc/ChangeLog:
PR target/91103
* config/i386/sse.md (extract_suf): Add V8SF/V8SI/V4DF/V4DI.
(*vec_extract<mode><ssescalarmodelower>_valign): Output
vextract{i,f}{32x4,64x2} instruction when byte_offset % 16 ==
0.
gcc/testsuite/ChangeLog:
PR target/91103
* gcc.target/i386/pr91103-1.c: Add extract tests.
* gcc.target/i386/pr91103-2.c: Ditto.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/sse.md | 21 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr91103-1.c | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr91103-2.c | 4 |
3 files changed, 27 insertions, 5 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b67ec15..1564539 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -9089,7 +9089,8 @@ [(V16SF "avx512f") (V16SI "avx512f") (V8DF "avx512dq") (V8DI "avx512dq")]) (define_mode_attr extract_suf - [(V16SF "32x4") (V16SI "32x4") (V8DF "64x2") (V8DI "64x2")]) + [(V16SF "32x4") (V16SI "32x4") (V8DF "64x2") (V8DI "64x2") + (V8SF "32x4") (V8SI "32x4") (V4DF "64x2") (V4DI "64x2")]) (define_mode_iterator AVX512_VEC [(V8DF "TARGET_AVX512DQ") (V8DI "TARGET_AVX512DQ") V16SF V16SI]) @@ -10661,9 +10662,21 @@ (match_operand:V48_256_512_AVX512VL 1 "register_operand" "v") (parallel [(match_operand 2 "<vec_extract_imm_predicate>")])))] "TARGET_AVX512F - && INTVAL(operands[2]) >= 16 / GET_MODE_SIZE (<ssescalarmode>mode)" - "valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}"; - [(set_attr "prefix" "evex") + && INTVAL(operands[2]) * GET_MODE_SIZE (<ssescalarmode>mode) >= 16" +{ + int byte_offset = INTVAL (operands[2]) * GET_MODE_SIZE (<ssescalarmode>mode); + if (byte_offset % 16 == 0) + { + operands[2] = GEN_INT (byte_offset / 16); + if (byte_offset / 16 == 1) + return "vextract<shuffletype><extract_suf>\t{%2, %t1, %x0|%x0, %t1, %2}"; + else + return "vextract<shuffletype><extract_suf>\t{%2, %1, %x0|%x0, %1, %2}"; + } + else + return "valign<ternlogsuffix>\t{%2, %1, %1, %<xtg_mode>0|%<xtg_mode>0, %1, %1, %2}"; +} + [(set_attr "prefix" "maybe_evex") (set_attr "mode" "<sseintvecinsnmode>")]) (define_expand "avx512f_shufps512_mask" diff --git a/gcc/testsuite/gcc.target/i386/pr91103-1.c b/gcc/testsuite/gcc.target/i386/pr91103-1.c index 11caaa8..2d78a6d 100644 --- a/gcc/testsuite/gcc.target/i386/pr91103-1.c +++ b/gcc/testsuite/gcc.target/i386/pr91103-1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512vl -O2" } */ -/* { dg-final { scan-assembler-times "valign\[dq\]" 16 } } */ +/* { dg-final { scan-assembler-times "valign\[dq\]" 8 } } */ +/* { dg-final { scan-assembler-times "vextract" 12 } } */ typedef float v8sf __attribute__((vector_size(32))); typedef float v16sf __attribute__((vector_size(64))); @@ -23,9 +24,13 @@ EXTRACT (v8sf, float, 4); EXTRACT (v8sf, float, 7); EXTRACT (v8si, int, 4); EXTRACT (v8si, int, 7); +EXTRACT (v16sf, float, 4); EXTRACT (v16sf, float, 8); +EXTRACT (v16sf, float, 12); EXTRACT (v16sf, float, 15); +EXTRACT (v16si, int, 4); EXTRACT (v16si, int, 8); +EXTRACT (v16si, int, 12); EXTRACT (v16si, int, 15); EXTRACT (v4df, double, 2); EXTRACT (v4df, double, 3); diff --git a/gcc/testsuite/gcc.target/i386/pr91103-2.c b/gcc/testsuite/gcc.target/i386/pr91103-2.c index 010e477..a928d87 100644 --- a/gcc/testsuite/gcc.target/i386/pr91103-2.c +++ b/gcc/testsuite/gcc.target/i386/pr91103-2.c @@ -61,9 +61,13 @@ RUNCHECK (f2, v8sf, float, 4); RUNCHECK (f2, v8sf, float, 7); RUNCHECK (di2, v8si, int, 4); RUNCHECK (di2, v8si, int, 7); +RUNCHECK (f1, v16sf, float, 4); RUNCHECK (f1, v16sf, float, 8); +RUNCHECK (f1, v16sf, float, 12); RUNCHECK (f1, v16sf, float, 15); +RUNCHECK (di1, v16si, int, 4); RUNCHECK (di1, v16si, int, 8); +RUNCHECK (di1, v16si, int, 12); RUNCHECK (di1, v16si, int, 15); RUNCHECK (d2, v4df, double, 2); RUNCHECK (d2, v4df, double, 3); |