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author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-10-10 22:24:02 +0200 |
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committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-11-18 21:15:24 +0100 |
commit | 23d9f62c50d935462ecda5516746037a474c25cd (patch) | |
tree | 4841223248fdc3d43760442184b90938c3cf59f4 /gcc | |
parent | 11543b27fe16d81ca5483ecb98ec7a5b2426e0c0 (diff) | |
download | gcc-23d9f62c50d935462ecda5516746037a474c25cd.zip gcc-23d9f62c50d935462ecda5516746037a474c25cd.tar.gz gcc-23d9f62c50d935462ecda5516746037a474c25cd.tar.bz2 |
RISC-V: allow bseti on SImode without sign-extension
As long as the SImode operand is not a partial subreg, we can use a
bseti without postprocessing to or in a bit, as the middle end is
smart enough to stay away from the signbit.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*bsetidisi): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bseti-02.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/bitmanip.md | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c | 25 |
2 files changed, 37 insertions, 0 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 2175c62..2e7142c 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -350,6 +350,18 @@ "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) +;; As long as the SImode operand is not a partial subreg, we can use a +;; bseti without postprocessing, as the middle end is smart enough to +;; stay away from the signbit. +(define_insn "*bsetidisi" + [(set (match_operand:DI 0 "register_operand" "=r") + (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "single_bit_mask_operand" "i")))] + "TARGET_ZBS && TARGET_64BIT + && !partial_subreg_p (operands[2])" + "bseti\t%0,%1,%S2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bclr<mode>" [(set (match_operand:X 0 "register_operand" "=r") (and:X (rotate:X (const_int -2) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c new file mode 100644 index 0000000..d362994 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +/* bexti */ +int f(int* a, int b) +{ + return ((*a << b) | (1 << 14)); +} + +int g(int a, int b) +{ + return ((a + b)| (1 << 30)); +} + +int h(int a, int b) +{ + return ((a + b)| (1ULL << 33)); +} + +/* { dg-final { scan-assembler-times "addw\t" 2 } } */ +/* { dg-final { scan-assembler-times "sllw\t" 1 } } */ +/* { dg-final { scan-assembler-times "bseti\t" 2 } } */ +/* { dg-final { scan-assembler-not "sext.w\t" } } */ + |