diff options
| author | Richard Sandiford <rsandifo@redhat.com> | 2004-08-23 07:13:13 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2004-08-23 07:13:13 +0000 |
| commit | 2222da3a18cdb5d8885fe3a05008f8283ad8fc65 (patch) | |
| tree | e49b5c8a491bc8c6a14c6a5996bd4cc7b49a253f /gcc | |
| parent | 15ac4ccfb45f27788e027d00316475d6c79f77ed (diff) | |
| download | gcc-2222da3a18cdb5d8885fe3a05008f8283ad8fc65.zip gcc-2222da3a18cdb5d8885fe3a05008f8283ad8fc65.tar.gz gcc-2222da3a18cdb5d8885fe3a05008f8283ad8fc65.tar.bz2 | |
* config/mips/mips.md ({,u}divmod[sd]i4): Redefine using :GPR.
From-SVN: r86408
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 64 |
2 files changed, 24 insertions, 44 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dfcf820..f0ee4cb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2004-08-23 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md ({,u}divmod[sd]i4): Redefine using :GPR. + +2004-08-23 Richard Sandiford <rsandifo@redhat.com> + * config/mips/mips.md (any_extend): New code macro. (u, su): New code attributes. ({,u}mulsidi3, {,u}mulsidi3_32bit_internal, {,u}mulsidi3_32bit_r4000) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index cecd282..65622e93 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1827,53 +1827,29 @@ ;; VR4120 errata MD(A1): signed division instructions do not work correctly ;; with negative operands. We use special libgcc functions instead. -(define_insn "divmodsi4" - [(set (match_operand:SI 0 "register_operand" "=l") - (div:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))) - (set (match_operand:SI 3 "register_operand" "=h") - (mod:SI (match_dup 1) - (match_dup 2)))] +(define_insn "divmod<mode>4" + [(set (match_operand:GPR 0 "register_operand" "=l") + (div:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d"))) + (set (match_operand:GPR 3 "register_operand" "=h") + (mod:GPR (match_dup 1) + (match_dup 2)))] "!TARGET_FIX_VR4120" - { return mips_output_division ("div\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "SI")]) - -(define_insn "divmoddi4" - [(set (match_operand:DI 0 "register_operand" "=l") - (div:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))) - (set (match_operand:DI 3 "register_operand" "=h") - (mod:DI (match_dup 1) - (match_dup 2)))] - "TARGET_64BIT && !TARGET_FIX_VR4120" - { return mips_output_division ("ddiv\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "DI")]) + { return mips_output_division ("<d>div\t$0,%1,%2", operands); } + [(set_attr "type" "idiv") + (set_attr "mode" "<MODE>")]) -(define_insn "udivmodsi4" - [(set (match_operand:SI 0 "register_operand" "=l") - (udiv:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "register_operand" "d"))) - (set (match_operand:SI 3 "register_operand" "=h") - (umod:SI (match_dup 1) - (match_dup 2)))] +(define_insn "udivmod<mode>4" + [(set (match_operand:GPR 0 "register_operand" "=l") + (udiv:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d"))) + (set (match_operand:GPR 3 "register_operand" "=h") + (umod:GPR (match_dup 1) + (match_dup 2)))] "" - { return mips_output_division ("divu\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "SI")]) - -(define_insn "udivmoddi4" - [(set (match_operand:DI 0 "register_operand" "=l") - (udiv:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:DI 2 "register_operand" "d"))) - (set (match_operand:DI 3 "register_operand" "=h") - (umod:DI (match_dup 1) - (match_dup 2)))] - "TARGET_64BIT" - { return mips_output_division ("ddivu\t$0,%1,%2", operands); } - [(set_attr "type" "idiv") - (set_attr "mode" "DI")]) + { return mips_output_division ("<d>divu\t$0,%1,%2", operands); } + [(set_attr "type" "idiv") + (set_attr "mode" "<MODE>")]) ;; ;; .................... |