Merge commit '4f01ae3761ca1f8dd7a33b833ae30624f047ac9c^' into HEAD

590 files changed, 15198 insertions, 3879 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0dcae8c..a82f00f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,1167 @@
+2023-06-21  Uros Bizjak  <ubizjak@gmail.com>
+
+	* function.h (emit_initial_value_sets):
+	Change return type from int to void.
+	(aggregate_value_p): Change return type from int to bool.
+	(prologue_contains): Ditto.
+	(epilogue_contains): Ditto.
+	(prologue_epilogue_contains): Ditto.
+	* function.cc (temp_slot): Make "in_use" variable bool.
+	(make_slot_available): Update for changed "in_use" variable.
+	(assign_stack_temp_for_type): Ditto.
+	(emit_initial_value_sets): Change return type from int to void
+	and update function body accordingly.
+	(instantiate_virtual_regs): Ditto.
+	(rest_of_handle_thread_prologue_and_epilogue): Ditto.
+	(safe_insn_predicate): Change return type from int to bool.
+	(aggregate_value_p): Change return type from int to bool
+	and update function body accordingly.
+	(prologue_contains): Change return type from int to bool.
+	(prologue_epilogue_contains): Ditto.
+
+2023-06-21  Alexander Monakov  <amonakov@ispras.ru>
+
+	* common.opt (fp_contract_mode) [on]: Remove fallback.
+	* config/sh/sh.md (*fmasf4): Correct flag_fp_contract_mode test.
+	* doc/invoke.texi (-ffp-contract): Update.
+	* trans-mem.cc (diagnose_tm_1): Skip internal function calls.
+
+2023-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
+	Add alternatives to prefer to avoid same input and output Z register.
+	(mask_gather_load<mode><v_int_container>): Likewise.
+	(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
+	(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
+	(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
+	Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
+	Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_sxtw): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
+	<VNx4_NARROW:mode>): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_uxtw): Likewise.
+	* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
+	(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
+	<SVE_PARTIAL_I:mode>): Likewise.
+
+2023-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
+	Convert to compact alternatives syntax.
+	(mask_gather_load<mode><v_int_container>): Likewise.
+	(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
+	(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
+	(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
+	Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
+	Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_sxtw): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
+	<VNx4_NARROW:mode>): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_uxtw): Likewise.
+	* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
+	(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
+	<SVE_PARTIAL_I:mode>): Likewise.
+
+2023-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	Revert:
+	2023-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
+	Convert to compact alternatives syntax.
+	(mask_gather_load<mode><v_int_container>): Likewise.
+	(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
+	(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
+	(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
+	Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
+	Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_sxtw): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
+	<VNx4_NARROW:mode>): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_uxtw): Likewise.
+	* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
+	(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
+	<SVE_PARTIAL_I:mode>): Likewise.
+
+2023-06-21  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+	* optabs-query.cc (can_vec_mask_load_store_p): Move to optabs-tree.cc.
+	(get_len_load_store_mode): Ditto.
+	* optabs-query.h (can_vec_mask_load_store_p): Move to optabs-tree.h.
+	(get_len_load_store_mode): Ditto.
+	* optabs-tree.cc (can_vec_mask_load_store_p): New function.
+	(get_len_load_store_mode): Ditto.
+	* optabs-tree.h (can_vec_mask_load_store_p): Ditto.
+	(get_len_load_store_mode): Ditto.
+	* tree-if-conv.cc: include optabs-tree instead of optabs-query
+
+2023-06-21  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-loop-ivopts.cc (add_iv_candidate_for_use): Use
+	split_constant_offset for the POINTER_PLUS_EXPR case.
+
+2023-06-21  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-loop-ivopts.cc (record_group_use): Use
+	split_constant_offset.
+
+2023-06-21  Richard Biener  <rguenther@suse.de>
+
+	* tree-loop-distribution.cc (classify_builtin_st): Use
+	split_constant_offset.
+	* tree-ssa-loop-ivopts.h (strip_offset): Remove.
+	* tree-ssa-loop-ivopts.cc (strip_offset): Make static.
+
+2023-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
+	Convert to compact alternatives syntax.
+	(mask_gather_load<mode><v_int_container>): Likewise.
+	(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
+	(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
+	(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
+	Likewise.
+	(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
+	Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_sxtw): Likewise.
+	(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
+	<SVE_2BHSI:mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(@aarch64_ldff1_gather<mode>): Likewise.
+	(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
+	<VNx4_NARROW:mode>): Likewise.
+	(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_sxtw): Likewise.
+	(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
+	<VNx2_NARROW:mode>_uxtw): Likewise.
+	* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
+	(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
+	<SVE_PARTIAL_I:mode>): Likewise.
+
+2023-06-21  Tamar Christina  <tamar.christina@arm.com>
+
+	PR other/110329
+	* doc/md.texi: Replace backslashchar.
+
+2023-06-21  Richard Biener  <rguenther@suse.de>
+
+	* config/i386/i386.cc (ix86_vector_costs::finish_cost):
+	Overload.  For masked main loops make sure the vectorization
+	factor isn't more than double the number of iterations.
+
+2023-06-21  Jan Beulich  <jbeulich@suse.com>
+
+	* config/i386/i386-expand.cc (ix86_expand_copysign): Request
+	value duplication by ix86_build_signbit_mask() when AVX512F and
+	not HFmode.
+	* config/i386/sse.md (*<avx512>_vternlog<mode>_all): Convert to
+	2-alternative form. Adjust "mode" attribute. Add "enabled"
+	attribute.
+	(*<avx512>_vpternlog<mode>_1): Also permit when TARGET_AVX512F
+	&& !TARGET_PREFER_AVX256.
+	(*<avx512>_vpternlog<mode>_2): Likewise.
+	(*<avx512>_vpternlog<mode>_3): Likewise.
+
+2023-06-21  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/110018
+	* tree-vect-stmts.cc (vectorizable_conversion): Use
+	intermiediate integer type for float_expr/fix_trunc_expr when
+	direct optab is not existed.
+
+2023-06-20  Tamar Christina  <tamar.christina@arm.com>
+
+	PR bootstrap/110324
+	* gensupport.cc (convert_syntax): Explicitly check for RTX code.
+
+2023-06-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.md (stack_tie): Hard-code the first
+	register operand to the stack pointer.  Require the second register
+	operand to have the number specified in a separate const_int operand.
+	* config/aarch64/aarch64.cc (aarch64_emit_stack_tie): New function.
+	(aarch64_allocate_and_probe_stack_space): Use it.
+	(aarch64_expand_prologue, aarch64_expand_epilogue): Likewise.
+	(aarch64_expand_epilogue): Likewise.
+
+2023-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/79173
+	* tree-ssa-math-opts.cc (match_uaddc_usubc): Remember lhs of
+	IMAGPART_EXPR of arg2/arg3 and use that as arg3 if it has the right
+	type.
+
+2023-06-20  Uros Bizjak  <ubizjak@gmail.com>
+
+	* calls.h (setjmp_call_p): Change return type from int to bool.
+	* calls.cc (struct arg_data): Change "pass_on_stack" to bool.
+	(store_one_arg): Change return type from int to bool
+	and adjust function body accordingly.  Change "sibcall_failure"
+	variable to bool.
+	(finalize_must_preallocate): Ditto.  Change *must_preallocate pointer
+	argument  to bool.  Change "partial_seen" variable to bool.
+	(load_register_parameters):  Change *sibcall_failure
+	pointer argument to bool.
+	(check_sibcall_argument_overlap_1): Change return type from int to bool
+	and adjust function body accordingly.
+	(check_sibcall_argument_overlap):  Ditto.  Change
+	"mark_stored_args_map" argument to bool.
+	(emit_call_1): Change "already_popped" variable to bool.
+	(setjmp_call_p): Change return type from int to bool
+	and adjust function body accordingly.
+	(initialize_argument_information): Change *must_preallocate
+	pointer argument to bool.
+	(expand_call): Change "pcc_struct_value", "must_preallocate"
+	and "sibcall_failure" variables to bool.
+	(emit_library_call_value_1): Change "pcc_struct_value"
+	variable to bool.
+
+2023-06-20  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/110276
+	* ipa-sra.cc (struct caller_issues): New field there_is_one.
+	(check_for_caller_issues): Set it.
+	(check_all_callers_for_issues): Check it.
+
+2023-06-20  Martin Jambor  <mjambor@suse.cz>
+
+	* ipa-prop.h (ipa_uid_to_idx_map_elt): New type.
+	(struct ipcp_transformation): Rearrange members	according to
+	C++ class coding convention, add m_uid_to_idx,
+	get_param_index and maybe_create_parm_idx_map.
+	* ipa-cp.cc (ipcp_transformation::get_param_index): New function.
+	(compare_uids): Likewise.
+	(ipcp_transformation::maype_create_parm_idx_map): Likewise.
+	* ipa-prop.cc (ipcp_get_parm_bits): Use get_param_index.
+	(ipcp_update_bits): Accept TS as a parameter, assume it is not NULL.
+	(ipcp_update_vr): Likewise.
+	(ipcp_transform_function): Call, maybe_create_parm_idx_map of TS, bail
+	out quickly if empty, pass it to ipcp_update_bits and ipcp_update_vr.
+
+2023-06-20  Carl Love  <cel@us.ibm.com>
+
+	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin):
+	Rename CODE_FOR_xsxsigqp_tf to CODE_FOR_xsxsigqp_tf_ti.
+	Rename CODE_FOR_xsxsigqp_kf to CODE_FOR_xsxsigqp_kf_ti.
+	Rename CCDE_FOR_xsxexpqp_tf to CODE_FOR_xsxexpqp_tf_di.
+	Rename CODE_FOR_xsxexpqp_kf to CODE_FOR_xsxexpqp_kf_di.
+	(CODE_FOR_xsxexpqp_kf_v2di, CODE_FOR_xsxsigqp_kf_v1ti,
+	CODE_FOR_xsiexpqp_kf_v2di): Add case statements.
+	* config/rs6000/rs6000-builtins.def
+	(__builtin_vsx_scalar_extract_exp_to_vec,
+	__builtin_vsx_scalar_extract_sig_to_vec,
+	__builtin_vsx_scalar_insert_exp_vqp): Add new builtin definitions.
+	Rename xsxexpqp_kf, xsxsigqp_kf, xsiexpqp_kf to xsexpqp_kf_di,
+	xsxsigqp_kf_ti, xsiexpqp_kf_di respectively.
+	* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
+	Update case RS6000_OVLD_VEC_VSIE to handle MODE_VECTOR_INT for new
+	overloaded instance. Update comments.
+	* config/rs6000/rs6000-overload.def
+	(__builtin_vec_scalar_insert_exp): Add new overload definition with
+	vector arguments.
+	(scalar_extract_exp_to_vec, scalar_extract_sig_to_vec): New
+	overloaded definitions.
+	* config/rs6000/vsx.md (V2DI_DI): New mode iterator.
+	(DI_to_TI): New mode attribute.
+	Rename xsxexpqp_<mode> to sxexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
+	Rename xsxsigqp_<mode> to xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>.
+	Rename xsiexpqp_<mode> to xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
+	* doc/extend.texi (scalar_extract_exp_to_vec,
+	scalar_extract_sig_to_vec): Add documentation for new builtins.
+	(scalar_insert_exp): Add new overloaded builtin definition.
+
+2023-06-20  Li Xu  <xuli1@eswincomputing.com>
+
+	* config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural
+	size of vector mask mode to one rvv register.
+
+2023-06-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* config/riscv/riscv-v.cc (expand_const_vector): Optimize codegen.
+
+2023-06-20  Lehua Ding  <lehua.ding@rivai.ai>
+
+	* config/riscv/riscv.cc (riscv_arg_has_vector): Add default
+	switch handler.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-dse.cc (dse_classify_store): When we found
+	no defs and the basic-block with the original definition
+	ends in __builtin_unreachable[_trap] the store is dead.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	* tree-ssa-phiprop.cc (phiprop_insert_phi): For simple loads
+	keep the virtual SSA form up-to-date.
+
+2023-06-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd.md (*aarch64_addp_same_reg<mode>):
+	New define_insn_and_split.
+
+2023-06-20  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64.md (*mov<mode>_aarch64): Drop test comment.
+
+2023-06-20  Jan Beulich  <jbeulich@suse.com>
+
+	* config/i386/sse.md (vec_dupv2di): Correct %vmovddup input
+	constraint. Add new AVX512F alternative.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	PR debug/110295
+	* dwarf2out.cc (process_scope_var): Continue processing
+	the decl after setting a parent in case the existing DIE
+	was in limbo.
+
+2023-06-20  Lehua Ding  <lehua.ding@rivai.ai>
+
+	* config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
+	(riscv_arg_has_vector): Simplify.
+	(riscv_pass_in_vector_p): Adjust warning message.
+
+2023-06-19  Jin Ma  <jinma@linux.alibaba.com>
+
+	* config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR.
+	(riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions.
+	* config/riscv/riscv.md (riscv_frcsr): New patterns.
+	(riscv_fscsr): Likewise.
+
+2023-06-19  Toru Kisuki  <tkisuki@tachyum.com>
+
+	PR rtl-optimization/110305
+	* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
+	Handle HONOR_SNANS for x + 0.0.
+
+2023-06-19  Jan Hubicka  <jh@suse.cz>
+
+	PR tree-optimization/109811
+	PR tree-optimization/109849
+	* passes.def: Add phiprop to early optimization passes.
+	* tree-ssa-phiprop.cc: Allow clonning.
+
+2023-06-19  Tamar Christina  <tamar.christina@arm.com>
+
+	* config/aarch64/aarch64.md (arches): Add nosimd.
+	(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Rewrite to
+	compact syntax.
+
+2023-06-19  Tamar Christina  <tamar.christina@arm.com>
+	    Omar Tahir  <Omar.Tahir2@arm.com>
+
+	* gensupport.cc (class conlist, add_constraints, add_attributes,
+	skip_spaces, expect_char, preprocess_compact_syntax,
+	parse_section_layout, parse_section, convert_syntax): New.
+	(process_rtx): Check for conversion.
+	* genoutput.cc (process_template): Check for unresolved iterators.
+	(class data): Add compact_syntax_p.
+	(gen_insn): Use it.
+	* gensupport.h (compact_syntax): New.
+	(hash-set.h): Include.
+	* doc/md.texi: Document it.
+
+2023-06-19  Uros Bizjak  <ubizjak@gmail.com>
+
+	* recog.h (check_asm_operands): Change return type from int to bool.
+	(insn_invalid_p): Ditto.
+	(verify_changes): Ditto.
+	(apply_change_group): Ditto.
+	(constrain_operands): Ditto.
+	(constrain_operands_cached): Ditto.
+	(validate_replace_rtx_subexp): Ditto.
+	(validate_replace_rtx): Ditto.
+	(validate_replace_rtx_part): Ditto.
+	(validate_replace_rtx_part_nosimplify): Ditto.
+	(added_clobbers_hard_reg_p): Ditto.
+	(peep2_regno_dead_p): Ditto.
+	(peep2_reg_dead_p): Ditto.
+	(store_data_bypass_p): Ditto.
+	(if_test_bypass_p): Ditto.
+	* rtl.h (split_all_insns_noflow): Change
+	return type from unsigned int to void.
+	* genemit.cc (output_added_clobbers_hard_reg_p): Change return type
+	of generated added_clobbers_hard_reg_p from int to bool and adjust
+	function body accordingly.  Change "used" variable type from
+	int to bool.
+	* recog.cc (check_asm_operands): Change return type
+	from int to bool and adjust function body accordingly.
+	(insn_invalid_p): Ditto.  Change "is_asm" variable to bool.
+	(verify_changes): Change return type from int to bool.
+	(apply_change_group): Change return type from int to bool
+	and adjust function body accordingly.
+	(validate_replace_rtx_subexp): Change return type from int to bool.
+	(validate_replace_rtx): Ditto.
+	(validate_replace_rtx_part): Ditto.
+	(validate_replace_rtx_part_nosimplify): Ditto.
+	(constrain_operands_cached): Ditto.
+	(constrain_operands): Ditto.  Change "lose" and "win"
+	variables type from int to bool.
+	(split_all_insns_noflow): Change return type from unsigned int
+	to void and adjust function body accordingly.
+	(peep2_regno_dead_p): Change return type from int to bool.
+	(peep2_reg_dead_p): Ditto.
+	(peep2_find_free_register): Change "success"
+	variable type from int to bool
+	(store_data_bypass_p_1): Change return type from int to bool.
+	(store_data_bypass_p): Ditto.
+
+2023-06-19  Li Xu  <xuli1@eswincomputing.com>
+
+	* config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the
+	Zve32f extension.
+
+2023-06-19  Pan Li  <pan2.li@intel.com>
+
+	PR target/110299
+	* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
+	modes.
+	* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
+	VWLMUL1_ZVE32, VI_ZVE64, VI_ZVE32, VWI, VWI_ZVE64, VWI_ZVE32,
+	VF_ZVE63 and VF_ZVE32.
+	* config/riscv/vector.md
+	(@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Removed.
+	(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
+	(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>): Ditto.
+	(@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
+	(@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
+	(@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): New pattern.
+	(@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Ditto.
+	(@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Ditto.
+	(@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Ditto.
+	(@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Ditto.
+
+2023-06-19  Pan Li  <pan2.li@intel.com>
+
+	PR target/110277
+	* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
+	ret_mode.
+	* config/riscv/vector-iterators.md: Add VHF, VSF, VDF,
+	VHF_LMUL1, VSF_LMUL1, VDF_LMUL1, and remove unused attr.
+	* config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): Removed.
+	(@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
+	(@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
+	(@pred_reduc_plus<order><mode><vlmul1>): Ditto.
+	(@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
+	(@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
+	(@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): New pattern.
+	(@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Ditto.
+	(@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Ditto.
+	(@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Ditto.
+	(@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Ditto.
+	(@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Ditto.
+
+2023-06-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn.cc (gcn_expand_divmod_libfunc): New function.
+	(gcn_init_libfuncs): Add div and mod functions for all modes.
+	Add placeholders for divmod functions.
+	(TARGET_EXPAND_DIVMOD_LIBFUNC): Define.
+
+2023-06-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* tree-vect-generic.cc: Include optabs-libfuncs.h.
+	(get_compute_type): Check optab_libfunc.
+	* tree-vect-stmts.cc: Include optabs-libfuncs.h.
+	(vectorizable_operation): Check optab_libfunc.
+
+2023-06-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn-protos.h (vgpr_4reg_mode_p): New function.
+	* config/gcn/gcn-valu.md (V_4REG, V_4REG_ALT): New iterators.
+	(V_MOV, V_MOV_ALT): Likewise.
+	(scalar_mode, SCALAR_MODE): Add TImode.
+	(vnsi, VnSI, vndi, VnDI): Likewise.
+	(vec_merge, vec_merge_with_clobber, vec_merge_with_vcc): Use V_MOV.
+	(mov<mode>, mov<mode>_unspec): Use V_MOV.
+	(*mov<mode>_4reg): New insn.
+	(mov<mode>_exec): New 4reg variant.
+	(mov<mode>_sgprbase): Likewise.
+	(reload_in<mode>, reload_out<mode>): Use V_MOV.
+	(vec_set<mode>): Likewise.
+	(vec_duplicate<mode><exec>): New 4reg variant.
+	(vec_extract<mode><scalar_mode>): Likewise.
+	(vec_extract<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
+	(vec_extract<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
+	(vec_extract<V_4REG:mode><V_4REG_ALT:mode>_nop): New 4reg variant.
+	(fold_extract_last_<mode>): Use V_MOV.
+	(vec_init<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
+	(vec_init<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
+	(gather_load<mode><vnsi>, gather<mode>_expr<exec>,
+	gather<mode>_insn_1offset<exec>, gather<mode>_insn_1offset_ds<exec>,
+	gather<mode>_insn_2offsets<exec>): Use V_MOV.
+	(scatter_store<mode><vnsi>, scatter<mode>_expr<exec_scatter>,
+	scatter<mode>_insn_1offset<exec_scatter>,
+	scatter<mode>_insn_1offset_ds<exec_scatter>,
+	scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
+	(maskload<mode>di, maskstore<mode>di, mask_gather_load<mode><vnsi>,
+	mask_scatter_store<mode><vnsi>): Likewise.
+	* config/gcn/gcn.cc (gcn_class_max_nregs): Use vgpr_4reg_mode_p.
+	(gcn_hard_regno_mode_ok): Likewise.
+	(GEN_VNM): Add TImode support.
+	(USE_TI): New macro. Separate TImode operations from non-TImode ones.
+	(gcn_vector_mode_supported_p): Add V64TImode, V32TImode, V16TImode,
+	V8TImode, and V2TImode.
+	(print_operand):  Add 'J' and 'K' print codes.
+
+2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110298
+	* tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely):
+	Clear number of iterations info before cleaning up the CFG.
+
+2023-06-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
+	Simplify vec_concat of lowpart subreg and high part vec_select.
+
+2023-06-19  Tobias Burnus  <tobias@codesourcery.com>
+
+	* doc/invoke.texi (-foffload-options): Remove '-O3' from the examples.
+
+2023-06-19  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
+	Handle null niters_skip.
+
+2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	* config/aarch64/aarch64.cc
+	(aarch64_vector_costs::analyze_loop_vinfo): Fix reference
+	to LOOP_VINFO_MASKS.
+
+2023-06-19  Senthil Kumar Selvaraj  <saaadhu@gcc.gnu.org>
+
+	PR target/105523
+	* common/config/avr/avr-common.cc: Remove setting
+	of OPT_fdelete_null_pointer_checks.
+	* config/avr/avr.cc (avr_option_override): Clear
+	flag_delete_null_pointer_checks if zero_address_valid.
+	(avr_addr_space_zero_address_valid): New function.
+	(TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Provide target
+	hook.
+
+2023-06-19  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+	    Robin Dapp  <rdapp.gcc@gmail.com>
+
+	* doc/md.texi: Add len_mask{load,store}.
+	* genopinit.cc (main): Ditto.
+	(CMP_NAME): Ditto.
+	* internal-fn.cc (len_maskload_direct): Ditto.
+	(len_maskstore_direct): Ditto.
+	(expand_call_mem_ref): Ditto.
+	(expand_partial_load_optab_fn): Ditto.
+	(expand_len_maskload_optab_fn): Ditto.
+	(expand_partial_store_optab_fn): Ditto.
+	(expand_len_maskstore_optab_fn): Ditto.
+	(direct_len_maskload_optab_supported_p): Ditto.
+	(direct_len_maskstore_optab_supported_p): Ditto.
+	* internal-fn.def (LEN_MASK_LOAD): Ditto.
+	(LEN_MASK_STORE): Ditto.
+	* optabs.def (OPTAB_CD): Ditto.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* config/riscv/autovec.md (<optab><mode>3): Implement binop
+	expander.
+	* config/riscv/riscv-protos.h (emit_vlmax_fp_insn): Declare.
+	(enum vxrm_field_enum): Rename this...
+	(enum fixed_point_rounding_mode): ...to this.
+	(enum frm_field_enum): Rename this...
+	(enum floating_point_rounding_mode): ...to this.
+	* config/riscv/riscv-v.cc (emit_vlmax_fp_insn): New function
+	* config/riscv/riscv.cc (riscv_const_insns): Clarify const
+	vector handling.
+	(riscv_libgcc_floating_mode_supported_p): Adjust comment.
+	(riscv_excess_precision): Do not convert to float for ZVFH.
+	* config/riscv/vector-iterators.md: Add VF_AUTO iterator.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* config/riscv/vector-iterators.md: Add VI_QH iterator.
+	* config/riscv/autovec-opt.md
+	(@pred_extract_first_sextdi<mode>): New vmv.x.s pattern
+	that includes sign extension.
+	(@pred_extract_first_sextsi<mode>): Dito for SImode.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* config/riscv/autovec.md (vec_set<mode>): Implement.
+	(vec_extract<mode><vel>): Implement.
+	* config/riscv/riscv-protos.h (enum insn_type): Add slide insn.
+	(emit_vlmax_slide_insn): Declare.
+	(emit_nonvlmax_slide_tu_insn): Declare.
+	(emit_scalar_move_insn): Export.
+	(emit_nonvlmax_integer_move_insn): Export.
+	* config/riscv/riscv-v.cc (emit_vlmax_slide_insn): New function.
+	(emit_nonvlmax_slide_tu_insn): New function.
+	(emit_vlmax_masked_mu_insn): No change.
+	(emit_vlmax_integer_move_insn): Export.
+
+2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	* tree-vectorizer.h (enum vect_partial_vector_style): New.
+	(_loop_vec_info::partial_vector_style): Likewise.
+	(LOOP_VINFO_PARTIAL_VECTORS_STYLE): Likewise.
+	(rgroup_controls::compare_type): Add.
+	(vec_loop_masks): Change from a typedef to auto_vec<>
+	to a structure.
+	* tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
+	Adjust.  Convert niters_skip to compare_type.
+	(vect_set_loop_condition_partial_vectors_avx512): New function
+	implementing the AVX512 partial vector codegen.
+	(vect_set_loop_condition): Dispatch to the correct
+	vect_set_loop_condition_partial_vectors_* function based on
+	LOOP_VINFO_PARTIAL_VECTORS_STYLE.
+	(vect_prepare_for_masked_peels): Compute LOOP_VINFO_MASK_SKIP_NITERS
+	in the original niter type.
+	* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
+	partial_vector_style.
+	(can_produce_all_loop_masks_p): Adjust.
+	(vect_verify_full_masking): Produce the rgroup_controls vector
+	here.  Set LOOP_VINFO_PARTIAL_VECTORS_STYLE on success.
+	(vect_verify_full_masking_avx512): New function implementing
+	verification of AVX512 style masking.
+	(vect_verify_loop_lens): Set LOOP_VINFO_PARTIAL_VECTORS_STYLE.
+	(vect_analyze_loop_2): Also try AVX512 style masking.
+	Adjust condition.
+	(vect_estimate_min_profitable_iters): Implement AVX512 style
+	mask producing cost.
+	(vect_record_loop_mask): Do not build the rgroup_controls
+	vector here but record masks in a hash-set.
+	(vect_get_loop_mask): Implement AVX512 style mask query,
+	complementing the existing while_ult style.
+
+2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	* tree-vectorizer.h (vect_get_loop_mask): Add loop_vec_info
+	argument.
+	* tree-vect-loop.cc (vect_get_loop_mask): Likewise.
+	(vectorize_fold_left_reduction): Adjust.
+	(vect_transform_reduction): Likewise.
+	(vectorizable_live_operation): Likewise.
+	* tree-vect-stmts.cc (vectorizable_call): Likewise.
+	(vectorizable_operation): Likewise.
+	(vectorizable_store): Likewise.
+	(vectorizable_load): Likewise.
+	(vectorizable_condition): Likewise.
+
+2023-06-19  Senthil Kumar Selvaraj  <saaadhu@gcc.gnu.org>
+
+	PR target/110086
+	* config/avr/avr.opt (mgas-isr-prologues, mmain-is-OS_task):
+	Add Optimization option property.
+
+2023-06-19  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+
+	* config/xtensa/xtensa.cc (xtensa_constantsynth_2insn):
+	Add new pattern for the abovementioned case.
+
+2023-06-19  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
+
+	* config/xtensa/xtensa.cc
+	(TARGET_MEMORY_MOVE_COST, xtensa_memory_move_cost): Remove.
+
+2023-06-19  Jiufu Guo  <guojiufu@linux.ibm.com>
+
+	* config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define.
+
+2023-06-19  Jiufu Guo  <guojiufu@linux.ibm.com>
+
+	* cse.cc (try_const_anchors): Check SCALAR_INT_MODE.
+
+2023-06-19  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/110235
+	* config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>):
+	Substitute with ..
+	(sse2_packsswb<mask_name>): .. this, ..
+	(avx2_packsswb<mask_name>): .. this and ..
+	(avx512bw_packsswb<mask_name>): .. this.
+	(<sse2_avx2>_packssdw<mask_name>): Substitute with ..
+	(sse2_packssdw<mask_name>): .. this, ..
+	(avx2_packssdw<mask_name>): .. this and ..
+	(avx512bw_packssdw<mask_name>): .. this.
+
+2023-06-19  liuhongt  <hongtao.liu@intel.com>
+
+	PR target/110235
+	* config/i386/i386-expand.cc (ix86_split_mmx_pack): Use
+	UNSPEC_US_TRUNCATE instead of original us_truncate for
+	packusdw/packuswb.
+	* config/i386/mmx.md (mmx_pack<s_trunsuffix>swb): Substitute
+	with ..
+	(mmx_packsswb): .. this and ..
+	(mmx_packuswb): .. this.
+	(mmx_packusdw): Use UNSPEC_US_TRUNCATE instead of original
+	us_truncate.
+	(s_trunsuffix): Removed code iterator.
+	(any_s_truncate): Ditto.
+	* config/i386/sse.md (<sse2_avx2>_packuswb<mask_name>): Use
+	UNSPEC_US_TRUNCATE instead of original us_truncate.
+	(<sse4_1_avx2>_packusdw<mask_name>): Ditto.
+	* config/i386/i386.md (UNSPEC_US_TRUNCATE): New unspec_c_enum.
+
+2023-06-18  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/riscv-vector-builtins-bases.cc: Fix one typo.
+
+2023-06-18  Uros Bizjak  <ubizjak@gmail.com>
+
+	* rtl.h (*rtx_equal_p_callback_function):
+	Change return type from int to bool.
+	(rtx_equal_p): Ditto.
+	(*hash_rtx_callback_function): Ditto.
+	* rtl.cc (rtx_equal_p): Change return type from int to bool
+	and adjust function body accordingly.
+	* early-remat.cc (scratch_equal): Ditto.
+	* sel-sched-ir.cc (skip_unspecs_callback): Ditto.
+	(hash_with_unspec_callback): Ditto.
+
+2023-06-18  Jeff Law  <jlaw@ventanamicro.com>
+
+	* config/arc/arc.md (movqi_insn): Allow certain constants to
+	be stored into memory in the pattern's condition.
+	(movsf_insn): Similarly.
+
+2023-06-18  Honza  <jh@ryzen3.suse.cz>
+
+	PR tree-optimization/109849
+	* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Add new parameter
+	ES; handle ipa_predicate::not_sra_candidate.
+	(evaluate_properties_for_edge): Pass es to
+	evaluate_conditions_for_known_args.
+	(ipa_fn_summary_t::duplicate): Handle sra candidates.
+	(dump_ipa_call_summary): Dump points_to_possible_sra_candidate.
+	(load_or_store_of_ptr_parameter): New function.
+	(points_to_possible_sra_candidate_p): New function.
+	(analyze_function_body): Initialize points_to_possible_sra_candidate;
+	determine sra predicates.
+	(estimate_ipcp_clone_size_and_time): Update call of
+	evaluate_conditions_for_known_args.
+	(remap_edge_params): Update points_to_possible_sra_candidate.
+	(read_ipa_call_summary): Stream points_to_possible_sra_candidate
+	(write_ipa_call_summary): Likewise.
+	* ipa-predicate.cc (ipa_predicate::add_clause): Handle not_sra_candidate.
+	(dump_condition): Dump it.
+	* ipa-predicate.h (struct inline_param_summary): Add
+	points_to_possible_sra_candidate.
+
+2023-06-18  Roger Sayle  <roger@nextmovesoftware.com>
+
+	* config/i386/i386-expand.cc (ix86_expand_carry): New helper
+	function for setting the carry flag.
+	(ix86_expand_builtin) <handlecarry>: Use it here.
+	* config/i386/i386-protos.h (ix86_expand_carry): Prototype here.
+	* config/i386/i386.md (uaddc<mode>5): Use ix86_expand_carry.
+	(usubc<mode>5): Likewise.
+
+2023-06-18  Roger Sayle  <roger@nextmovesoftware.com>
+
+	* config/i386/i386.md (*concat<mode><dwi>3_1): Use QImode
+	for the immediate constant shift count.
+	(*concat<mode><dwi>3_2): Likewise.
+	(*concat<mode><dwi>3_3): Likewise.
+	(*concat<mode><dwi>3_4): Likewise.
+	(*concat<mode><dwi>3_5): Likewise.
+	(*concat<mode><dwi>3_6): Likewise.
+
+2023-06-18  Uros Bizjak  <ubizjak@gmail.com>
+
+	* cse.cc (hash_rtx_cb): Rename to hash_rtx.
+	(hash_rtx): Remove.
+	* early-remat.cc (remat_candidate_hasher::equal): Update
+	to call rtx_equal_p with rtx_equal_p_callback_function argument.
+	* rtl.cc (rtx_equal_p_cb): Rename to rtx_equal_p.
+	(rtx_equal_p): Remove.
+	* rtl.h (rtx_equal_p): Add rtx_equal_p_callback_function
+	argument with NULL default value.
+	(rtx_equal_p_cb): Remove function declaration.
+	(hash_rtx_cb): Ditto.
+	(hash_rtx): Add hash_rtx_callback_function argument
+	with NULL default value.
+	* sel-sched-ir.cc (free_nop_pool): Update function comment.
+	(skip_unspecs_callback): Ditto.
+	(vinsn_init): Update to call hash_rtx with
+	hash_rtx_callback_function argument.
+	(vinsn_equal_p): Ditto.
+
+2023-06-18  yulong  <shiyulong@iscas.ac.cn>
+
+	* config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple.
+	* config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
+	(ADJUST_ALIGNMENT): Ditto.
+	(RVV_TUPLE_PARTIAL_MODES): Ditto.
+	(ADJUST_NUNITS): Ditto.
+	* config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t):
+	New types.
+	(vfloat16mf4x3_t): Ditto.
+	(vfloat16mf4x4_t): Ditto.
+	(vfloat16mf4x5_t): Ditto.
+	(vfloat16mf4x6_t): Ditto.
+	(vfloat16mf4x7_t): Ditto.
+	(vfloat16mf4x8_t): Ditto.
+	(vfloat16mf2x2_t): Ditto.
+	(vfloat16mf2x3_t): Ditto.
+	(vfloat16mf2x4_t): Ditto.
+	(vfloat16mf2x5_t): Ditto.
+	(vfloat16mf2x6_t): Ditto.
+	(vfloat16mf2x7_t): Ditto.
+	(vfloat16mf2x8_t): Ditto.
+	(vfloat16m1x2_t): Ditto.
+	(vfloat16m1x3_t): Ditto.
+	(vfloat16m1x4_t): Ditto.
+	(vfloat16m1x5_t): Ditto.
+	(vfloat16m1x6_t): Ditto.
+	(vfloat16m1x7_t): Ditto.
+	(vfloat16m1x8_t): Ditto.
+	(vfloat16m2x2_t): Ditto.
+	(vfloat16m2x3_t): Ditto.
+	(vfloat16m2x4_t): Ditto.
+	(vfloat16m4x2_t): Ditto.
+	* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): New macro.
+	(vfloat16mf4x3_t): Ditto.
+	(vfloat16mf4x4_t): Ditto.
+	(vfloat16mf4x5_t): Ditto.
+	(vfloat16mf4x6_t): Ditto.
+	(vfloat16mf4x7_t): Ditto.
+	(vfloat16mf4x8_t): Ditto.
+	(vfloat16mf2x2_t): Ditto.
+	(vfloat16mf2x3_t): Ditto.
+	(vfloat16mf2x4_t): Ditto.
+	(vfloat16mf2x5_t): Ditto.
+	(vfloat16mf2x6_t): Ditto.
+	(vfloat16mf2x7_t): Ditto.
+	(vfloat16mf2x8_t): Ditto.
+	(vfloat16m1x2_t): Ditto.
+	(vfloat16m1x3_t): Ditto.
+	(vfloat16m1x4_t): Ditto.
+	(vfloat16m1x5_t): Ditto.
+	(vfloat16m1x6_t): Ditto.
+	(vfloat16m1x7_t): Ditto.
+	(vfloat16m1x8_t): Ditto.
+	(vfloat16m2x2_t): Ditto.
+	(vfloat16m2x3_t): Ditto.
+	(vfloat16m2x4_t): Ditto.
+	(vfloat16m4x2_t): Ditto.
+	* config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): New.
+	* config/riscv/riscv.md: New.
+	* config/riscv/vector-iterators.md: New.
+
+2023-06-17  Roger Sayle  <roger@nextmovesoftware.com>
+
+	* config/i386/i386-expand.cc (ix86_expand_move): Check that OP1 is
+	CONST_WIDE_INT_P before calling ix86_convert_wide_int_to_broadcast.
+	Generalize special case for converting TImode to V1TImode to handle
+	all 128-bit vector conversions.
+
+2023-06-17  Costas Argyris  <costas.argyris@gmail.com>
+
+	* gcc-ar.cc (main): Refactor to slightly reduce code
+	duplication.  Avoid unnecessary elements in nargv.
+
+2023-06-16  Pan Li  <pan2.li@intel.com>
+
+	PR target/110265
+	* config/riscv/riscv-vector-builtins-bases.cc: Add ret_mode for
+	integer reduction expand.
+	* config/riscv/vector-iterators.md: Add VQI, VHI, VSI and VDI,
+	and the LMUL1 attr respectively.
+	* config/riscv/vector.md
+	(@pred_reduc_<reduc><mode><vlmul1>): Removed.
+	(@pred_reduc_<reduc><mode><vlmul1_zve64>): Likewise.
+	(@pred_reduc_<reduc><mode><vlmul1_zve32>): Likewise.
+	(@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>): New pattern.
+	(@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Likewise.
+	(@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Likewise.
+	(@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Likewise.
+
+2023-06-16  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	PR target/110264
+	* config/riscv/riscv-vsetvl.cc (insert_vsetvl): Fix bug.
+
+2023-06-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/79173
+	* builtin-types.def (BT_FN_UINT_UINT_UINT_UINT_UINTPTR,
+	BT_FN_ULONG_ULONG_ULONG_ULONG_ULONGPTR,
+	BT_FN_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONGPTR): New
+	types.
+	* builtins.def (BUILT_IN_ADDC, BUILT_IN_ADDCL, BUILT_IN_ADDCLL,
+	BUILT_IN_SUBC, BUILT_IN_SUBCL, BUILT_IN_SUBCLL): New builtins.
+	* builtins.cc (fold_builtin_addc_subc): New function.
+	(fold_builtin_varargs): Handle BUILT_IN_{ADD,SUB}C{,L,LL}.
+	* doc/extend.texi (__builtin_addc, __builtin_subc): Document.
+
+2023-06-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/110271
+	* tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children)
+	<case PLUS_EXPR>: Ignore return value from match_arith_overflow,
+	instead call match_uaddc_usubc only if gsi_stmt (gsi) is still stmt.
+
+2023-06-16  Martin Jambor  <mjambor@suse.cz>
+
+	* configure: Regenerate.
+
+2023-06-16  Roger Sayle  <roger@nextmovesoftware.com>
+	    Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/31985
+	* config/i386/i386.md (*add<dwi>3_doubleword_concat): New
+	define_insn_and_split combine *add<dwi>3_doubleword with
+	a *concat<mode><dwi>3 for more efficient lowering after reload.
+
+2023-06-16  Vladimir N. Makarov  <vmakarov@redhat.com>
+
+	* ira-lives.cc: Include except.h.
+	(process_bb_node_lives): Ignore conflicts from cleanup exceptions
+	when the pseudo does not live at the exception landing pad.
+
+2023-06-16  Alex Coplan  <alex.coplan@arm.com>
+
+	* doc/invoke.texi: Document -Welaborated-enum-base.
+
+2023-06-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd-builtins.def (shrn2_n): Rename builtins to...
+	(ushrn2_n): ... This.
+	(sqshrn2_n): Rename builtins to...
+	(ssqshrn2_n): ... This.
+	(uqshrn2_n): Rename builtins to...
+	(uqushrn2_n): ... This.
+	* config/aarch64/arm_neon.h (vqshrn_high_n_s16): Adjust for the above.
+	(vqshrn_high_n_s32): Likewise.
+	(vqshrn_high_n_s64): Likewise.
+	(vqshrn_high_n_u16): Likewise.
+	(vqshrn_high_n_u32): Likewise.
+	(vqshrn_high_n_u64): Likewise.
+	(vshrn_high_n_s16): Likewise.
+	(vshrn_high_n_s32): Likewise.
+	(vshrn_high_n_s64): Likewise.
+	(vshrn_high_n_u16): Likewise.
+	(vshrn_high_n_u32): Likewise.
+	(vshrn_high_n_u64): Likewise.
+	* config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn2_n<mode>_insn_le):
+	Rename to...
+	(aarch64_<shrn_op><sra_op>shrn2_n<mode>_insn_le): ... This.
+	Use SHIFTRT iterator and AARCH64_VALID_SHRN_OP check.
+	(aarch64_<shrn_op>shrn2_n<mode>_insn_be): Rename to...
+	(aarch64_<shrn_op><sra_op>shrn2_n<mode>_insn_be): ... This.
+	Use SHIFTRT iterator and AARCH64_VALID_SHRN_OP check.
+	(aarch64_<shrn_op>shrn2_n<mode>): Rename to...
+	(aarch64_<shrn_op><sra_op>shrn2_n<mode>): ... This.
+	Update expander for the above.
+
+2023-06-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd-builtins.def (shrn2): Rename builtins to...
+	(shrn2_n): ... This.
+	(rshrn2): Rename builtins to...
+	(rshrn2_n): ... This.
+	* config/aarch64/arm_neon.h (vrshrn_high_n_s16): Adjust for the above.
+	(vrshrn_high_n_s32): Likewise.
+	(vrshrn_high_n_s64): Likewise.
+	(vrshrn_high_n_u16): Likewise.
+	(vrshrn_high_n_u32): Likewise.
+	(vrshrn_high_n_u64): Likewise.
+	(vshrn_high_n_s16): Likewise.
+	(vshrn_high_n_s32): Likewise.
+	(vshrn_high_n_s64): Likewise.
+	(vshrn_high_n_u16): Likewise.
+	(vshrn_high_n_u32): Likewise.
+	(vshrn_high_n_u64): Likewise.
+	* config/aarch64/aarch64-simd.md (*aarch64_<srn_op>shrn<mode>2_vect_le):
+	Delete.
+	(*aarch64_<srn_op>shrn<mode>2_vect_be): Likewise.
+	(aarch64_shrn2<mode>_insn_le): Likewise.
+	(aarch64_shrn2<mode>_insn_be): Likewise.
+	(aarch64_shrn2<mode>): Likewise.
+	(aarch64_rshrn2<mode>_insn_le): Likewise.
+	(aarch64_rshrn2<mode>_insn_be): Likewise.
+	(aarch64_rshrn2<mode>): Likewise.
+	(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Likewise.
+	(aarch64_<shrn_op>shrn2_n<mode>_insn_le): New define_insn.
+	(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Delete.
+	(aarch64_<shrn_op>shrn2_n<mode>_insn_be): New define_insn.
+	(aarch64_<sur>q<r>shr<u>n2_n<mode>): Delete.
+	(aarch64_<shrn_op>shrn2_n<mode>): New define_expand.
+	(aarch64_<shrn_op>rshrn2_n<mode>_insn_le): New define_insn.
+	(aarch64_<shrn_op>rshrn2_n<mode>_insn_be): New define_insn.
+	(aarch64_<shrn_op>rshrn2_n<mode>): New define_expand.
+	(aarch64_sqshrun2_n<mode>_insn_le): New define_insn.
+	(aarch64_sqshrun2_n<mode>_insn_be): New define_insn.
+	(aarch64_sqshrun2_n<mode>): New define_expand.
+	(aarch64_sqrshrun2_n<mode>_insn_le): New define_insn.
+	(aarch64_sqrshrun2_n<mode>_insn_be): New define_insn.
+	(aarch64_sqrshrun2_n<mode>): New define_expand.
+	* config/aarch64/iterators.md (UNSPEC_SQSHRUN, UNSPEC_SQRSHRUN,
+	UNSPEC_SQSHRN, UNSPEC_UQSHRN, UNSPEC_SQRSHRN, UNSPEC_UQRSHRN):
+	Delete unspec values.
+	(VQSHRN_N): Delete int iterator.
+
+2023-06-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64.h (AARCH64_VALID_SHRN_OP): Define.
+	* config/aarch64/aarch64-simd.md
+	(*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): Rename to...
+	(*aarch64_<shrn_op><shrn_s>shrn_n<mode>_insn<vczle><vczbe>): ... This.
+	Use SHIFTRT iterator and add AARCH64_VALID_SHRN_OP to condition.
+	* config/aarch64/iterators.md (shrn_s): New code attribute.
+
+2023-06-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n_n<mode>):
+	Rename to...
+	(aarch64_<shrn_op>shrn_n<mode>): ... This.  Reimplement with RTL codes.
+	(*aarch64_<shrn_op>rshrn_n<mode>_insn): New define_insn.
+	(aarch64_sqrshrun_n<mode>_insn): Likewise.
+	(aarch64_sqshrun_n<mode>_insn): Likewise.
+	(aarch64_<shrn_op>rshrn_n<mode>): New define_expand.
+	(aarch64_sqshrun_n<mode>): Likewise.
+	(aarch64_sqrshrun_n<mode>): Likewise.
+	* config/aarch64/iterators.md (V2XWIDE): Add HI and SI modes.
+
+2023-06-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* config/aarch64/aarch64-simd-builtins.def (shrn): Rename builtins to...
+	(shrn_n): ... This.
+	(rshrn): Rename builtins to...
+	(rshrn_n): ... This.
+	* config/aarch64/arm_neon.h (vshrn_n_s16): Adjust for the above.
+	(vshrn_n_s32): Likewise.
+	(vshrn_n_s64): Likewise.
+	(vshrn_n_u16): Likewise.
+	(vshrn_n_u32): Likewise.
+	(vshrn_n_u64): Likewise.
+	(vrshrn_n_s16): Likewise.
+	(vrshrn_n_s32): Likewise.
+	(vrshrn_n_s64): Likewise.
+	(vrshrn_n_u16): Likewise.
+	(vrshrn_n_u32): Likewise.
+	(vrshrn_n_u64): Likewise.
+	* config/aarch64/aarch64-simd.md
+	(*aarch64_<srn_op>shrn<mode><vczle><vczbe>): Delete.
+	(aarch64_shrn<mode>): Likewise.
+	(aarch64_rshrn<mode><vczle><vczbe>_insn): Likewise.
+	(aarch64_rshrn<mode>): Likewise.
+	(aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): Likewise.
+	(aarch64_<sur>q<r>shr<u>n_n<mode>): Likewise.
+	(*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): New define_insn.
+	(*aarch64_<shrn_op>rshrn_n<mode>_insn<vczle><vczbe>): Likewise.
+	(*aarch64_sqshrun_n<mode>_insn<vczle><vczbe>): Likewise.
+	(*aarch64_sqrshrun_n<mode>_insn<vczle><vczbe>): Likewise.
+	(aarch64_<shrn_op>shrn_n<mode>): New define_expand.
+	(aarch64_<shrn_op>rshrn_n<mode>): Likewise.
+	(aarch64_sqshrun_n<mode>): Likewise.
+	(aarch64_sqrshrun_n<mode>): Likewise.
+	* config/aarch64/iterators.md (ALL_TRUNC): New code iterator.
+	(TRUNCEXTEND): New code attribute.
+	(TRUNC_SHIFT): Likewise.
+	(shrn_op): Likewise.
+	* config/aarch64/predicates.md (aarch64_simd_umax_quarter_mode):
+	New predicate.
+
+2023-06-16  Pan Li  <pan2.li@intel.com>
+
+	* config/riscv/riscv-vsetvl.cc
+	(pass_vsetvl::global_eliminate_vsetvl_insn): Initialize var by NULL.
+
+2023-06-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110278
+	* match.pd (uns < (typeof uns)(uns != 0) -> false): New.
+	(x != (typeof x)(x == 0) -> true): Likewise.
+
+2023-06-16  Pali Rohár  <pali@kernel.org>
+
+	* config/i386/mingw-w64.h (CPP_SPEC): Adjust for -mcrtdll=.
+	(REAL_LIBGCC_SPEC): New define.
+	* config/i386/mingw.opt: Add mcrtdll=
+	* config/i386/mingw32.h (CPP_SPEC): Adjust for -mcrtdll=.
+	(REAL_LIBGCC_SPEC): Adjust for -mcrtdll=.
+	(STARTFILE_SPEC): Adjust for -mcrtdll=.
+	* doc/invoke.texi: Add mcrtdll= documentation.
+
+2023-06-16  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* config/mips/mips.cc (enum mips_code_readable_setting):New enmu.
+	(mips_handle_code_readable_attr):New static function.
+	(mips_get_code_readable_attr):New static enum function.
+	(mips_set_current_function):Set the code_readable mode.
+	(mips_option_override):Same as above.
+	* doc/extend.texi:Document code_readable.
+
+2023-06-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110269
+	* fold-const.cc (fold_binary_loc): Merge x != 0 folding
+	with tree_expr_nonzero_p ...
+	* match.pd (cmp (convert? addr@0) integer_zerop): With this
+	pattern.
+
 2023-06-15  Marek Polacek  <polacek@redhat.com>
 
 	* Makefile.in: Set LD_PICFLAG.  Use it.  Set enable_host_pie.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index d8455aa..2fa3911 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230616
+20230622
diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog
index c3035d1..5110f3d 100644
--- a/gcc/ada/ChangeLog
+++ b/gcc/ada/ChangeLog
@@ -1,3 +1,223 @@
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Variable>: Pass
+	the NULL_TREE explicitly and test imported_p in lieu of
+	Is_Imported. <E_Function>: Remove public_flag local variable and
+	make extern_flag local variable a constant.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* sem_res.adb (Resolve_Call): Fix change that replaced test for
+	quantified expressions by the test for potentially unevaluated
+	contexts. Both should be performed.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_ch7.adb (Convert_View): Detect more cases of mismatches for
+	private types and use Implementation_Base_Type as main criterion.
+	* gen_il-fields.ads (Opt_Field_Enum): Add
+	Has_Secondary_Private_View
+	* gen_il-gen-gen_nodes.adb (N_Expanded_Name): Likewise.
+	(N_Direct_Name): Likewise.
+	(N_Op): Likewise.
+	* sem_ch12.ads (Check_Private_View): Document the usage of second
+	flag Has_Secondary_Private_View.
+	* sem_ch12.adb (Get_Associated_Entity): New function to retrieve
+	the ultimate associated entity, if any.
+	(Check_Private_View): Implement Has_Secondary_Private_View
+	support.
+	(Copy_Generic_Node): Remove specific treatment for Component_Type
+	of an array type and Designated_Type of an access type. Add
+	specific treatment for comparison and equality operators, as well
+	as iterator and loop parameter specifications.
+	(Instantiate_Type): Implement Has_Secondary_Private_View support.
+	(Requires_Delayed_Save): Call Get_Associated_Entity.
+	(Set_Global_Type): Implement Has_Secondary_Private_View support.
+	* sem_ch6.adb (Conforming_Types): Remove bypass for private views
+	in instances.
+	* sem_type.adb (Covers): Return true if Is_Subtype_Of does so.
+	Remove bypass for private views in instances.
+	(Specific_Type): Likewise.
+	* sem_util.adb (Wrong_Type): Likewise.
+	* sinfo.ads (Has_Secondary_Private_View): Document new flag.
+
+2023-06-20  Ronan Desplanques  <desplanques@adacore.com>
+
+	* libgnarl/s-mudido.ads: Remove outdated comment.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* doc/gnat_ugn/gnat_and_program_execution.rst (Overflows in GNAT)
+	<Default Settings>: Remove obsolete paragraph about -gnato.
+	<Implementation Notes>: Replace CHECKED with STRICT.
+	* gnat_ugn.texi: Regenerate.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* sem_util.adb (Check_Result_And_Post_State): Do not warn in cases
+	where the warning could be spurious.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* err_vars.ads (Error_Msg_Code): New variable for error codes.
+	* errout.adb (Error_Msg_Internal): Display continuation message
+	when an error code was present.
+	(Set_Msg_Text): Handle character sequence [] for error codes.
+	* errout.ads: Document new insertion sequence [].
+	(Error_Msg_Code): New renaming.
+	* erroutc.adb (Prescan_Message): Detect presence of error code.
+	(Set_Msg_Insertion_Code): Handle new insertion sequence [].
+	* erroutc.ads (Has_Error_Code): New variable for prescan.
+	(Set_Msg_Insertion_Code): Handle new insertion sequence [].
+	* contracts.adb (Check_Type_Or_Object_External_Properties):
+	Replace reference to SPARK RM section by an error code.
+	* sem_elab.adb (SPARK_Processor): Same.
+	* sem_prag.adb (Check_Missing_Part_Of): Same.
+	* sem_res.adb (Resolve_Actuals, Resolve_Entity_Name): Same.
+
+2023-06-20  Piotr Trojanek  <trojanek@adacore.com>
+
+	* sem_res.adb (Resolve_Entity_Name): Handle Range like First and Last.
+
+2023-06-20  Jose Ruiz  <ruiz@adacore.com>
+
+	* doc/gnat_ugn/the_gnat_compilation_model.rst
+	(Partition-Wide Settings): add this subsection to document
+	configuration settings made by the Ada run time.
+	* gnat_ugn.texi: Regenerate.
+
+2023-06-20  Piotr Trojanek  <trojanek@adacore.com>
+
+	* sem_res.adb (Resolve_Entity_Name): Ignore implicit loop scopes
+	introduced by quantified expressions.
+
+2023-06-20  Bob Duff  <duff@adacore.com>
+
+	* sem_ch3.adb (Analyze_Object_Declaration): Remove predicate-check
+	generation if there is an address clause. These are unnecessary,
+	and cause gigi to crash.
+	* exp_util.ads (Following_Address_Clause): Remove obsolete "???"
+	comments. The suggested changes were done long ago.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* einfo.ads (Has_Private_Ancestor): Fix inaccuracy in description.
+	* sem_ch12.adb (Check_Actual_Type): Do not switch the view of the
+	type if it has a private ancestor.
+
+2023-06-20  Daniel King  <dmking@adacore.com>
+
+	* libgnat/i-cheri.ads: Add CHERI intrinsics and helper functions.
+	* libgnat/i-cheri.adb: Likewise
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_ch7.adb (Convert_View): Remove Ind parameter and adjust.
+	* sem_ch12.adb (Check_Generic_Actuals): Check the type of both in
+	and in out actual objects, as well as the type of formal parameters
+	of actual subprograms.  Extend the condition under which the views
+	are swapped to nested generic constructs.
+	(Save_References_In_Identifier): Call Set_Global_Type on a global
+	identifier rewritten as an explicit dereference, either directly
+	or after having first been rewritten as a function call.
+	(Save_References_In_Operator): Set N2 unconditionally and reuse it.
+	* sem_ch3.adb (Build_Derived_Record_Type): Add missing comment.
+	* sem_res.adb (Resolve_Implicit_Dereference): Remove special bypass
+	for private views in instances.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* exp_aggr.adb (Convert_To_Assignments): Tweak comment.
+	(Expand_Array_Aggregate): Do not delay the expansion if the parent
+	node is a container aggregate.
+
+2023-06-20  Ghjuvan Lacambre  <lacambre@adacore.com>
+
+	* errout.adb (Output_Messages): Fix loop termination condition.
+
+2023-06-20  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* doc/gnat_ugn/building_executable_programs_with_gnat.rst (Compiler
+	Switches): Document -gnateH.
+	* opt.ads (Reverse_Bit_Order_Threshold): New variable.
+	* sem_ch13.adb (Adjust_Record_For_Reverse_Bit_Order): Use its value
+	if it is nonnegative instead of System_Max_Integer_Size.
+	* switch-c.adb (Scan_Front_End_Switches): Deal with -gnateH.
+	* usage.adb (Usage): Print -gnateH.
+	* gnat_ugn.texi: Regenerate.
+
+2023-06-20  Yannick Moy  <moy@adacore.com>
+
+	* libgnat/s-aridou.adb (Scaled_Divide): Add assertions.
+	* libgnat/s-valuti.adb: Add Loop_Variant.
+	* libgnat/s-valuti.ads: Add Exceptional_Cases on No_Return
+	procedure.
+
+2023-06-20  Marc Poulhiès  <poulhies@adacore.com>
+
+	* sem_ch3.adb (Build_Derived_Record_Type): Use full view as
+	Parent_Base if needed.
+
+2023-06-20  Ghjuvan Lacambre  <lacambre@adacore.com>
+
+	* lib-load.adb (Load_Unit): Pass Error_Node to calls to Error_Msg.
+
+2023-06-20  Claire Dross  <dross@adacore.com>
+
+	* libgnat/a-strfix.ads: Replace Might_Not_Return annotations by
+	Exceptional_Cases and Always_Terminates aspects.
+	* libgnat/a-tideio.ads: Idem.
+	* libgnat/a-tienio.ads: Idem.
+	* libgnat/a-tifiio.ads: Idem.
+	* libgnat/a-tiflio.ads: Idem.
+	* libgnat/a-tiinio.ads: Idem.
+	* libgnat/a-timoio.ads: Idem.
+	* libgnat/a-textio.ads: Idem. Also mark functions Name, Col, Line,
+	and Page as out of SPARK as they might raise Layout_Error.
+	* libgnarl/a-reatim.ads: Replace Always_Return annotations by
+	Always_Terminates aspects.
+	* libgnat/a-chahan.ads: Idem.
+	* libgnat/a-nbnbig.ads: Idem.
+	* libgnat/a-nbnbin.ads: Idem.
+	* libgnat/a-nbnbre.ads: Idem.
+	* libgnat/a-ngelfu.ads: Idem.
+	* libgnat/a-nlelfu.ads: Idem.
+	* libgnat/a-nllefu.ads: Idem.
+	* libgnat/a-nselfu.ads: Idem.
+	* libgnat/a-nuelfu.ads: Idem.
+	* libgnat/a-strbou.ads: Idem.
+	* libgnat/a-strmap.ads: Idem.
+	* libgnat/a-strsea.ads: Idem.
+	* libgnat/a-strsup.ads: Idem.
+	* libgnat/a-strunb.ads: Idem.
+	* libgnat/a-strunb__shared.ads: Idem.
+	* libgnat/g-souinf.ads: Idem.
+	* libgnat/i-c.ads: Idem.
+	* libgnat/interfac.ads: Idem.
+	* libgnat/interfac__2020.ads: Idem.
+	* libgnat/s-aridou.adb: Idem.
+	* libgnat/s-arit32.adb: Idem.
+	* libgnat/s-atacco.ads: Idem.
+	* libgnat/s-spcuop.ads: Idem.
+	* libgnat/s-stoele.ads: Idem.
+	* libgnat/s-vaispe.ads: Idem.
+	* libgnat/s-vauspe.ads: Idem.
+	* libgnat/i-cstrin.ads: Add a precondition instead of a
+	Might_Not_Return annotation.
+
+2023-06-20  Javier Miranda  <miranda@adacore.com>
+
+	* sem_ch4.adb
+	(Try_Selected_Component_In_Instance): New subprogram; factorizes
+	existing code.
+	(Find_Component_In_Instance) Moved inside the new subprogram.
+	(Analyze_Selected_Component): Invoke the new subprogram before
+	trying the Object.Operation notation.
+
+2023-06-20  Ronan Desplanques  <desplanques@adacore.com>
+
+	* libgnat/a-calfor.adb (Time_Of): Fix handling of special case.
+
 2023-06-15  Marek Polacek  <polacek@redhat.com>
 
 	* gcc-interface/Make-lang.in (ALL_ADAFLAGS): Remove NO_PIE_CFLAGS.  Add
diff --git a/gcc/ada/contracts.adb b/gcc/ada/contracts.adb
index 26bc4b3..77578da 100644
--- a/gcc/ada/contracts.adb
+++ b/gcc/ada/contracts.adb
@@ -1040,11 +1040,12 @@ package body Contracts is
             --  appear at the library level (SPARK RM 7.1.3(3), C.6(6)).
 
             if not Is_Library_Level_Entity (Type_Or_Obj_Id) then
+               Error_Msg_Code := GEC_Volatile_At_Library_Level;
                Error_Msg_N
                  ("effectively volatile "
                     & Decl_Kind
-                    & " & must be declared at library level "
-                    & "(SPARK RM 7.1.3(3))", Type_Or_Obj_Id);
+                    & " & must be declared at library level '[[]']",
+                    Type_Or_Obj_Id);
 
             --  An object of a discriminated type cannot be effectively
             --  volatile except for protected objects (SPARK RM 7.1.3(5)).
diff --git a/gcc/ada/doc/gnat_ugn/building_executable_programs_with_gnat.rst b/gcc/ada/doc/gnat_ugn/building_executable_programs_with_gnat.rst
index 20e003d..8e47967 100644
--- a/gcc/ada/doc/gnat_ugn/building_executable_programs_with_gnat.rst
+++ b/gcc/ada/doc/gnat_ugn/building_executable_programs_with_gnat.rst
@@ -1612,6 +1612,14 @@ Alphabetical List of All Switches
   Save result of preprocessing in a text file.
 
 
+.. index:: -gnateH  (gcc)
+
+:switch:`-gnateH`
+  Set the threshold from which the RM 13.5.1(13.3/2) clause applies to 64.
+  This is useful only on 64-bit plaforms where this threshold is 128, but
+  used to be 64 in earlier versions of the compiler.
+
+
 .. index:: -gnatei  (gcc)
 
 :switch:`-gnatei{nnn}`
diff --git a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst
index 9eb6b1c..62abca2 100644
--- a/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst
+++ b/gcc/ada/doc/gnat_ugn/gnat_and_program_execution.rst
@@ -2925,25 +2925,8 @@ The default mode for overflow checks is
 
       General => Strict
 
-which causes all computations both inside and outside assertions to use
-the base type.
-
-This retains compatibility with previous versions of
-GNAT which suppressed overflow checks by default and always
-used the base type for computation of intermediate results.
-
-.. Sphinx allows no emphasis within :index: role. As a workaround we
-   point the index to "switch" and use emphasis for "-gnato".
-
-The :index:`switch <-gnato (gcc)>` :switch:`-gnato` (with no digits following)
-is equivalent to
-
-  ::
-
-      General => Strict
-
-which causes overflow checking of all intermediate overflows
-both inside and outside assertions against the base type.
+which causes all computations both inside and outside assertions to use the
+base type, and is equivalent to :switch:`-gnato` (with no digits following).
 
 The pragma ``Suppress (Overflow_Check)`` disables overflow
 checking, but it has no effect on the method used for computing
@@ -2964,7 +2947,7 @@ reasonably efficient, and can be generally used. It also helps
 to ensure compatibility with code imported from some other
 compiler to GNAT.
 
-Setting all intermediate overflows checking (``CHECKED`` mode)
+Setting all intermediate overflows checking (``STRICT`` mode)
 makes sense if you want to
 make sure that your code is compatible with any other possible
 Ada implementation. This may be useful in ensuring portability
diff --git a/gcc/ada/doc/gnat_ugn/the_gnat_compilation_model.rst b/gcc/ada/doc/gnat_ugn/the_gnat_compilation_model.rst
index c7f15b4..e4639d9 100644
--- a/gcc/ada/doc/gnat_ugn/the_gnat_compilation_model.rst
+++ b/gcc/ada/doc/gnat_ugn/the_gnat_compilation_model.rst
@@ -4493,6 +4493,53 @@ finalizing the Ada run-time system along the way:
        return 0;
      }
 
+.. _Partition_Wide_Settings:
+
+Partition-Wide Settings
+-----------------------
+
+When building a mixed-language application it is important to be aware that
+Ada enforces some partition-wide settings that may implicitly impact the
+behavior of the other languages.
+
+This is the case of certain signals that are reserved to the
+implementation to implement proper Ada semantics (such as the behavior
+of ``abort`` statements).
+
+It means that the Ada part of the application may override signal handlers
+that were previously installed by either the system or by other user code.
+
+If your application requires that either system or user signals be preserved
+then you need to instruct the Ada part not to install its own signal handler.
+This is done using ``pragma Interrupt_State`` that provides a general
+mechanism for overriding such uses of interrupts.
+
+The set of interrupts for which the Ada run-time library sets a specific signal
+handler is the following:
+
+* Ada.Interrupts.Names.SIGSEGV
+* Ada.Interrupts.Names.SIGBUS
+* Ada.Interrupts.Names.SIGFPE
+* Ada.Interrupts.Names.SIGILL
+* Ada.Interrupts.Names.SIGABRT
+
+The run-time library can be instructed not to install its signal handler for a
+particular signal by using the configuration pragma ``Interrupt_State`` in the
+Ada code. For example:
+
+.. code-block:: ada
+
+   pragma Interrupt_State (Ada.Interrupts.Names.SIGSEGV, System);
+   pragma Interrupt_State (Ada.Interrupts.Names.SIGBUS,  System);
+   pragma Interrupt_State (Ada.Interrupts.Names.SIGFPE,  System);
+   pragma Interrupt_State (Ada.Interrupts.Names.SIGILL,  System);
+   pragma Interrupt_State (Ada.Interrupts.Names.SIGABRT, System);
+
+Obviously, if the Ada run-time system cannot set these handlers it comes with the
+drawback of not fully preserving Ada semantics. ``SIGSEGV``, ``SIGBUS``, ``SIGFPE``
+and ``SIGILL`` are used to raise corresponding Ada exceptions in the application,
+while ``SIGABRT`` is used to asynchronously abort an action or a task.
+
 .. _Generating_Ada_Bindings_for_C_and_C++_headers:
 
 Generating Ada Bindings for C and C++ headers
diff --git a/gcc/ada/einfo.ads b/gcc/ada/einfo.ads
index a861ff7..b356b76 100644
--- a/gcc/ada/einfo.ads
+++ b/gcc/ada/einfo.ads
@@ -1969,7 +1969,7 @@ package Einfo is
 --       is defined for the type.
 
 --    Has_Private_Ancestor
---       Applies to type extensions. True if some ancestor is derived from a
+--       Applies to derived record types. True if an ancestor is derived from a
 --       private type, making some components invisible and aggregates illegal.
 --       This flag is set at the point of derivation. The legality of the
 --       aggregate must be rechecked because it also depends on the visibility
diff --git a/gcc/ada/err_vars.ads b/gcc/ada/err_vars.ads
index e73e9fb..e84efb6 100644
--- a/gcc/ada/err_vars.ads
+++ b/gcc/ada/err_vars.ads
@@ -100,6 +100,11 @@ package Err_Vars is
    Error_Msg_Uint_2 : Uint := No_Uint;
    --  Uint values for ^ insertion characters in message
 
+   Error_Msg_Code_Digits : constant := 4;
+   Error_Msg_Code : Nat range 0 .. 10 ** Error_Msg_Code_Digits - 1;
+   --  Nat value for [] insertion sequence in message, where a value of zero
+   --  indicates the absence of an error code.
+
    --  WARNING: There is a matching C declaration of these variables in fe.h
 
    Error_Msg_Sloc : Source_Ptr;
diff --git a/gcc/ada/errout.adb b/gcc/ada/errout.adb
index 1c6222b..adc2608 100644
--- a/gcc/ada/errout.adb
+++ b/gcc/ada/errout.adb
@@ -1447,6 +1447,22 @@ package body Errout is
             raise Unrecoverable_Error;
          end if;
       end if;
+
+      if Has_Error_Code then
+         declare
+            Msg : constant String :=
+              "launch ""gnatprove --explain=[]"" for more information";
+         begin
+            Prescan_Message (Msg);
+            Has_Error_Code := False;
+            Error_Msg_Internal
+              (Msg      => Msg,
+               Span     => Span,
+               Opan     => Opan,
+               Msg_Cont => True,
+               Node     => Node);
+         end;
+      end if;
    end Error_Msg_Internal;
 
    -----------------
@@ -3062,16 +3078,19 @@ package body Errout is
 
             E := Errors.Table (E).Next;
 
-            --  Skip deleted messages.
-            --  Also skip continuation messages, as they have already been
-            --  printed along the message they're attached to.
+            while E /= No_Error_Msg loop
+
+               --  Skip deleted messages.
+               --  Also skip continuation messages, as they have already been
+               --  printed along the message they're attached to.
+
+               if not Errors.Table (E).Deleted
+                 and then not Errors.Table (E).Msg_Cont
+               then
+                  Write_Char (',');
+                  Output_JSON_Message (E);
+               end if;
 
-            while E /= No_Error_Msg
-              and then not Errors.Table (E).Deleted
-              and then not Errors.Table (E).Msg_Cont
-            loop
-               Write_Char (',');
-               Output_JSON_Message (E);
                E := Errors.Table (E).Next;
             end loop;
          end if;
@@ -4335,21 +4354,29 @@ package body Errout is
 
             when '[' =>
 
-               --  Switch the message from a warning to an error if the flag
-               --  -gnatwE is specified to treat run-time exception warnings
-               --  as errors.
+               --  "[]" (insertion of error code)
 
-               if Is_Warning_Msg
-                 and then Warning_Mode = Treat_Run_Time_Warnings_As_Errors
-               then
-                  Is_Warning_Msg   := False;
-                  Is_Runtime_Raise := True;
-               end if;
+               if P <= Text'Last and then Text (P) = ']' then
+                  P := P + 1;
+                  Set_Msg_Insertion_Code;
 
-               if Is_Warning_Msg then
-                  Set_Msg_Str ("will be raised at run time");
                else
-                  Set_Msg_Str ("would have been raised at run time");
+                  --  Switch the message from a warning to an error if the flag
+                  --  -gnatwE is specified to treat run-time exception warnings
+                  --  as errors.
+
+                  if Is_Warning_Msg
+                    and then Warning_Mode = Treat_Run_Time_Warnings_As_Errors
+                  then
+                     Is_Warning_Msg   := False;
+                     Is_Runtime_Raise := True;
+                  end if;
+
+                  if Is_Warning_Msg then
+                     Set_Msg_Str ("will be raised at run time");
+                  else
+                     Set_Msg_Str ("would have been raised at run time");
+                  end if;
                end if;
 
             --   ']' (may be/might have been raised at run time)
diff --git a/gcc/ada/errout.ads b/gcc/ada/errout.ads
index f152839..80dd7df 100644
--- a/gcc/ada/errout.ads
+++ b/gcc/ada/errout.ads
@@ -404,6 +404,10 @@ package Errout is
    --      This is like [ except that the insertion messages say may/might,
    --      instead of will/would.
 
+   --    Insertion sequence [] (Left and right brackets: error code)
+   --      The insertion sequence [] should be replaced by an error code, whose
+   --      value is given by Error_Msg_Code.
+
    --    Insertion sequence "(style)" (style message)
    --      This appears only at the start of the message (and not any of its
    --      continuations, if any), and indicates that the message is a style
@@ -454,6 +458,11 @@ package Errout is
    Error_Msg_Uint_2 : Uint renames Err_Vars.Error_Msg_Uint_2;
    --  Uint values for ^ insertion characters in message
 
+   Error_Msg_Code_Digits : constant := Err_Vars.Error_Msg_Code_Digits;
+   Error_Msg_Code : Nat renames Err_Vars.Error_Msg_Code;
+   --  Nat value for [] insertion sequence in message, where a value of zero
+   --  indicates the absence of an error code.
+
    Error_Msg_Sloc : Source_Ptr renames Err_Vars.Error_Msg_Sloc;
    --  Source location for # insertion character in message
 
@@ -600,6 +609,21 @@ package Errout is
    --  Returns the flag location of the error message with the given id E
 
    ------------------------
+   -- GNAT Explain Codes --
+   ------------------------
+
+   --  Explain codes are used in GNATprove to provide more information on
+   --  selected error/warning messages. The subset of those codes used in
+   --  the GNAT frontend are defined here.
+
+   GEC_None                             : constant := 0000;
+   GEC_Volatile_At_Library_Level        : constant := 0001;
+   GEC_Type_Early_Call_Region           : constant := 0003;
+   GEC_Volatile_Non_Interfering_Context : constant := 0004;
+   GEC_Required_Part_Of                 : constant := 0009;
+   GEC_Ownership_Moved_Object           : constant := 0010;
+
+   ------------------------
    -- List Pragmas Table --
    ------------------------
 
diff --git a/gcc/ada/erroutc.adb b/gcc/ada/erroutc.adb
index e5caeba..5a8556b 100644
--- a/gcc/ada/erroutc.adb
+++ b/gcc/ada/erroutc.adb
@@ -959,6 +959,7 @@ package body Erroutc is
       end if;
 
       Has_Double_Exclam  := False;
+      Has_Error_Code     := False;
       Has_Insertion_Line := False;
 
       --  Loop through message looking for relevant insertion sequences
@@ -1012,6 +1013,15 @@ package body Erroutc is
             Is_Serious_Error := False;
             J := J + 1;
 
+         --  Error code ([] insertion)
+
+         elsif Msg (J) = '['
+           and then J < Msg'Last
+           and then Msg (J + 1) = ']'
+         then
+            Has_Error_Code := True;
+            J := J + 2;
+
          else
             J := J + 1;
          end if;
@@ -1156,6 +1166,42 @@ package body Erroutc is
       end if;
    end Set_Msg_Char;
 
+   ----------------------------
+   -- Set_Msg_Insertion_Code --
+   ----------------------------
+
+   procedure Set_Msg_Insertion_Code is
+      H : constant array (Nat range 0 .. 9) of Character := "0123456789";
+      P10 : constant array (Natural range 0 .. 3) of Nat :=
+        (10 ** 0,
+         10 ** 1,
+         10 ** 2,
+         10 ** 3);
+
+      Code_Len : constant Natural :=
+        (case Error_Msg_Code is
+           when    0         => 0,
+           when    1 ..    9 => 1,
+           when   10 ..   99 => 2,
+           when  100 ..  999 => 3,
+           when 1000 .. 9999 => 4);
+      Code_Rest  : Nat := Error_Msg_Code;
+      Code_Digit : Nat;
+
+   begin
+      Set_Msg_Char ('E');
+
+      for J in 1 .. Error_Msg_Code_Digits - Code_Len loop
+         Set_Msg_Char ('0');
+      end loop;
+
+      for J in 1 .. Code_Len loop
+         Code_Digit := Code_Rest / P10 (Code_Len - J);
+         Set_Msg_Char (H (Code_Digit));
+         Code_Rest := Code_Rest - Code_Digit * P10 (Code_Len - J);
+      end loop;
+   end Set_Msg_Insertion_Code;
+
    ---------------------------------
    -- Set_Msg_Insertion_File_Name --
    ---------------------------------
diff --git a/gcc/ada/erroutc.ads b/gcc/ada/erroutc.ads
index c32b19f..6602907 100644
--- a/gcc/ada/erroutc.ads
+++ b/gcc/ada/erroutc.ads
@@ -51,6 +51,10 @@ package Erroutc is
    --  Set true to indicate that the current message contains the insertion
    --  sequence !! (force warnings even in non-main unit source files).
 
+   Has_Error_Code : Boolean := False;
+   --  Set true to indicate that the current message contains the insertion
+   --  sequence [] (insert error code).
+
    Has_Insertion_Line : Boolean := False;
    --  Set True to indicate that the current message contains the insertion
    --  character # (insert line number reference).
@@ -547,6 +551,9 @@ package Erroutc is
    --    Has_Double_Exclam is set True if the message contains the sequence !!
    --    and is otherwise set False.
    --
+   --    Has_Error_Code is set True if the message contains the sequence []
+   --    and is otherwise set False.
+   --
    --    Has_Insertion_Line is set True if the message contains the character #
    --    and is otherwise set False.
    --
@@ -581,6 +588,9 @@ package Erroutc is
    --  check for special insertion characters (they are just treated as text
    --  characters if they occur).
 
+   procedure Set_Msg_Insertion_Code;
+   --  Handle error code insertion ([] insertion character)
+
    procedure Set_Msg_Insertion_File_Name;
    --  Handle file name insertion (left brace insertion character)
 
diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index fb5f404..5e22fef 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -4244,9 +4244,9 @@ package body Exp_Aggr is
       --  done top down from above.
 
       if
-         --  Internal aggregate (transformed when expanding the parent)
-         --  excluding the Container aggregate as these are transformed to
-         --  procedure call later.
+         --  Internal aggregates (transformed when expanding the parent),
+         --  excluding container aggregates as these are transformed into
+         --  subprogram calls later.
 
          (Parent_Kind in
             N_Component_Association | N_Aggregate | N_Extension_Aggregate
@@ -6108,7 +6108,8 @@ package body Exp_Aggr is
       --  STEP 3
 
       --  Delay expansion for nested aggregates: it will be taken care of when
-      --  the parent aggregate is expanded.
+      --  the parent aggregate is expanded, excluding container aggregates as
+      --  these are transformed into subprogram calls later.
 
       Parent_Node := Parent (N);
       Parent_Kind := Nkind (Parent_Node);
@@ -6118,9 +6119,10 @@ package body Exp_Aggr is
          Parent_Kind := Nkind (Parent_Node);
       end if;
 
-      if Parent_Kind = N_Aggregate
-        or else Parent_Kind = N_Extension_Aggregate
-        or else Parent_Kind = N_Component_Association
+      if ((Parent_Kind = N_Component_Association
+            or else Parent_Kind = N_Aggregate
+            or else Parent_Kind = N_Extension_Aggregate)
+           and then not Is_Container_Aggregate (Parent_Node))
         or else (Parent_Kind = N_Object_Declaration
                   and then (Needs_Finalization (Typ)
                              or else Is_Special_Return_Object
diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb
index 42b41e5..1b16839 100644
--- a/gcc/ada/exp_ch7.adb
+++ b/gcc/ada/exp_ch7.adb
@@ -394,13 +394,9 @@ package body Exp_Ch7 is
    --  Check recursively whether a loop or block contains a subprogram that
    --  may need an activation record.
 
-   function Convert_View
-     (Proc : Entity_Id;
-      Arg  : Node_Id;
-      Ind  : Pos := 1) return Node_Id;
+   function Convert_View (Proc : Entity_Id; Arg  : Node_Id) return Node_Id;
    --  Proc is one of the Initialize/Adjust/Finalize operations, and Arg is the
-   --  argument being passed to it. Ind indicates which formal of procedure
-   --  Proc we are trying to match. This function will, if necessary, generate
+   --  argument being passed to it. This function will, if necessary, generate
    --  a conversion between the partial and full view of Arg to match the type
    --  of the formal of Proc, or force a conversion to the class-wide type in
    --  the case where the operation is abstract.
@@ -4402,22 +4398,12 @@ package body Exp_Ch7 is
    -- Convert_View --
    ------------------
 
-   function Convert_View
-     (Proc : Entity_Id;
-      Arg  : Node_Id;
-      Ind  : Pos := 1) return Node_Id
-   is
-      Fent : Entity_Id := First_Entity (Proc);
-      Ftyp : Entity_Id;
+   function Convert_View (Proc : Entity_Id; Arg  : Node_Id) return Node_Id is
+      Ftyp : constant Entity_Id := Etype (First_Formal (Proc));
+
       Atyp : Entity_Id;
 
    begin
-      for J in 2 .. Ind loop
-         Next_Entity (Fent);
-      end loop;
-
-      Ftyp := Etype (Fent);
-
       if Nkind (Arg) in N_Type_Conversion | N_Unchecked_Type_Conversion then
          Atyp := Entity (Subtype_Mark (Arg));
       else
@@ -4427,11 +4413,13 @@ package body Exp_Ch7 is
       if Is_Abstract_Subprogram (Proc) and then Is_Tagged_Type (Ftyp) then
          return Unchecked_Convert_To (Class_Wide_Type (Ftyp), Arg);
 
-      elsif Ftyp /= Atyp
-        and then Present (Atyp)
-        and then (Is_Private_Type (Ftyp) or else Is_Private_Type (Atyp))
-        and then Base_Type (Underlying_Type (Atyp)) =
-                 Base_Type (Underlying_Type (Ftyp))
+      elsif Present (Atyp)
+        and then Atyp /= Ftyp
+        and then (Is_Private_Type (Ftyp)
+                   or else Is_Private_Type (Atyp)
+                   or else Is_Private_Type (Base_Type (Atyp)))
+        and then Implementation_Base_Type (Atyp) =
+                 Implementation_Base_Type (Ftyp)
       then
          return Unchecked_Convert_To (Ftyp, Arg);
 
diff --git a/gcc/ada/exp_util.ads b/gcc/ada/exp_util.ads
index 24065b6..02324d23 100644
--- a/gcc/ada/exp_util.ads
+++ b/gcc/ada/exp_util.ads
@@ -647,13 +647,6 @@ package Exp_Util is
    --  current declarative part to look for an address clause for the object
    --  being declared, and returns the clause if one is found, returns
    --  Empty otherwise.
-   --
-   --  Note: this function can be costly and must be invoked with special care.
-   --  Possibly we could introduce a flag at parse time indicating the presence
-   --  of an address clause to speed this up???
-   --
-   --  Note: currently this function does not scan the private part, that seems
-   --  like a potential bug ???
 
    type Force_Evaluation_Mode is (Relaxed, Strict);
 
diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc
index b2b7778..494b24e 100644
--- a/gcc/ada/gcc-interface/decl.cc
+++ b/gcc/ada/gcc-interface/decl.cc
@@ -1162,7 +1162,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition)
 
 		    gnu_expr = build_unary_op (ADDR_EXPR, gnu_type, gnu_expr);
 
-		    create_var_decl (gnu_entity_name, gnu_ext_name,
+		    create_var_decl (gnu_entity_name, NULL_TREE,
 				     TREE_TYPE (gnu_expr), gnu_expr,
 				     const_flag, Is_Public (gnat_entity),
 				     imported_p, static_flag, volatile_flag,
@@ -1533,7 +1533,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition)
 
 	/* If this name is external or a name was specified, use it, but don't
 	   use the Interface_Name with an address clause (see cd30005).  */
-	if ((Is_Public (gnat_entity) && !Is_Imported (gnat_entity))
+	if ((Is_Public (gnat_entity) && !imported_p)
 	    || (Present (Interface_Name (gnat_entity))
 		&& No (Address_Clause (gnat_entity))))
 	  gnu_ext_name = create_concat_name (gnat_entity, NULL);
@@ -3977,10 +3977,9 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition)
 	  = gnu_ext_name_for_subprog (gnat_entity, gnu_entity_name);
 	const enum inline_status_t inline_status
 	  = inline_status_for_subprog (gnat_entity);
-	bool public_flag = Is_Public (gnat_entity) || imported_p;
 	/* Subprograms marked both Intrinsic and Always_Inline need not
 	   have a body of their own.  */
-	bool extern_flag
+	const bool extern_flag
 	  = ((Is_Public (gnat_entity) && !definition)
 	     || imported_p
 	     || (Is_Intrinsic_Subprogram (gnat_entity)
@@ -4135,10 +4134,9 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition)
 	    else
 	      gnu_decl
 		= create_subprog_decl (gnu_entity_name, gnu_ext_name,
-				       gnu_type, gnu_param_list,
-				       inline_status, public_flag,
-				       extern_flag, artificial_p,
-				       debug_info_p,
+				       gnu_type, gnu_param_list, inline_status,
+				       Is_Public (gnat_entity) || imported_p,
+				       extern_flag, artificial_p, debug_info_p,
 				       definition && imported_p, attr_list,
 				       gnat_entity);
 	  }
diff --git a/gcc/ada/gen_il-fields.ads b/gcc/ada/gen_il-fields.ads
index c62523d..a017f45 100644
--- a/gcc/ada/gen_il-fields.ads
+++ b/gcc/ada/gen_il-fields.ads
@@ -210,6 +210,7 @@ package Gen_IL.Fields is
       Has_Pragma_Suppress_All,
       Has_Private_View,
       Has_Relative_Deadline_Pragma,
+      Has_Secondary_Private_View,
       Has_Self_Reference,
       Has_SP_Choice,
       Has_Storage_Size_Pragma,
diff --git a/gcc/ada/gen_il-gen-gen_nodes.adb b/gcc/ada/gen_il-gen-gen_nodes.adb
index 19551fd..2ad6e60 100644
--- a/gcc/ada/gen_il-gen-gen_nodes.adb
+++ b/gcc/ada/gen_il-gen-gen_nodes.adb
@@ -170,13 +170,15 @@ begin -- Gen_IL.Gen.Gen_Nodes
         Sy (Selector_Name, Node_Id, Default_Empty),
         Sm (Atomic_Sync_Required, Flag),
         Sm (Has_Private_View, Flag),
+        Sm (Has_Secondary_Private_View, Flag),
         Sm (Is_Elaboration_Checks_OK_Node, Flag),
         Sm (Is_Elaboration_Warnings_OK_Node, Flag),
         Sm (Is_SPARK_Mode_On_Node, Flag),
         Sm (Redundant_Use, Flag)));
 
    Ab (N_Direct_Name, N_Has_Entity,
-       (Sm (Has_Private_View, Flag)));
+       (Sm (Has_Private_View, Flag),
+        Sm (Has_Secondary_Private_View, Flag)));
 
    Cc (N_Identifier, N_Direct_Name,
        (Sy (Chars, Name_Id, Default_No_Name),
@@ -197,7 +199,8 @@ begin -- Gen_IL.Gen.Gen_Nodes
 
    Ab (N_Op, N_Has_Entity,
        (Sm (Do_Overflow_Check, Flag),
-        Sm (Has_Private_View, Flag)));
+        Sm (Has_Private_View, Flag),
+        Sm (Has_Secondary_Private_View, Flag)));
 
    Ab (N_Binary_Op, N_Op);
 
diff --git a/gcc/ada/gnat_ugn.texi b/gcc/ada/gnat_ugn.texi
index 88123df..b85711b 100644
--- a/gcc/ada/gnat_ugn.texi
+++ b/gcc/ada/gnat_ugn.texi
@@ -19,7 +19,7 @@
 
 @copying
 @quotation
-GNAT User's Guide for Native Platforms , Jun 01, 2023
+GNAT User's Guide for Native Platforms , Jun 16, 2023
 
 AdaCore
 
@@ -198,6 +198,7 @@ Mixed Language Programming
 * Interfacing to C:: 
 * Calling Conventions:: 
 * Building Mixed Ada and C++ Programs:: 
+* Partition-Wide Settings:: 
 * Generating Ada Bindings for C and C++ headers:: 
 * Generating C Headers for Ada Specifications:: 
 
@@ -5086,6 +5087,7 @@ with a focus on combining Ada with C or C++.
 * Interfacing to C:: 
 * Calling Conventions:: 
 * Building Mixed Ada and C++ Programs:: 
+* Partition-Wide Settings:: 
 * Generating Ada Bindings for C and C++ headers:: 
 * Generating C Headers for Ada Specifications:: 
 
@@ -5638,7 +5640,7 @@ And from now on the identifier Fortran77 may be used as a convention
 identifier (for example in an @code{Import} pragma) with the same
 meaning as Fortran.
 
-@node Building Mixed Ada and C++ Programs,Generating Ada Bindings for C and C++ headers,Calling Conventions,Mixed Language Programming
+@node Building Mixed Ada and C++ Programs,Partition-Wide Settings,Calling Conventions,Mixed Language Programming
 @anchor{gnat_ugn/the_gnat_compilation_model building-mixed-ada-and-c-programs}@anchor{a3}@anchor{gnat_ugn/the_gnat_compilation_model id64}@anchor{a4}
 @subsection Building Mixed Ada and C++ Programs
 
@@ -6377,8 +6379,68 @@ int main ()
 @}
 @end example
 
-@node Generating Ada Bindings for C and C++ headers,Generating C Headers for Ada Specifications,Building Mixed Ada and C++ Programs,Mixed Language Programming
-@anchor{gnat_ugn/the_gnat_compilation_model generating-ada-bindings-for-c-and-c-headers}@anchor{a7}@anchor{gnat_ugn/the_gnat_compilation_model id70}@anchor{b0}
+@node Partition-Wide Settings,Generating Ada Bindings for C and C++ headers,Building Mixed Ada and C++ Programs,Mixed Language Programming
+@anchor{gnat_ugn/the_gnat_compilation_model id70}@anchor{b0}@anchor{gnat_ugn/the_gnat_compilation_model partition-wide-settings}@anchor{b1}
+@subsection Partition-Wide Settings
+
+
+When building a mixed-language application it is important to be aware that
+Ada enforces some partition-wide settings that may implicitly impact the
+behavior of the other languages.
+
+This is the case of certain signals that are reserved to the
+implementation to implement proper Ada semantics (such as the behavior
+of @code{abort} statements).
+
+It means that the Ada part of the application may override signal handlers
+that were previously installed by either the system or by other user code.
+
+If your application requires that either system or user signals be preserved
+then you need to instruct the Ada part not to install its own signal handler.
+This is done using @code{pragma Interrupt_State} that provides a general
+mechanism for overriding such uses of interrupts.
+
+The set of interrupts for which the Ada run-time library sets a specific signal
+handler is the following:
+
+
+@itemize *
+
+@item 
+Ada.Interrupts.Names.SIGSEGV
+
+@item 
+Ada.Interrupts.Names.SIGBUS
+
+@item 
+Ada.Interrupts.Names.SIGFPE
+
+@item 
+Ada.Interrupts.Names.SIGILL
+
+@item 
+Ada.Interrupts.Names.SIGABRT
+@end itemize
+
+The run-time library can be instructed not to install its signal handler for a
+particular signal by using the configuration pragma @code{Interrupt_State} in the
+Ada code. For example:
+
+@example
+pragma Interrupt_State (Ada.Interrupts.Names.SIGSEGV, System);
+pragma Interrupt_State (Ada.Interrupts.Names.SIGBUS,  System);
+pragma Interrupt_State (Ada.Interrupts.Names.SIGFPE,  System);
+pragma Interrupt_State (Ada.Interrupts.Names.SIGILL,  System);
+pragma Interrupt_State (Ada.Interrupts.Names.SIGABRT, System);
+@end example
+
+Obviously, if the Ada run-time system cannot set these handlers it comes with the
+drawback of not fully preserving Ada semantics. @code{SIGSEGV}, @code{SIGBUS}, @code{SIGFPE}
+and @code{SIGILL} are used to raise corresponding Ada exceptions in the application,
+while @code{SIGABRT} is used to asynchronously abort an action or a task.
+
+@node Generating Ada Bindings for C and C++ headers,Generating C Headers for Ada Specifications,Partition-Wide Settings,Mixed Language Programming
+@anchor{gnat_ugn/the_gnat_compilation_model generating-ada-bindings-for-c-and-c-headers}@anchor{a7}@anchor{gnat_ugn/the_gnat_compilation_model id71}@anchor{b2}
 @subsection Generating Ada Bindings for C and C++ headers
 
 
@@ -6429,7 +6491,7 @@ even if your code is compiled using earlier versions of Ada (e.g. @code{-gnat95}
 @end menu
 
 @node Running the Binding Generator,Generating Bindings for C++ Headers,,Generating Ada Bindings for C and C++ headers
-@anchor{gnat_ugn/the_gnat_compilation_model id71}@anchor{b1}@anchor{gnat_ugn/the_gnat_compilation_model running-the-binding-generator}@anchor{b2}
+@anchor{gnat_ugn/the_gnat_compilation_model id72}@anchor{b3}@anchor{gnat_ugn/the_gnat_compilation_model running-the-binding-generator}@anchor{b4}
 @subsubsection Running the Binding Generator
 
 
@@ -6495,7 +6557,7 @@ $ gcc -c -fdump-ada-spec readline1.h
 @end example
 
 @node Generating Bindings for C++ Headers,Switches,Running the Binding Generator,Generating Ada Bindings for C and C++ headers
-@anchor{gnat_ugn/the_gnat_compilation_model generating-bindings-for-c-headers}@anchor{b3}@anchor{gnat_ugn/the_gnat_compilation_model id72}@anchor{b4}
+@anchor{gnat_ugn/the_gnat_compilation_model generating-bindings-for-c-headers}@anchor{b5}@anchor{gnat_ugn/the_gnat_compilation_model id73}@anchor{b6}
 @subsubsection Generating Bindings for C++ Headers
 
 
@@ -6596,7 +6658,7 @@ use Class_Dog;
 @end example
 
 @node Switches,,Generating Bindings for C++ Headers,Generating Ada Bindings for C and C++ headers
-@anchor{gnat_ugn/the_gnat_compilation_model switches}@anchor{b5}@anchor{gnat_ugn/the_gnat_compilation_model switches-for-ada-binding-generation}@anchor{b6}
+@anchor{gnat_ugn/the_gnat_compilation_model switches}@anchor{b7}@anchor{gnat_ugn/the_gnat_compilation_model switches-for-ada-binding-generation}@anchor{b8}
 @subsubsection Switches
 
 
@@ -6644,7 +6706,7 @@ Extract comments from headers and generate Ada comments in the Ada spec files.
 @end table
 
 @node Generating C Headers for Ada Specifications,,Generating Ada Bindings for C and C++ headers,Mixed Language Programming
-@anchor{gnat_ugn/the_gnat_compilation_model generating-c-headers-for-ada-specifications}@anchor{b7}@anchor{gnat_ugn/the_gnat_compilation_model id73}@anchor{b8}
+@anchor{gnat_ugn/the_gnat_compilation_model generating-c-headers-for-ada-specifications}@anchor{b9}@anchor{gnat_ugn/the_gnat_compilation_model id74}@anchor{ba}
 @subsection Generating C Headers for Ada Specifications
 
 
@@ -6687,7 +6749,7 @@ Subprogram declarations
 @end menu
 
 @node Running the C Header Generator,,,Generating C Headers for Ada Specifications
-@anchor{gnat_ugn/the_gnat_compilation_model running-the-c-header-generator}@anchor{b9}
+@anchor{gnat_ugn/the_gnat_compilation_model running-the-c-header-generator}@anchor{bb}
 @subsubsection Running the C Header Generator
 
 
@@ -6755,7 +6817,7 @@ You can then @code{include} @code{pack1.h} from a C source file and use the type
 call subprograms, reference objects, and constants.
 
 @node GNAT and Other Compilation Models,Using GNAT Files with External Tools,Mixed Language Programming,The GNAT Compilation Model
-@anchor{gnat_ugn/the_gnat_compilation_model gnat-and-other-compilation-models}@anchor{2d}@anchor{gnat_ugn/the_gnat_compilation_model id74}@anchor{ba}
+@anchor{gnat_ugn/the_gnat_compilation_model gnat-and-other-compilation-models}@anchor{2d}@anchor{gnat_ugn/the_gnat_compilation_model id75}@anchor{bc}
 @section GNAT and Other Compilation Models
 
 
@@ -6771,7 +6833,7 @@ used for Ada 83.
 @end menu
 
 @node Comparison between GNAT and C/C++ Compilation Models,Comparison between GNAT and Conventional Ada Library Models,,GNAT and Other Compilation Models
-@anchor{gnat_ugn/the_gnat_compilation_model comparison-between-gnat-and-c-c-compilation-models}@anchor{bb}@anchor{gnat_ugn/the_gnat_compilation_model id75}@anchor{bc}
+@anchor{gnat_ugn/the_gnat_compilation_model comparison-between-gnat-and-c-c-compilation-models}@anchor{bd}@anchor{gnat_ugn/the_gnat_compilation_model id76}@anchor{be}
 @subsection Comparison between GNAT and C/C++ Compilation Models
 
 
@@ -6805,7 +6867,7 @@ elaboration, a C++ compiler would simply construct a program that
 malfunctioned at run time.
 
 @node Comparison between GNAT and Conventional Ada Library Models,,Comparison between GNAT and C/C++ Compilation Models,GNAT and Other Compilation Models
-@anchor{gnat_ugn/the_gnat_compilation_model comparison-between-gnat-and-conventional-ada-library-models}@anchor{bd}@anchor{gnat_ugn/the_gnat_compilation_model id76}@anchor{be}
+@anchor{gnat_ugn/the_gnat_compilation_model comparison-between-gnat-and-conventional-ada-library-models}@anchor{bf}@anchor{gnat_ugn/the_gnat_compilation_model id77}@anchor{c0}
 @subsection Comparison between GNAT and Conventional Ada Library Models
 
 
@@ -6873,7 +6935,7 @@ of rules saying what source files must be present when a file is
 compiled.
 
 @node Using GNAT Files with External Tools,,GNAT and Other Compilation Models,The GNAT Compilation Model
-@anchor{gnat_ugn/the_gnat_compilation_model id77}@anchor{bf}@anchor{gnat_ugn/the_gnat_compilation_model using-gnat-files-with-external-tools}@anchor{2e}
+@anchor{gnat_ugn/the_gnat_compilation_model id78}@anchor{c1}@anchor{gnat_ugn/the_gnat_compilation_model using-gnat-files-with-external-tools}@anchor{2e}
 @section Using GNAT Files with External Tools
 
 
@@ -6887,7 +6949,7 @@ used with tools designed for other languages.
 @end menu
 
 @node Using Other Utility Programs with GNAT,The External Symbol Naming Scheme of GNAT,,Using GNAT Files with External Tools
-@anchor{gnat_ugn/the_gnat_compilation_model id78}@anchor{c0}@anchor{gnat_ugn/the_gnat_compilation_model using-other-utility-programs-with-gnat}@anchor{c1}
+@anchor{gnat_ugn/the_gnat_compilation_model id79}@anchor{c2}@anchor{gnat_ugn/the_gnat_compilation_model using-other-utility-programs-with-gnat}@anchor{c3}
 @subsection Using Other Utility Programs with GNAT
 
 
@@ -6902,7 +6964,7 @@ gprof (a profiling program), gdb (the FSF debugger), and utilities such
 as Purify.
 
 @node The External Symbol Naming Scheme of GNAT,,Using Other Utility Programs with GNAT,Using GNAT Files with External Tools
-@anchor{gnat_ugn/the_gnat_compilation_model id79}@anchor{c2}@anchor{gnat_ugn/the_gnat_compilation_model the-external-symbol-naming-scheme-of-gnat}@anchor{c3}
+@anchor{gnat_ugn/the_gnat_compilation_model id80}@anchor{c4}@anchor{gnat_ugn/the_gnat_compilation_model the-external-symbol-naming-scheme-of-gnat}@anchor{c5}
 @subsection The External Symbol Naming Scheme of GNAT
 
 
@@ -6961,19 +7023,19 @@ the external name of this procedure will be @code{_ada_hello}.
 @c -- Example: A |withing| unit has a |with| clause, it |withs| a |withed| unit
 
 @node Building Executable Programs with GNAT,GNAT Utility Programs,The GNAT Compilation Model,Top
-@anchor{gnat_ugn/building_executable_programs_with_gnat doc}@anchor{c4}@anchor{gnat_ugn/building_executable_programs_with_gnat building-executable-programs-with-gnat}@anchor{a}@anchor{gnat_ugn/building_executable_programs_with_gnat id1}@anchor{c5}
+@anchor{gnat_ugn/building_executable_programs_with_gnat doc}@anchor{c6}@anchor{gnat_ugn/building_executable_programs_with_gnat building-executable-programs-with-gnat}@anchor{a}@anchor{gnat_ugn/building_executable_programs_with_gnat id1}@anchor{c7}
 @chapter Building Executable Programs with GNAT
 
 
 This chapter describes first the gnatmake tool
-(@ref{c6,,Building with gnatmake}),
+(@ref{c8,,Building with gnatmake}),
 which automatically determines the set of sources
 needed by an Ada compilation unit and executes the necessary
 (re)compilations, binding and linking.
 It also explains how to use each tool individually: the
-compiler (gcc, see @ref{c7,,Compiling with gcc}),
-binder (gnatbind, see @ref{c8,,Binding with gnatbind}),
-and linker (gnatlink, see @ref{c9,,Linking with gnatlink})
+compiler (gcc, see @ref{c9,,Compiling with gcc}),
+binder (gnatbind, see @ref{ca,,Binding with gnatbind}),
+and linker (gnatlink, see @ref{cb,,Linking with gnatlink})
 to build executable programs.
 Finally, this chapter provides examples of
 how to make use of the general GNU make mechanism
@@ -6992,7 +7054,7 @@ in a GNAT context (see @ref{70,,Using the GNU make Utility}).
 @end menu
 
 @node Building with gnatmake,Compiling with gcc,,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat building-with-gnatmake}@anchor{ca}@anchor{gnat_ugn/building_executable_programs_with_gnat the-gnat-make-program-gnatmake}@anchor{c6}
+@anchor{gnat_ugn/building_executable_programs_with_gnat building-with-gnatmake}@anchor{cc}@anchor{gnat_ugn/building_executable_programs_with_gnat the-gnat-make-program-gnatmake}@anchor{c8}
 @section Building with @code{gnatmake}
 
 
@@ -7056,7 +7118,7 @@ to @code{gnatmake}.
 @end menu
 
 @node Running gnatmake,Switches for gnatmake,,Building with gnatmake
-@anchor{gnat_ugn/building_executable_programs_with_gnat id2}@anchor{cb}@anchor{gnat_ugn/building_executable_programs_with_gnat running-gnatmake}@anchor{cc}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id2}@anchor{cd}@anchor{gnat_ugn/building_executable_programs_with_gnat running-gnatmake}@anchor{ce}
 @subsection Running @code{gnatmake}
 
 
@@ -7091,7 +7153,7 @@ All @code{gnatmake} output (except when you specify @code{-M}) is sent to
 @code{-M} switch is sent to @code{stdout}.
 
 @node Switches for gnatmake,Mode Switches for gnatmake,Running gnatmake,Building with gnatmake
-@anchor{gnat_ugn/building_executable_programs_with_gnat id3}@anchor{cd}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gnatmake}@anchor{ce}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id3}@anchor{cf}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gnatmake}@anchor{d0}
 @subsection Switches for @code{gnatmake}
 
 
@@ -7733,7 +7795,7 @@ Verbosity level High. Equivalent to -v.
 @item @code{-vP`x'}
 
 Indicate the verbosity of the parsing of GNAT project files.
-See @ref{cf,,Switches Related to Project Files}.
+See @ref{d1,,Switches Related to Project Files}.
 @end table
 
 @geindex -x (gnatmake)
@@ -7757,7 +7819,7 @@ command line need to be sources of a project file.
 Indicate that external variable @code{name} has the value @code{value}.
 The Project Manager will use this value for occurrences of
 @code{external(name)} when parsing the project file.
-@ref{cf,,Switches Related to Project Files}.
+@ref{d1,,Switches Related to Project Files}.
 @end table
 
 @geindex -z (gnatmake)
@@ -7928,7 +7990,7 @@ The selected path is handled like a normal RTS path.
 @end table
 
 @node Mode Switches for gnatmake,Notes on the Command Line,Switches for gnatmake,Building with gnatmake
-@anchor{gnat_ugn/building_executable_programs_with_gnat id4}@anchor{d0}@anchor{gnat_ugn/building_executable_programs_with_gnat mode-switches-for-gnatmake}@anchor{d1}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id4}@anchor{d2}@anchor{gnat_ugn/building_executable_programs_with_gnat mode-switches-for-gnatmake}@anchor{d3}
 @subsection Mode Switches for @code{gnatmake}
 
 
@@ -7988,7 +8050,7 @@ or @code{-largs}.
 @end table
 
 @node Notes on the Command Line,How gnatmake Works,Mode Switches for gnatmake,Building with gnatmake
-@anchor{gnat_ugn/building_executable_programs_with_gnat id5}@anchor{d2}@anchor{gnat_ugn/building_executable_programs_with_gnat notes-on-the-command-line}@anchor{d3}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id5}@anchor{d4}@anchor{gnat_ugn/building_executable_programs_with_gnat notes-on-the-command-line}@anchor{d5}
 @subsection Notes on the Command Line
 
 
@@ -8058,7 +8120,7 @@ that the debugging information may be out of date.
 @end itemize
 
 @node How gnatmake Works,Examples of gnatmake Usage,Notes on the Command Line,Building with gnatmake
-@anchor{gnat_ugn/building_executable_programs_with_gnat how-gnatmake-works}@anchor{d4}@anchor{gnat_ugn/building_executable_programs_with_gnat id6}@anchor{d5}
+@anchor{gnat_ugn/building_executable_programs_with_gnat how-gnatmake-works}@anchor{d6}@anchor{gnat_ugn/building_executable_programs_with_gnat id6}@anchor{d7}
 @subsection How @code{gnatmake} Works
 
 
@@ -8105,7 +8167,7 @@ by @code{gnatmake}. It may be necessary to use the switch
 -f.
 
 @node Examples of gnatmake Usage,,How gnatmake Works,Building with gnatmake
-@anchor{gnat_ugn/building_executable_programs_with_gnat examples-of-gnatmake-usage}@anchor{d6}@anchor{gnat_ugn/building_executable_programs_with_gnat id7}@anchor{d7}
+@anchor{gnat_ugn/building_executable_programs_with_gnat examples-of-gnatmake-usage}@anchor{d8}@anchor{gnat_ugn/building_executable_programs_with_gnat id7}@anchor{d9}
 @subsection Examples of @code{gnatmake} Usage
 
 
@@ -8137,7 +8199,7 @@ displaying commands it is executing.
 @end table
 
 @node Compiling with gcc,Compiler Switches,Building with gnatmake,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat compiling-with-gcc}@anchor{c7}@anchor{gnat_ugn/building_executable_programs_with_gnat id8}@anchor{d8}
+@anchor{gnat_ugn/building_executable_programs_with_gnat compiling-with-gcc}@anchor{c9}@anchor{gnat_ugn/building_executable_programs_with_gnat id8}@anchor{da}
 @section Compiling with @code{gcc}
 
 
@@ -8154,7 +8216,7 @@ that can be used to control the behavior of the compiler.
 @end menu
 
 @node Compiling Programs,Search Paths and the Run-Time Library RTL,,Compiling with gcc
-@anchor{gnat_ugn/building_executable_programs_with_gnat compiling-programs}@anchor{d9}@anchor{gnat_ugn/building_executable_programs_with_gnat id9}@anchor{da}
+@anchor{gnat_ugn/building_executable_programs_with_gnat compiling-programs}@anchor{db}@anchor{gnat_ugn/building_executable_programs_with_gnat id9}@anchor{dc}
 @subsection Compiling Programs
 
 
@@ -8265,11 +8327,11 @@ calls @code{gnat1} (the Ada compiler) twice to compile @code{x.adb} and
 The compiler generates two object files @code{x.o} and @code{y.o}
 and the two ALI files @code{x.ali} and @code{y.ali}.
 
-Any switches apply to all the files listed, see @ref{db,,Compiler Switches} for a
+Any switches apply to all the files listed, see @ref{dd,,Compiler Switches} for a
 list of available @code{gcc} switches.
 
 @node Search Paths and the Run-Time Library RTL,Order of Compilation Issues,Compiling Programs,Compiling with gcc
-@anchor{gnat_ugn/building_executable_programs_with_gnat id10}@anchor{dc}@anchor{gnat_ugn/building_executable_programs_with_gnat search-paths-and-the-run-time-library-rtl}@anchor{73}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id10}@anchor{de}@anchor{gnat_ugn/building_executable_programs_with_gnat search-paths-and-the-run-time-library-rtl}@anchor{73}
 @subsection Search Paths and the Run-Time Library (RTL)
 
 
@@ -8368,7 +8430,7 @@ in compiling sources from multiple directories. This can make
 development environments much more flexible.
 
 @node Order of Compilation Issues,Examples,Search Paths and the Run-Time Library RTL,Compiling with gcc
-@anchor{gnat_ugn/building_executable_programs_with_gnat id11}@anchor{dd}@anchor{gnat_ugn/building_executable_programs_with_gnat order-of-compilation-issues}@anchor{de}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id11}@anchor{df}@anchor{gnat_ugn/building_executable_programs_with_gnat order-of-compilation-issues}@anchor{e0}
 @subsection Order of Compilation Issues
 
 
@@ -8409,7 +8471,7 @@ described above), or you will receive a fatal error message.
 @end itemize
 
 @node Examples,,Order of Compilation Issues,Compiling with gcc
-@anchor{gnat_ugn/building_executable_programs_with_gnat examples}@anchor{df}@anchor{gnat_ugn/building_executable_programs_with_gnat id12}@anchor{e0}
+@anchor{gnat_ugn/building_executable_programs_with_gnat examples}@anchor{e1}@anchor{gnat_ugn/building_executable_programs_with_gnat id12}@anchor{e2}
 @subsection Examples
 
 
@@ -8437,7 +8499,7 @@ Compile the subunit in file @code{abc-def.adb} in semantic-checking-only
 mode.
 
 @node Compiler Switches,Linker Switches,Compiling with gcc,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat compiler-switches}@anchor{e1}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gcc}@anchor{db}
+@anchor{gnat_ugn/building_executable_programs_with_gnat compiler-switches}@anchor{e3}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gcc}@anchor{dd}
 @section Compiler Switches
 
 
@@ -8476,7 +8538,7 @@ compilation units.
 @end menu
 
 @node Alphabetical List of All Switches,Output and Error Message Control,,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat alphabetical-list-of-all-switches}@anchor{e2}@anchor{gnat_ugn/building_executable_programs_with_gnat id13}@anchor{e3}
+@anchor{gnat_ugn/building_executable_programs_with_gnat alphabetical-list-of-all-switches}@anchor{e4}@anchor{gnat_ugn/building_executable_programs_with_gnat id13}@anchor{e5}
 @subsection Alphabetical List of All Switches
 
 
@@ -8674,7 +8736,7 @@ and thus producing inferior code.
 
 Causes the compiler to avoid assumptions regarding non-aliasing
 of objects of different types. See
-@ref{e4,,Optimization and Strict Aliasing} for details.
+@ref{e6,,Optimization and Strict Aliasing} for details.
 @end table
 
 @geindex -fno-strict-overflow (gcc)
@@ -8700,7 +8762,7 @@ for very peculiar cases of low-level programming.
 @item @code{-fstack-check}
 
 Activates stack checking.
-See @ref{e5,,Stack Overflow Checking} for details.
+See @ref{e7,,Stack Overflow Checking} for details.
 @end table
 
 @geindex -fstack-usage (gcc)
@@ -8711,7 +8773,7 @@ See @ref{e5,,Stack Overflow Checking} for details.
 @item @code{-fstack-usage}
 
 Makes the compiler output stack usage information for the program, on a
-per-subprogram basis. See @ref{e6,,Static Stack Usage Analysis} for details.
+per-subprogram basis. See @ref{e8,,Static Stack Usage Analysis} for details.
 @end table
 
 @geindex -g (gcc)
@@ -8851,7 +8913,7 @@ Generate brief messages to @code{stderr} even if verbose mode set.
 @item @code{-gnatB}
 
 Assume no invalid (bad) values except for ‘Valid attribute use
-(@ref{e7,,Validity Checking}).
+(@ref{e9,,Validity Checking}).
 @end table
 
 @geindex -gnatc (gcc)
@@ -9061,7 +9123,7 @@ for unconstrained predefined types. See description of pragma
 
 The @code{-gnatc} switch must always be specified before this switch, e.g.
 @code{-gnatceg}. Generate a C header from the Ada input file. See
-@ref{b7,,Generating C Headers for Ada Specifications} for more
+@ref{b9,,Generating C Headers for Ada Specifications} for more
 information.
 @end quotation
 
@@ -9075,6 +9137,18 @@ information.
 Save result of preprocessing in a text file.
 @end table
 
+@geindex -gnateH (gcc)
+
+
+@table @asis
+
+@item @code{-gnateH}
+
+Set the threshold from which the RM 13.5.1(13.3/2) clause applies to 64.
+This is useful only on 64-bit plaforms where this threshold is 128, but
+used to be 64 in earlier versions of the compiler.
+@end table
+
 @geindex -gnatei (gcc)
 
 
@@ -9135,7 +9209,7 @@ This switch turns off the info messages about implicit elaboration pragmas.
 
 Specify a mapping file
 (the equal sign is optional)
-(@ref{e8,,Units to Sources Mapping Files}).
+(@ref{ea,,Units to Sources Mapping Files}).
 @end table
 
 @geindex -gnatep (gcc)
@@ -9347,7 +9421,7 @@ support this switch.
 @item @code{-gnateV}
 
 Check that all actual parameters of a subprogram call are valid according to
-the rules of validity checking (@ref{e7,,Validity Checking}).
+the rules of validity checking (@ref{e9,,Validity Checking}).
 @end table
 
 @geindex -gnateY (gcc)
@@ -9699,7 +9773,7 @@ overflow checking is enabled.
 Note that division by zero is a separate check that is not
 controlled by this switch (divide-by-zero checking is on by default).
 
-See also @ref{e9,,Specifying the Desired Mode}.
+See also @ref{eb,,Specifying the Desired Mode}.
 @end table
 
 @geindex -gnatp (gcc)
@@ -9709,7 +9783,7 @@ See also @ref{e9,,Specifying the Desired Mode}.
 
 @item @code{-gnatp}
 
-Suppress all checks. See @ref{ea,,Run-Time Checks} for details. This switch
+Suppress all checks. See @ref{ec,,Run-Time Checks} for details. This switch
 has no effect if cancelled by a subsequent @code{-gnat-p} switch.
 @end table
 
@@ -9835,7 +9909,7 @@ Verbose mode. Full error output with source lines to @code{stdout}.
 
 @item @code{-gnatV}
 
-Control level of validity checking (@ref{e7,,Validity Checking}).
+Control level of validity checking (@ref{e9,,Validity Checking}).
 @end table
 
 @geindex -gnatw (gcc)
@@ -9848,7 +9922,7 @@ Control level of validity checking (@ref{e7,,Validity Checking}).
 Warning mode where
 @code{xxx} is a string of option letters that denotes
 the exact warnings that
-are enabled or disabled (@ref{eb,,Warning Message Control}).
+are enabled or disabled (@ref{ed,,Warning Message Control}).
 @end table
 
 @geindex -gnatW (gcc)
@@ -9899,7 +9973,7 @@ Enable all GNAT implementation extensions and latest Ada version.
 
 @item @code{-gnaty}
 
-Enable built-in style checks (@ref{ec,,Style Checking}).
+Enable built-in style checks (@ref{ee,,Style Checking}).
 @end table
 
 @geindex -gnatz (gcc)
@@ -10042,7 +10116,7 @@ Optimize space usage
 @end multitable
 
 
-See also @ref{ed,,Optimization Levels}.
+See also @ref{ef,,Optimization Levels}.
 @end table
 
 @geindex -pass-exit-codes (gcc)
@@ -10064,7 +10138,7 @@ exit status.
 @item @code{--RTS=`rts-path'}
 
 Specifies the default location of the run-time library. Same meaning as the
-equivalent @code{gnatmake} flag (@ref{ce,,Switches for gnatmake}).
+equivalent @code{gnatmake} flag (@ref{d0,,Switches for gnatmake}).
 @end table
 
 @geindex -S (gcc)
@@ -10190,7 +10264,7 @@ as warning mode modifiers (see description of @code{-gnatw}).
 @item 
 Once a ‘V’ appears in the string (that is a use of the @code{-gnatV}
 switch), then all further characters in the switch are interpreted
-as validity checking options (@ref{e7,,Validity Checking}).
+as validity checking options (@ref{e9,,Validity Checking}).
 
 @item 
 Option ‘em’, ‘ec’, ‘ep’, ‘l=’ and ‘R’ must be the last options in
@@ -10198,7 +10272,7 @@ a combined list of options.
 @end itemize
 
 @node Output and Error Message Control,Warning Message Control,Alphabetical List of All Switches,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id14}@anchor{ee}@anchor{gnat_ugn/building_executable_programs_with_gnat output-and-error-message-control}@anchor{ef}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id14}@anchor{f0}@anchor{gnat_ugn/building_executable_programs_with_gnat output-and-error-message-control}@anchor{f1}
 @subsection Output and Error Message Control
 
 
@@ -10493,7 +10567,7 @@ since ALI files are never generated if @code{-gnats} is set.
 @end table
 
 @node Warning Message Control,Debugging and Assertion Control,Output and Error Message Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id15}@anchor{f0}@anchor{gnat_ugn/building_executable_programs_with_gnat warning-message-control}@anchor{eb}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id15}@anchor{f2}@anchor{gnat_ugn/building_executable_programs_with_gnat warning-message-control}@anchor{ed}
 @subsection Warning Message Control
 
 
@@ -12697,7 +12771,7 @@ used in conjunction with an optimization level greater than zero.
 @item @code{-Wstack-usage=`len'}
 
 Warn if the stack usage of a subprogram might be larger than @code{len} bytes.
-See @ref{e6,,Static Stack Usage Analysis} for details.
+See @ref{e8,,Static Stack Usage Analysis} for details.
 @end table
 
 @geindex -Wall (gcc)
@@ -12898,7 +12972,7 @@ When no switch @code{-gnatw} is used, this is equivalent to:
 @end quotation
 
 @node Debugging and Assertion Control,Validity Checking,Warning Message Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat debugging-and-assertion-control}@anchor{f1}@anchor{gnat_ugn/building_executable_programs_with_gnat id16}@anchor{f2}
+@anchor{gnat_ugn/building_executable_programs_with_gnat debugging-and-assertion-control}@anchor{f3}@anchor{gnat_ugn/building_executable_programs_with_gnat id16}@anchor{f4}
 @subsection Debugging and Assertion Control
 
 
@@ -13003,7 +13077,7 @@ is @code{False}, the exception @code{Assert_Failure} is raised.
 @end table
 
 @node Validity Checking,Style Checking,Debugging and Assertion Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id17}@anchor{f3}@anchor{gnat_ugn/building_executable_programs_with_gnat validity-checking}@anchor{e7}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id17}@anchor{f5}@anchor{gnat_ugn/building_executable_programs_with_gnat validity-checking}@anchor{e9}
 @subsection Validity Checking
 
 
@@ -13301,7 +13375,7 @@ the validity checking mode at the program source level, and also allows for
 temporary disabling of validity checks.
 
 @node Style Checking,Run-Time Checks,Validity Checking,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id18}@anchor{f4}@anchor{gnat_ugn/building_executable_programs_with_gnat style-checking}@anchor{ec}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id18}@anchor{f6}@anchor{gnat_ugn/building_executable_programs_with_gnat style-checking}@anchor{ee}
 @subsection Style Checking
 
 
@@ -14054,7 +14128,7 @@ built-in standard style check options are enabled.
 The switch @code{-gnatyN} clears any previously set style checks.
 
 @node Run-Time Checks,Using gcc for Syntax Checking,Style Checking,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id19}@anchor{f5}@anchor{gnat_ugn/building_executable_programs_with_gnat run-time-checks}@anchor{ea}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id19}@anchor{f7}@anchor{gnat_ugn/building_executable_programs_with_gnat run-time-checks}@anchor{ec}
 @subsection Run-Time Checks
 
 
@@ -14248,7 +14322,7 @@ on subprogram calls and generic instantiations.
 Note that @code{-gnatE} is not necessary for safety, because in the
 default mode, GNAT ensures statically that the checks would not fail.
 For full details of the effect and use of this switch,
-@ref{c7,,Compiling with gcc}.
+@ref{c9,,Compiling with gcc}.
 @end table
 
 @geindex -fstack-check (gcc)
@@ -14264,7 +14338,7 @@ For full details of the effect and use of this switch,
 @item @code{-fstack-check}
 
 Activates stack overflow checking. For full details of the effect and use of
-this switch see @ref{e5,,Stack Overflow Checking}.
+this switch see @ref{e7,,Stack Overflow Checking}.
 @end table
 
 @geindex Unsuppress
@@ -14275,7 +14349,7 @@ checks) or @code{Unsuppress} (to add back suppressed checks) pragmas in
 the program source.
 
 @node Using gcc for Syntax Checking,Using gcc for Semantic Checking,Run-Time Checks,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id20}@anchor{f6}@anchor{gnat_ugn/building_executable_programs_with_gnat using-gcc-for-syntax-checking}@anchor{f7}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id20}@anchor{f8}@anchor{gnat_ugn/building_executable_programs_with_gnat using-gcc-for-syntax-checking}@anchor{f9}
 @subsection Using @code{gcc} for Syntax Checking
 
 
@@ -14332,7 +14406,7 @@ together. This is primarily used by the @code{gnatchop} utility
 @end table
 
 @node Using gcc for Semantic Checking,Compiling Different Versions of Ada,Using gcc for Syntax Checking,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id21}@anchor{f8}@anchor{gnat_ugn/building_executable_programs_with_gnat using-gcc-for-semantic-checking}@anchor{f9}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id21}@anchor{fa}@anchor{gnat_ugn/building_executable_programs_with_gnat using-gcc-for-semantic-checking}@anchor{fb}
 @subsection Using @code{gcc} for Semantic Checking
 
 
@@ -14379,7 +14453,7 @@ and specifications where a separate body is present).
 @end table
 
 @node Compiling Different Versions of Ada,Character Set Control,Using gcc for Semantic Checking,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat compiling-different-versions-of-ada}@anchor{6}@anchor{gnat_ugn/building_executable_programs_with_gnat id22}@anchor{fa}
+@anchor{gnat_ugn/building_executable_programs_with_gnat compiling-different-versions-of-ada}@anchor{6}@anchor{gnat_ugn/building_executable_programs_with_gnat id22}@anchor{fc}
 @subsection Compiling Different Versions of Ada
 
 
@@ -14544,7 +14618,7 @@ extensions enabled by this switch, see the GNAT reference manual
 @end table
 
 @node Character Set Control,File Naming Control,Compiling Different Versions of Ada,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat character-set-control}@anchor{31}@anchor{gnat_ugn/building_executable_programs_with_gnat id23}@anchor{fb}
+@anchor{gnat_ugn/building_executable_programs_with_gnat character-set-control}@anchor{31}@anchor{gnat_ugn/building_executable_programs_with_gnat id23}@anchor{fd}
 @subsection Character Set Control
 
 
@@ -14771,7 +14845,7 @@ comments are ended by an appropriate (CR, or CR/LF, or LF) line terminator.
 This is a common mode for many programs with foreign language comments.
 
 @node File Naming Control,Subprogram Inlining Control,Character Set Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat file-naming-control}@anchor{fc}@anchor{gnat_ugn/building_executable_programs_with_gnat id24}@anchor{fd}
+@anchor{gnat_ugn/building_executable_programs_with_gnat file-naming-control}@anchor{fe}@anchor{gnat_ugn/building_executable_programs_with_gnat id24}@anchor{ff}
 @subsection File Naming Control
 
 
@@ -14791,7 +14865,7 @@ For the source file naming rules, @ref{3b,,File Naming Rules}.
 @end table
 
 @node Subprogram Inlining Control,Auxiliary Output Control,File Naming Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id25}@anchor{fe}@anchor{gnat_ugn/building_executable_programs_with_gnat subprogram-inlining-control}@anchor{ff}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id25}@anchor{100}@anchor{gnat_ugn/building_executable_programs_with_gnat subprogram-inlining-control}@anchor{101}
 @subsection Subprogram Inlining Control
 
 
@@ -14824,7 +14898,7 @@ If you specify this switch the compiler will access these bodies,
 creating an extra source dependency for the resulting object file, and
 where possible, the call will be inlined.
 For further details on when inlining is possible
-see @ref{100,,Inlining of Subprograms}.
+see @ref{102,,Inlining of Subprograms}.
 @end table
 
 @geindex -gnatN (gcc)
@@ -14844,7 +14918,7 @@ inlining, but that is no longer the case.
 @end table
 
 @node Auxiliary Output Control,Debugging Control,Subprogram Inlining Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat auxiliary-output-control}@anchor{101}@anchor{gnat_ugn/building_executable_programs_with_gnat id26}@anchor{102}
+@anchor{gnat_ugn/building_executable_programs_with_gnat auxiliary-output-control}@anchor{103}@anchor{gnat_ugn/building_executable_programs_with_gnat id26}@anchor{104}
 @subsection Auxiliary Output Control
 
 
@@ -14914,7 +14988,7 @@ An object file has been generated for every source file.
 @end table
 
 @node Debugging Control,Exception Handling Control,Auxiliary Output Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat debugging-control}@anchor{103}@anchor{gnat_ugn/building_executable_programs_with_gnat id27}@anchor{104}
+@anchor{gnat_ugn/building_executable_programs_with_gnat debugging-control}@anchor{105}@anchor{gnat_ugn/building_executable_programs_with_gnat id27}@anchor{106}
 @subsection Debugging Control
 
 
@@ -15263,7 +15337,7 @@ encodings for the rest.
 @end table
 
 @node Exception Handling Control,Units to Sources Mapping Files,Debugging Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat exception-handling-control}@anchor{105}@anchor{gnat_ugn/building_executable_programs_with_gnat id28}@anchor{106}
+@anchor{gnat_ugn/building_executable_programs_with_gnat exception-handling-control}@anchor{107}@anchor{gnat_ugn/building_executable_programs_with_gnat id28}@anchor{108}
 @subsection Exception Handling Control
 
 
@@ -15331,11 +15405,11 @@ is available for the target in use, otherwise it will generate an error.
 
 The same option @code{--RTS} must be used both for @code{gcc}
 and @code{gnatbind}. Passing this option to @code{gnatmake}
-(@ref{ce,,Switches for gnatmake}) will ensure the required consistency
+(@ref{d0,,Switches for gnatmake}) will ensure the required consistency
 through the compilation and binding steps.
 
 @node Units to Sources Mapping Files,Code Generation Control,Exception Handling Control,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat id29}@anchor{107}@anchor{gnat_ugn/building_executable_programs_with_gnat units-to-sources-mapping-files}@anchor{e8}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id29}@anchor{109}@anchor{gnat_ugn/building_executable_programs_with_gnat units-to-sources-mapping-files}@anchor{ea}
 @subsection Units to Sources Mapping Files
 
 
@@ -15387,7 +15461,7 @@ mapping file and communicates it to the compiler using this switch.
 @end table
 
 @node Code Generation Control,,Units to Sources Mapping Files,Compiler Switches
-@anchor{gnat_ugn/building_executable_programs_with_gnat code-generation-control}@anchor{108}@anchor{gnat_ugn/building_executable_programs_with_gnat id30}@anchor{109}
+@anchor{gnat_ugn/building_executable_programs_with_gnat code-generation-control}@anchor{10a}@anchor{gnat_ugn/building_executable_programs_with_gnat id30}@anchor{10b}
 @subsection Code Generation Control
 
 
@@ -15416,7 +15490,7 @@ there is no point in using @code{-m} switches to improve performance
 unless you actually see a performance improvement.
 
 @node Linker Switches,Binding with gnatbind,Compiler Switches,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat id31}@anchor{10a}@anchor{gnat_ugn/building_executable_programs_with_gnat linker-switches}@anchor{10b}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id31}@anchor{10c}@anchor{gnat_ugn/building_executable_programs_with_gnat linker-switches}@anchor{10d}
 @section Linker Switches
 
 
@@ -15437,7 +15511,7 @@ platforms.
 @end table
 
 @node Binding with gnatbind,Linking with gnatlink,Linker Switches,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat binding-with-gnatbind}@anchor{c8}@anchor{gnat_ugn/building_executable_programs_with_gnat id32}@anchor{10c}
+@anchor{gnat_ugn/building_executable_programs_with_gnat binding-with-gnatbind}@anchor{ca}@anchor{gnat_ugn/building_executable_programs_with_gnat id32}@anchor{10e}
 @section Binding with @code{gnatbind}
 
 
@@ -15488,7 +15562,7 @@ to be read by the @code{gnatlink} utility used to link the Ada application.
 @end menu
 
 @node Running gnatbind,Switches for gnatbind,,Binding with gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat id33}@anchor{10d}@anchor{gnat_ugn/building_executable_programs_with_gnat running-gnatbind}@anchor{10e}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id33}@anchor{10f}@anchor{gnat_ugn/building_executable_programs_with_gnat running-gnatbind}@anchor{110}
 @subsection Running @code{gnatbind}
 
 
@@ -15573,7 +15647,7 @@ Ada code provided the @code{-g} switch is used for
 @code{gnatbind} and @code{gnatlink}.
 
 @node Switches for gnatbind,Command-Line Access,Running gnatbind,Binding with gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat id34}@anchor{10f}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gnatbind}@anchor{110}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id34}@anchor{111}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gnatbind}@anchor{112}
 @subsection Switches for @code{gnatbind}
 
 
@@ -15768,7 +15842,7 @@ Currently the same as @code{-Ea}.
 
 @item @code{-f`elab-order'}
 
-Force elaboration order. For further details see @ref{111,,Elaboration Control}
+Force elaboration order. For further details see @ref{113,,Elaboration Control}
 and @ref{f,,Elaboration Order Handling in GNAT}.
 @end table
 
@@ -15817,7 +15891,7 @@ Legacy elaboration order model enabled. For further details see
 @item @code{-H32}
 
 Use 32-bit allocations for @code{__gnat_malloc} (and thus for access types).
-For further details see @ref{112,,Dynamic Allocation Control}.
+For further details see @ref{114,,Dynamic Allocation Control}.
 @end table
 
 @geindex -H64 (gnatbind)
@@ -15830,7 +15904,7 @@ For further details see @ref{112,,Dynamic Allocation Control}.
 @item @code{-H64}
 
 Use 64-bit allocations for @code{__gnat_malloc} (and thus for access types).
-For further details see @ref{112,,Dynamic Allocation Control}.
+For further details see @ref{114,,Dynamic Allocation Control}.
 
 @geindex -I (gnatbind)
 
@@ -15944,7 +16018,7 @@ Do not look for library files in the system default directory.
 @item @code{--RTS=`rts-path'}
 
 Specifies the default location of the run-time library. Same meaning as the
-equivalent @code{gnatmake} flag (@ref{ce,,Switches for gnatmake}).
+equivalent @code{gnatmake} flag (@ref{d0,,Switches for gnatmake}).
 
 @geindex -o (gnatbind)
 
@@ -16098,7 +16172,7 @@ Enable dynamic stack usage, with @code{n} results stored and displayed
 at program termination. A result is generated when a task
 terminates. Results that can’t be stored are displayed on the fly, at
 task termination. This option is currently not supported on Itanium
-platforms. (See @ref{113,,Dynamic Stack Usage Analysis} for details.)
+platforms. (See @ref{115,,Dynamic Stack Usage Analysis} for details.)
 
 @geindex -v (gnatbind)
 
@@ -16178,7 +16252,7 @@ no arguments.
 @end menu
 
 @node Consistency-Checking Modes,Binder Error Message Control,,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat consistency-checking-modes}@anchor{114}@anchor{gnat_ugn/building_executable_programs_with_gnat id35}@anchor{115}
+@anchor{gnat_ugn/building_executable_programs_with_gnat consistency-checking-modes}@anchor{116}@anchor{gnat_ugn/building_executable_programs_with_gnat id35}@anchor{117}
 @subsubsection Consistency-Checking Modes
 
 
@@ -16232,7 +16306,7 @@ case the checking against sources has already been performed by
 @end table
 
 @node Binder Error Message Control,Elaboration Control,Consistency-Checking Modes,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat binder-error-message-control}@anchor{116}@anchor{gnat_ugn/building_executable_programs_with_gnat id36}@anchor{117}
+@anchor{gnat_ugn/building_executable_programs_with_gnat binder-error-message-control}@anchor{118}@anchor{gnat_ugn/building_executable_programs_with_gnat id36}@anchor{119}
 @subsubsection Binder Error Message Control
 
 
@@ -16342,7 +16416,7 @@ with extreme care.
 @end table
 
 @node Elaboration Control,Output Control,Binder Error Message Control,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat elaboration-control}@anchor{111}@anchor{gnat_ugn/building_executable_programs_with_gnat id37}@anchor{118}
+@anchor{gnat_ugn/building_executable_programs_with_gnat elaboration-control}@anchor{113}@anchor{gnat_ugn/building_executable_programs_with_gnat id37}@anchor{11a}
 @subsubsection Elaboration Control
 
 
@@ -16427,7 +16501,7 @@ debugging/experimental use.
 @end table
 
 @node Output Control,Dynamic Allocation Control,Elaboration Control,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat id38}@anchor{119}@anchor{gnat_ugn/building_executable_programs_with_gnat output-control}@anchor{11a}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id38}@anchor{11b}@anchor{gnat_ugn/building_executable_programs_with_gnat output-control}@anchor{11c}
 @subsubsection Output Control
 
 
@@ -16508,7 +16582,7 @@ be used to improve code generation in some cases.
 @end table
 
 @node Dynamic Allocation Control,Binding with Non-Ada Main Programs,Output Control,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat dynamic-allocation-control}@anchor{112}@anchor{gnat_ugn/building_executable_programs_with_gnat id39}@anchor{11b}
+@anchor{gnat_ugn/building_executable_programs_with_gnat dynamic-allocation-control}@anchor{114}@anchor{gnat_ugn/building_executable_programs_with_gnat id39}@anchor{11d}
 @subsubsection Dynamic Allocation Control
 
 
@@ -16534,7 +16608,7 @@ unless explicitly overridden by a @code{'Size} clause on the access type.
 These switches are only effective on VMS platforms.
 
 @node Binding with Non-Ada Main Programs,Binding Programs with No Main Subprogram,Dynamic Allocation Control,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat binding-with-non-ada-main-programs}@anchor{a0}@anchor{gnat_ugn/building_executable_programs_with_gnat id40}@anchor{11c}
+@anchor{gnat_ugn/building_executable_programs_with_gnat binding-with-non-ada-main-programs}@anchor{a0}@anchor{gnat_ugn/building_executable_programs_with_gnat id40}@anchor{11e}
 @subsubsection Binding with Non-Ada Main Programs
 
 
@@ -16630,7 +16704,7 @@ side effect is that this could be the wrong mode for the foreign code
 where floating point computation could be broken after this call.
 
 @node Binding Programs with No Main Subprogram,,Binding with Non-Ada Main Programs,Switches for gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat binding-programs-with-no-main-subprogram}@anchor{11d}@anchor{gnat_ugn/building_executable_programs_with_gnat id41}@anchor{11e}
+@anchor{gnat_ugn/building_executable_programs_with_gnat binding-programs-with-no-main-subprogram}@anchor{11f}@anchor{gnat_ugn/building_executable_programs_with_gnat id41}@anchor{120}
 @subsubsection Binding Programs with No Main Subprogram
 
 
@@ -16661,7 +16735,7 @@ the binder switch
 @end table
 
 @node Command-Line Access,Search Paths for gnatbind,Switches for gnatbind,Binding with gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat command-line-access}@anchor{11f}@anchor{gnat_ugn/building_executable_programs_with_gnat id42}@anchor{120}
+@anchor{gnat_ugn/building_executable_programs_with_gnat command-line-access}@anchor{121}@anchor{gnat_ugn/building_executable_programs_with_gnat id42}@anchor{122}
 @subsection Command-Line Access
 
 
@@ -16691,7 +16765,7 @@ required, your main program must set @code{gnat_argc} and
 it.
 
 @node Search Paths for gnatbind,Examples of gnatbind Usage,Command-Line Access,Binding with gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat id43}@anchor{121}@anchor{gnat_ugn/building_executable_programs_with_gnat search-paths-for-gnatbind}@anchor{76}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id43}@anchor{123}@anchor{gnat_ugn/building_executable_programs_with_gnat search-paths-for-gnatbind}@anchor{76}
 @subsection Search Paths for @code{gnatbind}
 
 
@@ -16795,7 +16869,7 @@ in compiling sources from multiple directories. This can make
 development environments much more flexible.
 
 @node Examples of gnatbind Usage,,Search Paths for gnatbind,Binding with gnatbind
-@anchor{gnat_ugn/building_executable_programs_with_gnat examples-of-gnatbind-usage}@anchor{122}@anchor{gnat_ugn/building_executable_programs_with_gnat id44}@anchor{123}
+@anchor{gnat_ugn/building_executable_programs_with_gnat examples-of-gnatbind-usage}@anchor{124}@anchor{gnat_ugn/building_executable_programs_with_gnat id44}@anchor{125}
 @subsection Examples of @code{gnatbind} Usage
 
 
@@ -16824,7 +16898,7 @@ since gnatlink will not be able to find the generated file.
 @end quotation
 
 @node Linking with gnatlink,Using the GNU make Utility,Binding with gnatbind,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat id45}@anchor{124}@anchor{gnat_ugn/building_executable_programs_with_gnat linking-with-gnatlink}@anchor{c9}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id45}@anchor{126}@anchor{gnat_ugn/building_executable_programs_with_gnat linking-with-gnatlink}@anchor{cb}
 @section Linking with @code{gnatlink}
 
 
@@ -16845,7 +16919,7 @@ generated by the @code{gnatbind} to determine this list.
 @end menu
 
 @node Running gnatlink,Switches for gnatlink,,Linking with gnatlink
-@anchor{gnat_ugn/building_executable_programs_with_gnat id46}@anchor{125}@anchor{gnat_ugn/building_executable_programs_with_gnat running-gnatlink}@anchor{126}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id46}@anchor{127}@anchor{gnat_ugn/building_executable_programs_with_gnat running-gnatlink}@anchor{128}
 @subsection Running @code{gnatlink}
 
 
@@ -16904,8 +16978,8 @@ $ gnatlink my_prog -Wl,-Map,MAPFILE
 
 Using @code{linker options} it is possible to set the program stack and
 heap size.
-See @ref{127,,Setting Stack Size from gnatlink} and
-@ref{128,,Setting Heap Size from gnatlink}.
+See @ref{129,,Setting Stack Size from gnatlink} and
+@ref{12a,,Setting Heap Size from gnatlink}.
 
 @code{gnatlink} determines the list of objects required by the Ada
 program and prepends them to the list of objects passed to the linker.
@@ -16914,7 +16988,7 @@ program and prepends them to the list of objects passed to the linker.
 presented to the linker.
 
 @node Switches for gnatlink,,Running gnatlink,Linking with gnatlink
-@anchor{gnat_ugn/building_executable_programs_with_gnat id47}@anchor{129}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gnatlink}@anchor{12a}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id47}@anchor{12b}@anchor{gnat_ugn/building_executable_programs_with_gnat switches-for-gnatlink}@anchor{12c}
 @subsection Switches for @code{gnatlink}
 
 
@@ -17109,7 +17183,7 @@ switch.
 @end table
 
 @node Using the GNU make Utility,,Linking with gnatlink,Building Executable Programs with GNAT
-@anchor{gnat_ugn/building_executable_programs_with_gnat id48}@anchor{12b}@anchor{gnat_ugn/building_executable_programs_with_gnat using-the-gnu-make-utility}@anchor{70}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id48}@anchor{12d}@anchor{gnat_ugn/building_executable_programs_with_gnat using-the-gnu-make-utility}@anchor{70}
 @section Using the GNU @code{make} Utility
 
 
@@ -17118,7 +17192,7 @@ switch.
 
 This chapter offers some examples of makefiles that solve specific
 problems. It does not explain how to write a makefile, nor does it try to replace the
-@code{gnatmake} utility (@ref{c6,,Building with gnatmake}).
+@code{gnatmake} utility (@ref{c8,,Building with gnatmake}).
 
 All the examples in this section are specific to the GNU version of
 make. Although @code{make} is a standard utility, and the basic language
@@ -17134,7 +17208,7 @@ is the same, these examples use some advanced features found only in
 @end menu
 
 @node Using gnatmake in a Makefile,Automatically Creating a List of Directories,,Using the GNU make Utility
-@anchor{gnat_ugn/building_executable_programs_with_gnat id49}@anchor{12c}@anchor{gnat_ugn/building_executable_programs_with_gnat using-gnatmake-in-a-makefile}@anchor{12d}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id49}@anchor{12e}@anchor{gnat_ugn/building_executable_programs_with_gnat using-gnatmake-in-a-makefile}@anchor{12f}
 @subsection Using gnatmake in a Makefile
 
 
@@ -17153,7 +17227,7 @@ the appropriate directories.
 
 Note that you should also read the example on how to automatically
 create the list of directories
-(@ref{12e,,Automatically Creating a List of Directories})
+(@ref{130,,Automatically Creating a List of Directories})
 which might help you in case your project has a lot of subdirectories.
 
 @example
@@ -17233,7 +17307,7 @@ clean::
 @end example
 
 @node Automatically Creating a List of Directories,Generating the Command Line Switches,Using gnatmake in a Makefile,Using the GNU make Utility
-@anchor{gnat_ugn/building_executable_programs_with_gnat automatically-creating-a-list-of-directories}@anchor{12e}@anchor{gnat_ugn/building_executable_programs_with_gnat id50}@anchor{12f}
+@anchor{gnat_ugn/building_executable_programs_with_gnat automatically-creating-a-list-of-directories}@anchor{130}@anchor{gnat_ugn/building_executable_programs_with_gnat id50}@anchor{131}
 @subsection Automatically Creating a List of Directories
 
 
@@ -17306,12 +17380,12 @@ DIRS := $@{shell find $@{ROOT_DIRECTORY@} -type d -print@}
 @end example
 
 @node Generating the Command Line Switches,Overcoming Command Line Length Limits,Automatically Creating a List of Directories,Using the GNU make Utility
-@anchor{gnat_ugn/building_executable_programs_with_gnat generating-the-command-line-switches}@anchor{130}@anchor{gnat_ugn/building_executable_programs_with_gnat id51}@anchor{131}
+@anchor{gnat_ugn/building_executable_programs_with_gnat generating-the-command-line-switches}@anchor{132}@anchor{gnat_ugn/building_executable_programs_with_gnat id51}@anchor{133}
 @subsection Generating the Command Line Switches
 
 
 Once you have created the list of directories as explained in the
-previous section (@ref{12e,,Automatically Creating a List of Directories}),
+previous section (@ref{130,,Automatically Creating a List of Directories}),
 you can easily generate the command line arguments to pass to gnatmake.
 
 For the sake of completeness, this example assumes that the source path
@@ -17332,7 +17406,7 @@ all:
 @end example
 
 @node Overcoming Command Line Length Limits,,Generating the Command Line Switches,Using the GNU make Utility
-@anchor{gnat_ugn/building_executable_programs_with_gnat id52}@anchor{132}@anchor{gnat_ugn/building_executable_programs_with_gnat overcoming-command-line-length-limits}@anchor{133}
+@anchor{gnat_ugn/building_executable_programs_with_gnat id52}@anchor{134}@anchor{gnat_ugn/building_executable_programs_with_gnat overcoming-command-line-length-limits}@anchor{135}
 @subsection Overcoming Command Line Length Limits
 
 
@@ -17347,7 +17421,7 @@ even none on most systems).
 
 It assumes that you have created a list of directories in your Makefile,
 using one of the methods presented in
-@ref{12e,,Automatically Creating a List of Directories}.
+@ref{130,,Automatically Creating a List of Directories}.
 For the sake of completeness, we assume that the object
 path (where the ALI files are found) is different from the sources patch.
 
@@ -17390,7 +17464,7 @@ all:
 @end example
 
 @node GNAT Utility Programs,GNAT and Program Execution,Building Executable Programs with GNAT,Top
-@anchor{gnat_ugn/gnat_utility_programs doc}@anchor{134}@anchor{gnat_ugn/gnat_utility_programs gnat-utility-programs}@anchor{b}@anchor{gnat_ugn/gnat_utility_programs id1}@anchor{135}
+@anchor{gnat_ugn/gnat_utility_programs doc}@anchor{136}@anchor{gnat_ugn/gnat_utility_programs gnat-utility-programs}@anchor{b}@anchor{gnat_ugn/gnat_utility_programs id1}@anchor{137}
 @chapter GNAT Utility Programs
 
 
@@ -17401,10 +17475,10 @@ This chapter describes a number of utility programs:
 @itemize *
 
 @item 
-@ref{136,,The File Cleanup Utility gnatclean}
+@ref{138,,The File Cleanup Utility gnatclean}
 
 @item 
-@ref{137,,The GNAT Library Browser gnatls}
+@ref{139,,The GNAT Library Browser gnatls}
 @end itemize
 
 Other GNAT utilities are described elsewhere in this manual:
@@ -17432,7 +17506,7 @@ Other GNAT utilities are described elsewhere in this manual:
 @end menu
 
 @node The File Cleanup Utility gnatclean,The GNAT Library Browser gnatls,,GNAT Utility Programs
-@anchor{gnat_ugn/gnat_utility_programs id2}@anchor{138}@anchor{gnat_ugn/gnat_utility_programs the-file-cleanup-utility-gnatclean}@anchor{136}
+@anchor{gnat_ugn/gnat_utility_programs id2}@anchor{13a}@anchor{gnat_ugn/gnat_utility_programs the-file-cleanup-utility-gnatclean}@anchor{138}
 @section The File Cleanup Utility @code{gnatclean}
 
 
@@ -17452,7 +17526,7 @@ generated files and executable files.
 @end menu
 
 @node Running gnatclean,Switches for gnatclean,,The File Cleanup Utility gnatclean
-@anchor{gnat_ugn/gnat_utility_programs id3}@anchor{139}@anchor{gnat_ugn/gnat_utility_programs running-gnatclean}@anchor{13a}
+@anchor{gnat_ugn/gnat_utility_programs id3}@anchor{13b}@anchor{gnat_ugn/gnat_utility_programs running-gnatclean}@anchor{13c}
 @subsection Running @code{gnatclean}
 
 
@@ -17476,7 +17550,7 @@ the linker. In informative-only mode, specified by switch
 normal mode is listed, but no file is actually deleted.
 
 @node Switches for gnatclean,,Running gnatclean,The File Cleanup Utility gnatclean
-@anchor{gnat_ugn/gnat_utility_programs id4}@anchor{13b}@anchor{gnat_ugn/gnat_utility_programs switches-for-gnatclean}@anchor{13c}
+@anchor{gnat_ugn/gnat_utility_programs id4}@anchor{13d}@anchor{gnat_ugn/gnat_utility_programs switches-for-gnatclean}@anchor{13e}
 @subsection Switches for @code{gnatclean}
 
 
@@ -17627,7 +17701,7 @@ Verbose mode.
 @item @code{-vP`x'}
 
 Indicates the verbosity of the parsing of GNAT project files.
-@ref{cf,,Switches Related to Project Files}.
+@ref{d1,,Switches Related to Project Files}.
 @end table
 
 @geindex -X (gnatclean)
@@ -17640,7 +17714,7 @@ Indicates the verbosity of the parsing of GNAT project files.
 Indicates that external variable @code{name} has the value @code{value}.
 The Project Manager will use this value for occurrences of
 @code{external(name)} when parsing the project file.
-See @ref{cf,,Switches Related to Project Files}.
+See @ref{d1,,Switches Related to Project Files}.
 @end table
 
 @geindex -aO (gnatclean)
@@ -17678,7 +17752,7 @@ where @code{gnatclean} was invoked.
 @end table
 
 @node The GNAT Library Browser gnatls,,The File Cleanup Utility gnatclean,GNAT Utility Programs
-@anchor{gnat_ugn/gnat_utility_programs id5}@anchor{13d}@anchor{gnat_ugn/gnat_utility_programs the-gnat-library-browser-gnatls}@anchor{137}
+@anchor{gnat_ugn/gnat_utility_programs id5}@anchor{13f}@anchor{gnat_ugn/gnat_utility_programs the-gnat-library-browser-gnatls}@anchor{139}
 @section The GNAT Library Browser @code{gnatls}
 
 
@@ -17699,7 +17773,7 @@ as well as various characteristics.
 @end menu
 
 @node Running gnatls,Switches for gnatls,,The GNAT Library Browser gnatls
-@anchor{gnat_ugn/gnat_utility_programs id6}@anchor{13e}@anchor{gnat_ugn/gnat_utility_programs running-gnatls}@anchor{13f}
+@anchor{gnat_ugn/gnat_utility_programs id6}@anchor{140}@anchor{gnat_ugn/gnat_utility_programs running-gnatls}@anchor{141}
 @subsection Running @code{gnatls}
 
 
@@ -17779,7 +17853,7 @@ version of the same source that has been modified.
 @end table
 
 @node Switches for gnatls,Example of gnatls Usage,Running gnatls,The GNAT Library Browser gnatls
-@anchor{gnat_ugn/gnat_utility_programs id7}@anchor{140}@anchor{gnat_ugn/gnat_utility_programs switches-for-gnatls}@anchor{141}
+@anchor{gnat_ugn/gnat_utility_programs id7}@anchor{142}@anchor{gnat_ugn/gnat_utility_programs switches-for-gnatls}@anchor{143}
 @subsection Switches for @code{gnatls}
 
 
@@ -17894,7 +17968,7 @@ Several such switches may be specified simultaneously.
 @item @code{-aO`dir'}, @code{-aI`dir'}, @code{-I`dir'}, @code{-I-}, @code{-nostdinc}
 
 Source path manipulation. Same meaning as the equivalent @code{gnatmake}
-flags (@ref{ce,,Switches for gnatmake}).
+flags (@ref{d0,,Switches for gnatmake}).
 @end table
 
 @geindex -aP (gnatls)
@@ -17915,7 +17989,7 @@ Add @code{dir} at the beginning of the project search dir.
 @item @code{--RTS=`rts-path'}
 
 Specifies the default location of the runtime library. Same meaning as the
-equivalent @code{gnatmake} flag (@ref{ce,,Switches for gnatmake}).
+equivalent @code{gnatmake} flag (@ref{d0,,Switches for gnatmake}).
 @end table
 
 @geindex -v (gnatls)
@@ -17961,7 +18035,7 @@ by the user.
 @end table
 
 @node Example of gnatls Usage,,Switches for gnatls,The GNAT Library Browser gnatls
-@anchor{gnat_ugn/gnat_utility_programs example-of-gnatls-usage}@anchor{142}@anchor{gnat_ugn/gnat_utility_programs id8}@anchor{143}
+@anchor{gnat_ugn/gnat_utility_programs example-of-gnatls-usage}@anchor{144}@anchor{gnat_ugn/gnat_utility_programs id8}@anchor{145}
 @subsection Example of @code{gnatls} Usage
 
 
@@ -18047,7 +18121,7 @@ instr.ads
 @c -- Example: A |withing| unit has a |with| clause, it |withs| a |withed| unit
 
 @node GNAT and Program Execution,Platform-Specific Information,GNAT Utility Programs,Top
-@anchor{gnat_ugn/gnat_and_program_execution doc}@anchor{144}@anchor{gnat_ugn/gnat_and_program_execution gnat-and-program-execution}@anchor{c}@anchor{gnat_ugn/gnat_and_program_execution id1}@anchor{145}
+@anchor{gnat_ugn/gnat_and_program_execution doc}@anchor{146}@anchor{gnat_ugn/gnat_and_program_execution gnat-and-program-execution}@anchor{c}@anchor{gnat_ugn/gnat_and_program_execution id1}@anchor{147}
 @chapter GNAT and Program Execution
 
 
@@ -18057,25 +18131,25 @@ This chapter covers several topics:
 @itemize *
 
 @item 
-@ref{146,,Running and Debugging Ada Programs}
+@ref{148,,Running and Debugging Ada Programs}
 
 @item 
-@ref{147,,Profiling}
+@ref{149,,Profiling}
 
 @item 
-@ref{148,,Improving Performance}
+@ref{14a,,Improving Performance}
 
 @item 
-@ref{149,,Overflow Check Handling in GNAT}
+@ref{14b,,Overflow Check Handling in GNAT}
 
 @item 
-@ref{14a,,Performing Dimensionality Analysis in GNAT}
+@ref{14c,,Performing Dimensionality Analysis in GNAT}
 
 @item 
-@ref{14b,,Stack Related Facilities}
+@ref{14d,,Stack Related Facilities}
 
 @item 
-@ref{14c,,Memory Management Issues}
+@ref{14e,,Memory Management Issues}
 @end itemize
 
 @menu
@@ -18090,7 +18164,7 @@ This chapter covers several topics:
 @end menu
 
 @node Running and Debugging Ada Programs,Profiling,,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id2}@anchor{146}@anchor{gnat_ugn/gnat_and_program_execution running-and-debugging-ada-programs}@anchor{14d}
+@anchor{gnat_ugn/gnat_and_program_execution id2}@anchor{148}@anchor{gnat_ugn/gnat_and_program_execution running-and-debugging-ada-programs}@anchor{14f}
 @section Running and Debugging Ada Programs
 
 
@@ -18144,7 +18218,7 @@ the incorrect user program.
 @end menu
 
 @node The GNAT Debugger GDB,Running GDB,,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id3}@anchor{14e}@anchor{gnat_ugn/gnat_and_program_execution the-gnat-debugger-gdb}@anchor{14f}
+@anchor{gnat_ugn/gnat_and_program_execution id3}@anchor{150}@anchor{gnat_ugn/gnat_and_program_execution the-gnat-debugger-gdb}@anchor{151}
 @subsection The GNAT Debugger GDB
 
 
@@ -18201,7 +18275,7 @@ the debugging information and can respond to user commands to inspect
 variables, and more generally to report on the state of execution.
 
 @node Running GDB,Introduction to GDB Commands,The GNAT Debugger GDB,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id4}@anchor{150}@anchor{gnat_ugn/gnat_and_program_execution running-gdb}@anchor{151}
+@anchor{gnat_ugn/gnat_and_program_execution id4}@anchor{152}@anchor{gnat_ugn/gnat_and_program_execution running-gdb}@anchor{153}
 @subsection Running GDB
 
 
@@ -18228,7 +18302,7 @@ exactly as if the debugger were not present. The following section
 describes some of the additional commands that can be given to @code{GDB}.
 
 @node Introduction to GDB Commands,Using Ada Expressions,Running GDB,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id5}@anchor{152}@anchor{gnat_ugn/gnat_and_program_execution introduction-to-gdb-commands}@anchor{153}
+@anchor{gnat_ugn/gnat_and_program_execution id5}@anchor{154}@anchor{gnat_ugn/gnat_and_program_execution introduction-to-gdb-commands}@anchor{155}
 @subsection Introduction to GDB Commands
 
 
@@ -18436,7 +18510,7 @@ Note that most commands can be abbreviated
 (for example, c for continue, bt for backtrace).
 
 @node Using Ada Expressions,Calling User-Defined Subprograms,Introduction to GDB Commands,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id6}@anchor{154}@anchor{gnat_ugn/gnat_and_program_execution using-ada-expressions}@anchor{155}
+@anchor{gnat_ugn/gnat_and_program_execution id6}@anchor{156}@anchor{gnat_ugn/gnat_and_program_execution using-ada-expressions}@anchor{157}
 @subsection Using Ada Expressions
 
 
@@ -18474,7 +18548,7 @@ their packages, regardless of context. Where this causes ambiguity,
 For details on the supported Ada syntax, see @cite{Debugging with GDB}.
 
 @node Calling User-Defined Subprograms,Using the next Command in a Function,Using Ada Expressions,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution calling-user-defined-subprograms}@anchor{156}@anchor{gnat_ugn/gnat_and_program_execution id7}@anchor{157}
+@anchor{gnat_ugn/gnat_and_program_execution calling-user-defined-subprograms}@anchor{158}@anchor{gnat_ugn/gnat_and_program_execution id7}@anchor{159}
 @subsection Calling User-Defined Subprograms
 
 
@@ -18533,7 +18607,7 @@ elements directly from GDB, you can write a callable procedure that prints
 the elements in the desired format.
 
 @node Using the next Command in a Function,Stopping When Ada Exceptions Are Raised,Calling User-Defined Subprograms,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id8}@anchor{158}@anchor{gnat_ugn/gnat_and_program_execution using-the-next-command-in-a-function}@anchor{159}
+@anchor{gnat_ugn/gnat_and_program_execution id8}@anchor{15a}@anchor{gnat_ugn/gnat_and_program_execution using-the-next-command-in-a-function}@anchor{15b}
 @subsection Using the `next' Command in a Function
 
 
@@ -18556,7 +18630,7 @@ The value returned is always that from the first return statement
 that was stepped through.
 
 @node Stopping When Ada Exceptions Are Raised,Ada Tasks,Using the next Command in a Function,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id9}@anchor{15a}@anchor{gnat_ugn/gnat_and_program_execution stopping-when-ada-exceptions-are-raised}@anchor{15b}
+@anchor{gnat_ugn/gnat_and_program_execution id9}@anchor{15c}@anchor{gnat_ugn/gnat_and_program_execution stopping-when-ada-exceptions-are-raised}@anchor{15d}
 @subsection Stopping When Ada Exceptions Are Raised
 
 
@@ -18613,7 +18687,7 @@ argument, prints out only those exceptions whose name matches `regexp'.
 @geindex Tasks (in gdb)
 
 @node Ada Tasks,Debugging Generic Units,Stopping When Ada Exceptions Are Raised,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution ada-tasks}@anchor{15c}@anchor{gnat_ugn/gnat_and_program_execution id10}@anchor{15d}
+@anchor{gnat_ugn/gnat_and_program_execution ada-tasks}@anchor{15e}@anchor{gnat_ugn/gnat_and_program_execution id10}@anchor{15f}
 @subsection Ada Tasks
 
 
@@ -18700,7 +18774,7 @@ see @cite{Debugging with GDB}.
 @geindex Generics
 
 @node Debugging Generic Units,Remote Debugging with gdbserver,Ada Tasks,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution debugging-generic-units}@anchor{15e}@anchor{gnat_ugn/gnat_and_program_execution id11}@anchor{15f}
+@anchor{gnat_ugn/gnat_and_program_execution debugging-generic-units}@anchor{160}@anchor{gnat_ugn/gnat_and_program_execution id11}@anchor{161}
 @subsection Debugging Generic Units
 
 
@@ -18759,7 +18833,7 @@ other units.
 @geindex Remote Debugging with gdbserver
 
 @node Remote Debugging with gdbserver,GNAT Abnormal Termination or Failure to Terminate,Debugging Generic Units,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id12}@anchor{160}@anchor{gnat_ugn/gnat_and_program_execution remote-debugging-with-gdbserver}@anchor{161}
+@anchor{gnat_ugn/gnat_and_program_execution id12}@anchor{162}@anchor{gnat_ugn/gnat_and_program_execution remote-debugging-with-gdbserver}@anchor{163}
 @subsection Remote Debugging with gdbserver
 
 
@@ -18817,7 +18891,7 @@ GNAT provides support for gdbserver on x86-linux, x86-windows and x86_64-linux.
 @geindex Abnormal Termination or Failure to Terminate
 
 @node GNAT Abnormal Termination or Failure to Terminate,Naming Conventions for GNAT Source Files,Remote Debugging with gdbserver,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution gnat-abnormal-termination-or-failure-to-terminate}@anchor{162}@anchor{gnat_ugn/gnat_and_program_execution id13}@anchor{163}
+@anchor{gnat_ugn/gnat_and_program_execution gnat-abnormal-termination-or-failure-to-terminate}@anchor{164}@anchor{gnat_ugn/gnat_and_program_execution id13}@anchor{165}
 @subsection GNAT Abnormal Termination or Failure to Terminate
 
 
@@ -18872,7 +18946,7 @@ Finally, you can start
 @code{gdb} directly on the @code{gnat1} executable. @code{gnat1} is the
 front-end of GNAT, and can be run independently (normally it is just
 called from @code{gcc}). You can use @code{gdb} on @code{gnat1} as you
-would on a C program (but @ref{14f,,The GNAT Debugger GDB} for caveats). The
+would on a C program (but @ref{151,,The GNAT Debugger GDB} for caveats). The
 @code{where} command is the first line of attack; the variable
 @code{lineno} (seen by @code{print lineno}), used by the second phase of
 @code{gnat1} and by the @code{gcc} backend, indicates the source line at
@@ -18881,7 +18955,7 @@ the source file.
 @end itemize
 
 @node Naming Conventions for GNAT Source Files,Getting Internal Debugging Information,GNAT Abnormal Termination or Failure to Terminate,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id14}@anchor{164}@anchor{gnat_ugn/gnat_and_program_execution naming-conventions-for-gnat-source-files}@anchor{165}
+@anchor{gnat_ugn/gnat_and_program_execution id14}@anchor{166}@anchor{gnat_ugn/gnat_and_program_execution naming-conventions-for-gnat-source-files}@anchor{167}
 @subsection Naming Conventions for GNAT Source Files
 
 
@@ -18962,7 +19036,7 @@ the other @code{.c} files are modifications of common @code{gcc} files.
 @end itemize
 
 @node Getting Internal Debugging Information,Stack Traceback,Naming Conventions for GNAT Source Files,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution getting-internal-debugging-information}@anchor{166}@anchor{gnat_ugn/gnat_and_program_execution id15}@anchor{167}
+@anchor{gnat_ugn/gnat_and_program_execution getting-internal-debugging-information}@anchor{168}@anchor{gnat_ugn/gnat_and_program_execution id15}@anchor{169}
 @subsection Getting Internal Debugging Information
 
 
@@ -18990,7 +19064,7 @@ are replaced with run-time calls.
 @geindex stack unwinding
 
 @node Stack Traceback,Pretty-Printers for the GNAT runtime,Getting Internal Debugging Information,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id16}@anchor{168}@anchor{gnat_ugn/gnat_and_program_execution stack-traceback}@anchor{169}
+@anchor{gnat_ugn/gnat_and_program_execution id16}@anchor{16a}@anchor{gnat_ugn/gnat_and_program_execution stack-traceback}@anchor{16b}
 @subsection Stack Traceback
 
 
@@ -19019,7 +19093,7 @@ is enabled, and no exception is raised during program execution.
 @end menu
 
 @node Non-Symbolic Traceback,Symbolic Traceback,,Stack Traceback
-@anchor{gnat_ugn/gnat_and_program_execution id17}@anchor{16a}@anchor{gnat_ugn/gnat_and_program_execution non-symbolic-traceback}@anchor{16b}
+@anchor{gnat_ugn/gnat_and_program_execution id17}@anchor{16c}@anchor{gnat_ugn/gnat_and_program_execution non-symbolic-traceback}@anchor{16d}
 @subsubsection Non-Symbolic Traceback
 
 
@@ -19035,7 +19109,7 @@ To enable this feature you must use the @code{-E} @code{gnatbind} option. With
 this option a stack traceback is stored as part of exception information.
 
 You can translate this information using the @code{addr2line} tool, provided that
-the program is compiled with debugging options (see @ref{db,,Compiler Switches})
+the program is compiled with debugging options (see @ref{dd,,Compiler Switches})
 and linked at a fixed position with @code{-no-pie}.
 
 Here is a simple example with @code{gnatmake}:
@@ -19152,7 +19226,7 @@ $ addr2line -e stb -a -f -p --demangle=gnat 0x401373 0x40138b
 From this traceback we can see that the exception was raised in @code{stb.adb}
 at line 5, which was reached from a procedure call in @code{stb.adb} at line
 10, and so on. The @code{b~std.adb} is the binder file, which contains the
-call to the main program. @ref{10e,,Running gnatbind}. The remaining entries are
+call to the main program. @ref{110,,Running gnatbind}. The remaining entries are
 assorted runtime routines and the output will vary from platform to platform.
 
 It is also possible to use @code{GDB} with these traceback addresses to debug
@@ -19340,7 +19414,7 @@ addresses need to be specified in C format, with a leading ‘0x’).
 @geindex symbolic
 
 @node Symbolic Traceback,,Non-Symbolic Traceback,Stack Traceback
-@anchor{gnat_ugn/gnat_and_program_execution id18}@anchor{16c}@anchor{gnat_ugn/gnat_and_program_execution symbolic-traceback}@anchor{16d}
+@anchor{gnat_ugn/gnat_and_program_execution id18}@anchor{16e}@anchor{gnat_ugn/gnat_and_program_execution symbolic-traceback}@anchor{16f}
 @subsubsection Symbolic Traceback
 
 
@@ -19459,7 +19533,7 @@ which will also be printed if an unhandled exception terminates the
 program.
 
 @node Pretty-Printers for the GNAT runtime,,Stack Traceback,Running and Debugging Ada Programs
-@anchor{gnat_ugn/gnat_and_program_execution id19}@anchor{16e}@anchor{gnat_ugn/gnat_and_program_execution pretty-printers-for-the-gnat-runtime}@anchor{16f}
+@anchor{gnat_ugn/gnat_and_program_execution id19}@anchor{170}@anchor{gnat_ugn/gnat_and_program_execution pretty-printers-for-the-gnat-runtime}@anchor{171}
 @subsection Pretty-Printers for the GNAT runtime
 
 
@@ -19566,7 +19640,7 @@ for more information.
 @geindex Profiling
 
 @node Profiling,Improving Performance,Running and Debugging Ada Programs,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id20}@anchor{170}@anchor{gnat_ugn/gnat_and_program_execution profiling}@anchor{147}
+@anchor{gnat_ugn/gnat_and_program_execution id20}@anchor{172}@anchor{gnat_ugn/gnat_and_program_execution profiling}@anchor{149}
 @section Profiling
 
 
@@ -19582,7 +19656,7 @@ This section describes how to use the @code{gprof} profiler tool on Ada programs
 @end menu
 
 @node Profiling an Ada Program with gprof,,,Profiling
-@anchor{gnat_ugn/gnat_and_program_execution id21}@anchor{171}@anchor{gnat_ugn/gnat_and_program_execution profiling-an-ada-program-with-gprof}@anchor{172}
+@anchor{gnat_ugn/gnat_and_program_execution id21}@anchor{173}@anchor{gnat_ugn/gnat_and_program_execution profiling-an-ada-program-with-gprof}@anchor{174}
 @subsection Profiling an Ada Program with gprof
 
 
@@ -19636,7 +19710,7 @@ to interpret the results.
 @end menu
 
 @node Compilation for profiling,Program execution,,Profiling an Ada Program with gprof
-@anchor{gnat_ugn/gnat_and_program_execution compilation-for-profiling}@anchor{173}@anchor{gnat_ugn/gnat_and_program_execution id22}@anchor{174}
+@anchor{gnat_ugn/gnat_and_program_execution compilation-for-profiling}@anchor{175}@anchor{gnat_ugn/gnat_and_program_execution id22}@anchor{176}
 @subsubsection Compilation for profiling
 
 
@@ -19667,7 +19741,7 @@ Note that on Windows, gprof does not support PIE. The @code{-no-pie} switch
 should be added to the linker flags to disable this feature.
 
 @node Program execution,Running gprof,Compilation for profiling,Profiling an Ada Program with gprof
-@anchor{gnat_ugn/gnat_and_program_execution id23}@anchor{175}@anchor{gnat_ugn/gnat_and_program_execution program-execution}@anchor{176}
+@anchor{gnat_ugn/gnat_and_program_execution id23}@anchor{177}@anchor{gnat_ugn/gnat_and_program_execution program-execution}@anchor{178}
 @subsubsection Program execution
 
 
@@ -19682,7 +19756,7 @@ generated in the directory where the program was launched from. If this file
 already exists, it will be overwritten.
 
 @node Running gprof,Interpretation of profiling results,Program execution,Profiling an Ada Program with gprof
-@anchor{gnat_ugn/gnat_and_program_execution id24}@anchor{177}@anchor{gnat_ugn/gnat_and_program_execution running-gprof}@anchor{178}
+@anchor{gnat_ugn/gnat_and_program_execution id24}@anchor{179}@anchor{gnat_ugn/gnat_and_program_execution running-gprof}@anchor{17a}
 @subsubsection Running gprof
 
 
@@ -19795,7 +19869,7 @@ may be given; only one @code{function_name} may be indicated with each
 @end table
 
 @node Interpretation of profiling results,,Running gprof,Profiling an Ada Program with gprof
-@anchor{gnat_ugn/gnat_and_program_execution id25}@anchor{179}@anchor{gnat_ugn/gnat_and_program_execution interpretation-of-profiling-results}@anchor{17a}
+@anchor{gnat_ugn/gnat_and_program_execution id25}@anchor{17b}@anchor{gnat_ugn/gnat_and_program_execution interpretation-of-profiling-results}@anchor{17c}
 @subsubsection Interpretation of profiling results
 
 
@@ -19812,7 +19886,7 @@ and the subprograms that it calls. It also provides an estimate of the time
 spent in each of those callers/called subprograms.
 
 @node Improving Performance,Overflow Check Handling in GNAT,Profiling,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id26}@anchor{148}@anchor{gnat_ugn/gnat_and_program_execution improving-performance}@anchor{17b}
+@anchor{gnat_ugn/gnat_and_program_execution id26}@anchor{14a}@anchor{gnat_ugn/gnat_and_program_execution improving-performance}@anchor{17d}
 @section Improving Performance
 
 
@@ -19833,7 +19907,7 @@ which can reduce the size of program executables.
 @end menu
 
 @node Performance Considerations,Text_IO Suggestions,,Improving Performance
-@anchor{gnat_ugn/gnat_and_program_execution id27}@anchor{17c}@anchor{gnat_ugn/gnat_and_program_execution performance-considerations}@anchor{17d}
+@anchor{gnat_ugn/gnat_and_program_execution id27}@anchor{17e}@anchor{gnat_ugn/gnat_and_program_execution performance-considerations}@anchor{17f}
 @subsection Performance Considerations
 
 
@@ -19894,7 +19968,7 @@ some guidelines on debugging optimized code.
 @end menu
 
 @node Controlling Run-Time Checks,Use of Restrictions,,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution controlling-run-time-checks}@anchor{17e}@anchor{gnat_ugn/gnat_and_program_execution id28}@anchor{17f}
+@anchor{gnat_ugn/gnat_and_program_execution controlling-run-time-checks}@anchor{180}@anchor{gnat_ugn/gnat_and_program_execution id28}@anchor{181}
 @subsubsection Controlling Run-Time Checks
 
 
@@ -19908,7 +19982,7 @@ necessary checking is done at compile time.
 @geindex -gnato (gcc)
 
 The gnat switch, @code{-gnatp} allows this default to be modified. See
-@ref{ea,,Run-Time Checks}.
+@ref{ec,,Run-Time Checks}.
 
 Our experience is that the default is suitable for most development
 purposes.
@@ -19946,7 +20020,7 @@ remove checks) or @code{pragma Unsuppress} (to add back suppressed
 checks) in the program source.
 
 @node Use of Restrictions,Optimization Levels,Controlling Run-Time Checks,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id29}@anchor{180}@anchor{gnat_ugn/gnat_and_program_execution use-of-restrictions}@anchor{181}
+@anchor{gnat_ugn/gnat_and_program_execution id29}@anchor{182}@anchor{gnat_ugn/gnat_and_program_execution use-of-restrictions}@anchor{183}
 @subsubsection Use of Restrictions
 
 
@@ -19981,7 +20055,7 @@ that this also means that you can write code without worrying about the
 possibility of an immediate abort at any point.
 
 @node Optimization Levels,Debugging Optimized Code,Use of Restrictions,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id30}@anchor{182}@anchor{gnat_ugn/gnat_and_program_execution optimization-levels}@anchor{ed}
+@anchor{gnat_ugn/gnat_and_program_execution id30}@anchor{184}@anchor{gnat_ugn/gnat_and_program_execution optimization-levels}@anchor{ef}
 @subsubsection Optimization Levels
 
 
@@ -20062,7 +20136,7 @@ the slowest compilation time.
 
 Full optimization as in @code{-O2};
 also uses more aggressive automatic inlining of subprograms within a unit
-(@ref{100,,Inlining of Subprograms}) and attempts to vectorize loops.
+(@ref{102,,Inlining of Subprograms}) and attempts to vectorize loops.
 @end table
 
 @item 
@@ -20102,10 +20176,10 @@ levels.
 Note regarding the use of @code{-O3}: The use of this optimization level
 ought not to be automatically preferred over that of level @code{-O2},
 since it often results in larger executables which may run more slowly.
-See further discussion of this point in @ref{100,,Inlining of Subprograms}.
+See further discussion of this point in @ref{102,,Inlining of Subprograms}.
 
 @node Debugging Optimized Code,Inlining of Subprograms,Optimization Levels,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution debugging-optimized-code}@anchor{183}@anchor{gnat_ugn/gnat_and_program_execution id31}@anchor{184}
+@anchor{gnat_ugn/gnat_and_program_execution debugging-optimized-code}@anchor{185}@anchor{gnat_ugn/gnat_and_program_execution id31}@anchor{186}
 @subsubsection Debugging Optimized Code
 
 
@@ -20233,7 +20307,7 @@ on the resulting executable,
 which removes both debugging information and global symbols.
 
 @node Inlining of Subprograms,Floating Point Operations,Debugging Optimized Code,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id32}@anchor{185}@anchor{gnat_ugn/gnat_and_program_execution inlining-of-subprograms}@anchor{100}
+@anchor{gnat_ugn/gnat_and_program_execution id32}@anchor{187}@anchor{gnat_ugn/gnat_and_program_execution inlining-of-subprograms}@anchor{102}
 @subsubsection Inlining of Subprograms
 
 
@@ -20372,7 +20446,7 @@ indeed you should use @code{-O3} only if tests show that it actually
 improves performance for your program.
 
 @node Floating Point Operations,Vectorization of loops,Inlining of Subprograms,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution floating-point-operations}@anchor{186}@anchor{gnat_ugn/gnat_and_program_execution id33}@anchor{187}
+@anchor{gnat_ugn/gnat_and_program_execution floating-point-operations}@anchor{188}@anchor{gnat_ugn/gnat_and_program_execution id33}@anchor{189}
 @subsubsection Floating Point Operations
 
 
@@ -20420,7 +20494,7 @@ so it is permissible to mix units compiled with and without these
 switches.
 
 @node Vectorization of loops,Other Optimization Switches,Floating Point Operations,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id34}@anchor{188}@anchor{gnat_ugn/gnat_and_program_execution vectorization-of-loops}@anchor{189}
+@anchor{gnat_ugn/gnat_and_program_execution id34}@anchor{18a}@anchor{gnat_ugn/gnat_and_program_execution vectorization-of-loops}@anchor{18b}
 @subsubsection Vectorization of loops
 
 
@@ -20571,7 +20645,7 @@ placed immediately within the loop will tell the compiler that it can safely
 omit the non-vectorized version of the loop as well as the run-time test.
 
 @node Other Optimization Switches,Optimization and Strict Aliasing,Vectorization of loops,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id35}@anchor{18a}@anchor{gnat_ugn/gnat_and_program_execution other-optimization-switches}@anchor{18b}
+@anchor{gnat_ugn/gnat_and_program_execution id35}@anchor{18c}@anchor{gnat_ugn/gnat_and_program_execution other-optimization-switches}@anchor{18d}
 @subsubsection Other Optimization Switches
 
 
@@ -20588,7 +20662,7 @@ the `Submodel Options' section in the `Hardware Models and Configurations'
 chapter of @cite{Using the GNU Compiler Collection (GCC)}.
 
 @node Optimization and Strict Aliasing,Aliased Variables and Optimization,Other Optimization Switches,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id36}@anchor{18c}@anchor{gnat_ugn/gnat_and_program_execution optimization-and-strict-aliasing}@anchor{e4}
+@anchor{gnat_ugn/gnat_and_program_execution id36}@anchor{18e}@anchor{gnat_ugn/gnat_and_program_execution optimization-and-strict-aliasing}@anchor{e6}
 @subsubsection Optimization and Strict Aliasing
 
 
@@ -20828,7 +20902,7 @@ review any uses of unchecked conversion of access types,
 particularly if you are getting the warnings described above.
 
 @node Aliased Variables and Optimization,Atomic Variables and Optimization,Optimization and Strict Aliasing,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution aliased-variables-and-optimization}@anchor{18d}@anchor{gnat_ugn/gnat_and_program_execution id37}@anchor{18e}
+@anchor{gnat_ugn/gnat_and_program_execution aliased-variables-and-optimization}@anchor{18f}@anchor{gnat_ugn/gnat_and_program_execution id37}@anchor{190}
 @subsubsection Aliased Variables and Optimization
 
 
@@ -20886,7 +20960,7 @@ This means that the above example will in fact “work” reliably,
 that is, it will produce the expected results.
 
 @node Atomic Variables and Optimization,Passive Task Optimization,Aliased Variables and Optimization,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution atomic-variables-and-optimization}@anchor{18f}@anchor{gnat_ugn/gnat_and_program_execution id38}@anchor{190}
+@anchor{gnat_ugn/gnat_and_program_execution atomic-variables-and-optimization}@anchor{191}@anchor{gnat_ugn/gnat_and_program_execution id38}@anchor{192}
 @subsubsection Atomic Variables and Optimization
 
 
@@ -20967,7 +21041,7 @@ such synchronization code is not required, it may be
 useful to disable it.
 
 @node Passive Task Optimization,,Atomic Variables and Optimization,Performance Considerations
-@anchor{gnat_ugn/gnat_and_program_execution id39}@anchor{191}@anchor{gnat_ugn/gnat_and_program_execution passive-task-optimization}@anchor{192}
+@anchor{gnat_ugn/gnat_and_program_execution id39}@anchor{193}@anchor{gnat_ugn/gnat_and_program_execution passive-task-optimization}@anchor{194}
 @subsubsection Passive Task Optimization
 
 
@@ -21012,7 +21086,7 @@ that typically clients of the tasks who call entries, will not have
 to be modified, only the task definition itself.
 
 @node Text_IO Suggestions,Reducing Size of Executables with Unused Subprogram/Data Elimination,Performance Considerations,Improving Performance
-@anchor{gnat_ugn/gnat_and_program_execution id40}@anchor{193}@anchor{gnat_ugn/gnat_and_program_execution text-io-suggestions}@anchor{194}
+@anchor{gnat_ugn/gnat_and_program_execution id40}@anchor{195}@anchor{gnat_ugn/gnat_and_program_execution text-io-suggestions}@anchor{196}
 @subsection @code{Text_IO} Suggestions
 
 
@@ -21035,7 +21109,7 @@ of the standard output file, or change the standard output file to
 be buffered using @code{Interfaces.C_Streams.setvbuf}.
 
 @node Reducing Size of Executables with Unused Subprogram/Data Elimination,,Text_IO Suggestions,Improving Performance
-@anchor{gnat_ugn/gnat_and_program_execution id41}@anchor{195}@anchor{gnat_ugn/gnat_and_program_execution reducing-size-of-executables-with-unused-subprogram-data-elimination}@anchor{196}
+@anchor{gnat_ugn/gnat_and_program_execution id41}@anchor{197}@anchor{gnat_ugn/gnat_and_program_execution reducing-size-of-executables-with-unused-subprogram-data-elimination}@anchor{198}
 @subsection Reducing Size of Executables with Unused Subprogram/Data Elimination
 
 
@@ -21052,7 +21126,7 @@ your executable just by setting options at compilation time.
 @end menu
 
 @node About unused subprogram/data elimination,Compilation options,,Reducing Size of Executables with Unused Subprogram/Data Elimination
-@anchor{gnat_ugn/gnat_and_program_execution about-unused-subprogram-data-elimination}@anchor{197}@anchor{gnat_ugn/gnat_and_program_execution id42}@anchor{198}
+@anchor{gnat_ugn/gnat_and_program_execution about-unused-subprogram-data-elimination}@anchor{199}@anchor{gnat_ugn/gnat_and_program_execution id42}@anchor{19a}
 @subsubsection About unused subprogram/data elimination
 
 
@@ -21068,7 +21142,7 @@ architecture and on all cross platforms using the ELF binary file format.
 In both cases GNU binutils version 2.16 or later are required to enable it.
 
 @node Compilation options,Example of unused subprogram/data elimination,About unused subprogram/data elimination,Reducing Size of Executables with Unused Subprogram/Data Elimination
-@anchor{gnat_ugn/gnat_and_program_execution compilation-options}@anchor{199}@anchor{gnat_ugn/gnat_and_program_execution id43}@anchor{19a}
+@anchor{gnat_ugn/gnat_and_program_execution compilation-options}@anchor{19b}@anchor{gnat_ugn/gnat_and_program_execution id43}@anchor{19c}
 @subsubsection Compilation options
 
 
@@ -21107,7 +21181,7 @@ The GNAT static library is now compiled with -ffunction-sections and
 and data of the GNAT library from your executable.
 
 @node Example of unused subprogram/data elimination,,Compilation options,Reducing Size of Executables with Unused Subprogram/Data Elimination
-@anchor{gnat_ugn/gnat_and_program_execution example-of-unused-subprogram-data-elimination}@anchor{19b}@anchor{gnat_ugn/gnat_and_program_execution id44}@anchor{19c}
+@anchor{gnat_ugn/gnat_and_program_execution example-of-unused-subprogram-data-elimination}@anchor{19d}@anchor{gnat_ugn/gnat_and_program_execution id44}@anchor{19e}
 @subsubsection Example of unused subprogram/data elimination
 
 
@@ -21177,7 +21251,7 @@ appropriate options.
 @geindex Checks (overflow)
 
 @node Overflow Check Handling in GNAT,Performing Dimensionality Analysis in GNAT,Improving Performance,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id45}@anchor{149}@anchor{gnat_ugn/gnat_and_program_execution overflow-check-handling-in-gnat}@anchor{19d}
+@anchor{gnat_ugn/gnat_and_program_execution id45}@anchor{14b}@anchor{gnat_ugn/gnat_and_program_execution overflow-check-handling-in-gnat}@anchor{19f}
 @section Overflow Check Handling in GNAT
 
 
@@ -21193,7 +21267,7 @@ This section explains how to control the handling of overflow checks.
 @end menu
 
 @node Background,Management of Overflows in GNAT,,Overflow Check Handling in GNAT
-@anchor{gnat_ugn/gnat_and_program_execution background}@anchor{19e}@anchor{gnat_ugn/gnat_and_program_execution id46}@anchor{19f}
+@anchor{gnat_ugn/gnat_and_program_execution background}@anchor{1a0}@anchor{gnat_ugn/gnat_and_program_execution id46}@anchor{1a1}
 @subsection Background
 
 
@@ -21319,7 +21393,7 @@ exception raised because of the intermediate overflow (and we really
 would prefer this precondition to be considered True at run time).
 
 @node Management of Overflows in GNAT,Specifying the Desired Mode,Background,Overflow Check Handling in GNAT
-@anchor{gnat_ugn/gnat_and_program_execution id47}@anchor{1a0}@anchor{gnat_ugn/gnat_and_program_execution management-of-overflows-in-gnat}@anchor{1a1}
+@anchor{gnat_ugn/gnat_and_program_execution id47}@anchor{1a2}@anchor{gnat_ugn/gnat_and_program_execution management-of-overflows-in-gnat}@anchor{1a3}
 @subsection Management of Overflows in GNAT
 
 
@@ -21433,7 +21507,7 @@ out in the normal manner (with infinite values always failing all
 range checks).
 
 @node Specifying the Desired Mode,Default Settings,Management of Overflows in GNAT,Overflow Check Handling in GNAT
-@anchor{gnat_ugn/gnat_and_program_execution id48}@anchor{1a2}@anchor{gnat_ugn/gnat_and_program_execution specifying-the-desired-mode}@anchor{e9}
+@anchor{gnat_ugn/gnat_and_program_execution id48}@anchor{1a4}@anchor{gnat_ugn/gnat_and_program_execution specifying-the-desired-mode}@anchor{eb}
 @subsection Specifying the Desired Mode
 
 
@@ -21557,7 +21631,7 @@ causing all intermediate operations to be computed using the base
 type (@code{STRICT} mode).
 
 @node Default Settings,Implementation Notes,Specifying the Desired Mode,Overflow Check Handling in GNAT
-@anchor{gnat_ugn/gnat_and_program_execution default-settings}@anchor{1a3}@anchor{gnat_ugn/gnat_and_program_execution id49}@anchor{1a4}
+@anchor{gnat_ugn/gnat_and_program_execution default-settings}@anchor{1a5}@anchor{gnat_ugn/gnat_and_program_execution id49}@anchor{1a6}
 @subsection Default Settings
 
 
@@ -21570,30 +21644,8 @@ General => Strict
 @end example
 @end quotation
 
-which causes all computations both inside and outside assertions to use
-the base type.
-
-This retains compatibility with previous versions of
-GNAT which suppressed overflow checks by default and always
-used the base type for computation of intermediate results.
-
-@c Sphinx allows no emphasis within :index: role. As a workaround we
-@c point the index to "switch" and use emphasis for "-gnato".
-
-The 
-@geindex -gnato (gcc)
-switch @code{-gnato} (with no digits following)
-is equivalent to
-
-@quotation
-
-@example
-General => Strict
-@end example
-@end quotation
-
-which causes overflow checking of all intermediate overflows
-both inside and outside assertions against the base type.
+which causes all computations both inside and outside assertions to use the
+base type, and is equivalent to @code{-gnato} (with no digits following).
 
 The pragma @code{Suppress (Overflow_Check)} disables overflow
 checking, but it has no effect on the method used for computing
@@ -21604,7 +21656,7 @@ checking, but it has no effect on the method used for computing
 intermediate results.
 
 @node Implementation Notes,,Default Settings,Overflow Check Handling in GNAT
-@anchor{gnat_ugn/gnat_and_program_execution id50}@anchor{1a5}@anchor{gnat_ugn/gnat_and_program_execution implementation-notes}@anchor{1a6}
+@anchor{gnat_ugn/gnat_and_program_execution id50}@anchor{1a7}@anchor{gnat_ugn/gnat_and_program_execution implementation-notes}@anchor{1a8}
 @subsection Implementation Notes
 
 
@@ -21613,7 +21665,7 @@ reasonably efficient, and can be generally used. It also helps
 to ensure compatibility with code imported from some other
 compiler to GNAT.
 
-Setting all intermediate overflows checking (@code{CHECKED} mode)
+Setting all intermediate overflows checking (@code{STRICT} mode)
 makes sense if you want to
 make sure that your code is compatible with any other possible
 Ada implementation. This may be useful in ensuring portability
@@ -21652,7 +21704,7 @@ platforms for which @code{Long_Long_Integer} is 64-bits (nearly all GNAT
 platforms).
 
 @node Performing Dimensionality Analysis in GNAT,Stack Related Facilities,Overflow Check Handling in GNAT,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id51}@anchor{14a}@anchor{gnat_ugn/gnat_and_program_execution performing-dimensionality-analysis-in-gnat}@anchor{1a7}
+@anchor{gnat_ugn/gnat_and_program_execution id51}@anchor{14c}@anchor{gnat_ugn/gnat_and_program_execution performing-dimensionality-analysis-in-gnat}@anchor{1a9}
 @section Performing Dimensionality Analysis in GNAT
 
 
@@ -22039,7 +22091,7 @@ passing (the dimension vector for the actual parameter must be equal to the
 dimension vector for the formal parameter).
 
 @node Stack Related Facilities,Memory Management Issues,Performing Dimensionality Analysis in GNAT,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id52}@anchor{14b}@anchor{gnat_ugn/gnat_and_program_execution stack-related-facilities}@anchor{1a8}
+@anchor{gnat_ugn/gnat_and_program_execution id52}@anchor{14d}@anchor{gnat_ugn/gnat_and_program_execution stack-related-facilities}@anchor{1aa}
 @section Stack Related Facilities
 
 
@@ -22055,7 +22107,7 @@ particular, it deals with dynamic and static stack usage measurements.
 @end menu
 
 @node Stack Overflow Checking,Static Stack Usage Analysis,,Stack Related Facilities
-@anchor{gnat_ugn/gnat_and_program_execution id53}@anchor{1a9}@anchor{gnat_ugn/gnat_and_program_execution stack-overflow-checking}@anchor{e5}
+@anchor{gnat_ugn/gnat_and_program_execution id53}@anchor{1ab}@anchor{gnat_ugn/gnat_and_program_execution stack-overflow-checking}@anchor{e7}
 @subsection Stack Overflow Checking
 
 
@@ -22092,7 +22144,7 @@ If the space is exceeded, then a @code{Storage_Error} exception is raised.
 
 For declared tasks, the default stack size is defined by the GNAT runtime,
 whose size may be modified at bind time through the @code{-d} bind switch
-(@ref{110,,Switches for gnatbind}). Task specific stack sizes may be set using the
+(@ref{112,,Switches for gnatbind}). Task specific stack sizes may be set using the
 @code{Storage_Size} pragma.
 
 For the environment task, the stack size is determined by the operating system.
@@ -22100,7 +22152,7 @@ Consequently, to modify the size of the environment task please refer to your
 operating system documentation.
 
 @node Static Stack Usage Analysis,Dynamic Stack Usage Analysis,Stack Overflow Checking,Stack Related Facilities
-@anchor{gnat_ugn/gnat_and_program_execution id54}@anchor{1aa}@anchor{gnat_ugn/gnat_and_program_execution static-stack-usage-analysis}@anchor{e6}
+@anchor{gnat_ugn/gnat_and_program_execution id54}@anchor{1ac}@anchor{gnat_ugn/gnat_and_program_execution static-stack-usage-analysis}@anchor{e8}
 @subsection Static Stack Usage Analysis
 
 
@@ -22149,7 +22201,7 @@ subprogram whose stack usage might be larger than the specified amount of
 bytes.  The wording is in keeping with the qualifier documented above.
 
 @node Dynamic Stack Usage Analysis,,Static Stack Usage Analysis,Stack Related Facilities
-@anchor{gnat_ugn/gnat_and_program_execution dynamic-stack-usage-analysis}@anchor{113}@anchor{gnat_ugn/gnat_and_program_execution id55}@anchor{1ab}
+@anchor{gnat_ugn/gnat_and_program_execution dynamic-stack-usage-analysis}@anchor{115}@anchor{gnat_ugn/gnat_and_program_execution id55}@anchor{1ad}
 @subsection Dynamic Stack Usage Analysis
 
 
@@ -22231,7 +22283,7 @@ The package @code{GNAT.Task_Stack_Usage} provides facilities to get
 stack-usage reports at run time. See its body for the details.
 
 @node Memory Management Issues,,Stack Related Facilities,GNAT and Program Execution
-@anchor{gnat_ugn/gnat_and_program_execution id56}@anchor{14c}@anchor{gnat_ugn/gnat_and_program_execution memory-management-issues}@anchor{1ac}
+@anchor{gnat_ugn/gnat_and_program_execution id56}@anchor{14e}@anchor{gnat_ugn/gnat_and_program_execution memory-management-issues}@anchor{1ae}
 @section Memory Management Issues
 
 
@@ -22247,7 +22299,7 @@ incorrect uses of access values (including ‘dangling references’).
 @end menu
 
 @node Some Useful Memory Pools,The GNAT Debug Pool Facility,,Memory Management Issues
-@anchor{gnat_ugn/gnat_and_program_execution id57}@anchor{1ad}@anchor{gnat_ugn/gnat_and_program_execution some-useful-memory-pools}@anchor{1ae}
+@anchor{gnat_ugn/gnat_and_program_execution id57}@anchor{1af}@anchor{gnat_ugn/gnat_and_program_execution some-useful-memory-pools}@anchor{1b0}
 @subsection Some Useful Memory Pools
 
 
@@ -22328,7 +22380,7 @@ for T1'Storage_Size use 10_000;
 @end quotation
 
 @node The GNAT Debug Pool Facility,,Some Useful Memory Pools,Memory Management Issues
-@anchor{gnat_ugn/gnat_and_program_execution id58}@anchor{1af}@anchor{gnat_ugn/gnat_and_program_execution the-gnat-debug-pool-facility}@anchor{1b0}
+@anchor{gnat_ugn/gnat_and_program_execution id58}@anchor{1b1}@anchor{gnat_ugn/gnat_and_program_execution the-gnat-debug-pool-facility}@anchor{1b2}
 @subsection The GNAT Debug Pool Facility
 
 
@@ -22491,7 +22543,7 @@ Debug Pool info:
 @c -- E.g. Ada |nbsp| 95
 
 @node Platform-Specific Information,Example of Binder Output File,GNAT and Program Execution,Top
-@anchor{gnat_ugn/platform_specific_information doc}@anchor{1b1}@anchor{gnat_ugn/platform_specific_information id1}@anchor{1b2}@anchor{gnat_ugn/platform_specific_information platform-specific-information}@anchor{d}
+@anchor{gnat_ugn/platform_specific_information doc}@anchor{1b3}@anchor{gnat_ugn/platform_specific_information id1}@anchor{1b4}@anchor{gnat_ugn/platform_specific_information platform-specific-information}@anchor{d}
 @chapter Platform-Specific Information
 
 
@@ -22509,7 +22561,7 @@ related to the GNAT implementation on specific Operating Systems.
 @end menu
 
 @node Run-Time Libraries,Specifying a Run-Time Library,,Platform-Specific Information
-@anchor{gnat_ugn/platform_specific_information id2}@anchor{1b3}@anchor{gnat_ugn/platform_specific_information run-time-libraries}@anchor{1b4}
+@anchor{gnat_ugn/platform_specific_information id2}@anchor{1b5}@anchor{gnat_ugn/platform_specific_information run-time-libraries}@anchor{1b6}
 @section Run-Time Libraries
 
 
@@ -22570,7 +22622,7 @@ are supplied on various GNAT platforms.
 @end menu
 
 @node Summary of Run-Time Configurations,,,Run-Time Libraries
-@anchor{gnat_ugn/platform_specific_information id3}@anchor{1b5}@anchor{gnat_ugn/platform_specific_information summary-of-run-time-configurations}@anchor{1b6}
+@anchor{gnat_ugn/platform_specific_information id3}@anchor{1b7}@anchor{gnat_ugn/platform_specific_information summary-of-run-time-configurations}@anchor{1b8}
 @subsection Summary of Run-Time Configurations
 
 
@@ -22670,7 +22722,7 @@ ZCX
 
 
 @node Specifying a Run-Time Library,GNU/Linux Topics,Run-Time Libraries,Platform-Specific Information
-@anchor{gnat_ugn/platform_specific_information id4}@anchor{1b7}@anchor{gnat_ugn/platform_specific_information specifying-a-run-time-library}@anchor{1b8}
+@anchor{gnat_ugn/platform_specific_information id4}@anchor{1b9}@anchor{gnat_ugn/platform_specific_information specifying-a-run-time-library}@anchor{1ba}
 @section Specifying a Run-Time Library
 
 
@@ -22757,7 +22809,7 @@ Alternatively, you can specify @code{rts-sjlj/adainclude} in the file
 
 Selecting another run-time library temporarily can be
 achieved by using the @code{--RTS} switch, e.g., @code{--RTS=sjlj}
-@anchor{gnat_ugn/platform_specific_information choosing-the-scheduling-policy}@anchor{1b9}
+@anchor{gnat_ugn/platform_specific_information choosing-the-scheduling-policy}@anchor{1bb}
 @geindex SCHED_FIFO scheduling policy
 
 @geindex SCHED_RR scheduling policy
@@ -22770,7 +22822,7 @@ achieved by using the @code{--RTS} switch, e.g., @code{--RTS=sjlj}
 @end menu
 
 @node Choosing the Scheduling Policy,,,Specifying a Run-Time Library
-@anchor{gnat_ugn/platform_specific_information id5}@anchor{1ba}
+@anchor{gnat_ugn/platform_specific_information id5}@anchor{1bc}
 @subsection Choosing the Scheduling Policy
 
 
@@ -22832,7 +22884,7 @@ have sufficient priviledge for running the container image.
 @geindex GNU/Linux
 
 @node GNU/Linux Topics,Microsoft Windows Topics,Specifying a Run-Time Library,Platform-Specific Information
-@anchor{gnat_ugn/platform_specific_information gnu-linux-topics}@anchor{1bb}@anchor{gnat_ugn/platform_specific_information id6}@anchor{1bc}
+@anchor{gnat_ugn/platform_specific_information gnu-linux-topics}@anchor{1bd}@anchor{gnat_ugn/platform_specific_information id6}@anchor{1be}
 @section GNU/Linux Topics
 
 
@@ -22846,7 +22898,7 @@ This section describes topics that are specific to GNU/Linux platforms.
 @end menu
 
 @node Required Packages on GNU/Linux,Position Independent Executable PIE Enabled by Default on Linux,,GNU/Linux Topics
-@anchor{gnat_ugn/platform_specific_information id7}@anchor{1bd}@anchor{gnat_ugn/platform_specific_information required-packages-on-gnu-linux}@anchor{1be}
+@anchor{gnat_ugn/platform_specific_information id7}@anchor{1bf}@anchor{gnat_ugn/platform_specific_information required-packages-on-gnu-linux}@anchor{1c0}
 @subsection Required Packages on GNU/Linux
 
 
@@ -22883,7 +22935,7 @@ Other GNU/Linux distributions might be choosing a different name
 for those packages.
 
 @node Position Independent Executable PIE Enabled by Default on Linux,A GNU/Linux Debug Quirk,Required Packages on GNU/Linux,GNU/Linux Topics
-@anchor{gnat_ugn/platform_specific_information pie-enabled-by-default-on-linux}@anchor{1bf}@anchor{gnat_ugn/platform_specific_information position-independent-executable-pie-enabled-by-default-on-linux}@anchor{1c0}
+@anchor{gnat_ugn/platform_specific_information pie-enabled-by-default-on-linux}@anchor{1c1}@anchor{gnat_ugn/platform_specific_information position-independent-executable-pie-enabled-by-default-on-linux}@anchor{1c2}
 @subsection Position Independent Executable (PIE) Enabled by Default on Linux
 
 
@@ -22927,7 +22979,7 @@ dependencies rebuilt with PIE enabled (compiled with @code{-fPIE}
 and linked with @code{-pie}).
 
 @node A GNU/Linux Debug Quirk,,Position Independent Executable PIE Enabled by Default on Linux,GNU/Linux Topics
-@anchor{gnat_ugn/platform_specific_information a-gnu-linux-debug-quirk}@anchor{1c1}@anchor{gnat_ugn/platform_specific_information id8}@anchor{1c2}
+@anchor{gnat_ugn/platform_specific_information a-gnu-linux-debug-quirk}@anchor{1c3}@anchor{gnat_ugn/platform_specific_information id8}@anchor{1c4}
 @subsection A GNU/Linux Debug Quirk
 
 
@@ -22947,7 +22999,7 @@ the symptoms most commonly observed.
 @geindex Windows
 
 @node Microsoft Windows Topics,Mac OS Topics,GNU/Linux Topics,Platform-Specific Information
-@anchor{gnat_ugn/platform_specific_information id9}@anchor{1c3}@anchor{gnat_ugn/platform_specific_information microsoft-windows-topics}@anchor{1c4}
+@anchor{gnat_ugn/platform_specific_information id9}@anchor{1c5}@anchor{gnat_ugn/platform_specific_information microsoft-windows-topics}@anchor{1c6}
 @section Microsoft Windows Topics
 
 
@@ -22968,7 +23020,7 @@ platforms.
 @end menu
 
 @node Using GNAT on Windows,Using a network installation of GNAT,,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information id10}@anchor{1c5}@anchor{gnat_ugn/platform_specific_information using-gnat-on-windows}@anchor{1c6}
+@anchor{gnat_ugn/platform_specific_information id10}@anchor{1c7}@anchor{gnat_ugn/platform_specific_information using-gnat-on-windows}@anchor{1c8}
 @subsection Using GNAT on Windows
 
 
@@ -23045,7 +23097,7 @@ uninstall or integrate different GNAT products.
 @end itemize
 
 @node Using a network installation of GNAT,CONSOLE and WINDOWS subsystems,Using GNAT on Windows,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information id11}@anchor{1c7}@anchor{gnat_ugn/platform_specific_information using-a-network-installation-of-gnat}@anchor{1c8}
+@anchor{gnat_ugn/platform_specific_information id11}@anchor{1c9}@anchor{gnat_ugn/platform_specific_information using-a-network-installation-of-gnat}@anchor{1ca}
 @subsection Using a network installation of GNAT
 
 
@@ -23072,7 +23124,7 @@ transfer of large amounts of data across the network and will likely cause
 serious performance penalty.
 
 @node CONSOLE and WINDOWS subsystems,Temporary Files,Using a network installation of GNAT,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information console-and-windows-subsystems}@anchor{1c9}@anchor{gnat_ugn/platform_specific_information id12}@anchor{1ca}
+@anchor{gnat_ugn/platform_specific_information console-and-windows-subsystems}@anchor{1cb}@anchor{gnat_ugn/platform_specific_information id12}@anchor{1cc}
 @subsection CONSOLE and WINDOWS subsystems
 
 
@@ -23097,7 +23149,7 @@ $ gnatmake winprog -largs -mwindows
 @end quotation
 
 @node Temporary Files,Disabling Command Line Argument Expansion,CONSOLE and WINDOWS subsystems,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information id13}@anchor{1cb}@anchor{gnat_ugn/platform_specific_information temporary-files}@anchor{1cc}
+@anchor{gnat_ugn/platform_specific_information id13}@anchor{1cd}@anchor{gnat_ugn/platform_specific_information temporary-files}@anchor{1ce}
 @subsection Temporary Files
 
 
@@ -23136,7 +23188,7 @@ environments where you may not have write access to some
 directories.
 
 @node Disabling Command Line Argument Expansion,Windows Socket Timeouts,Temporary Files,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information disabling-command-line-argument-expansion}@anchor{1cd}
+@anchor{gnat_ugn/platform_specific_information disabling-command-line-argument-expansion}@anchor{1cf}
 @subsection Disabling Command Line Argument Expansion
 
 
@@ -23207,7 +23259,7 @@ Ada.Command_Line.Argument (1) -> "'*.txt'"
 @end example
 
 @node Windows Socket Timeouts,Mixed-Language Programming on Windows,Disabling Command Line Argument Expansion,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information windows-socket-timeouts}@anchor{1ce}
+@anchor{gnat_ugn/platform_specific_information windows-socket-timeouts}@anchor{1d0}
 @subsection Windows Socket Timeouts
 
 
@@ -23253,7 +23305,7 @@ shorter than 500 ms is needed on these Windows versions, a call to
 Check_Selector should be added before any socket read or write operations.
 
 @node Mixed-Language Programming on Windows,Windows Specific Add-Ons,Windows Socket Timeouts,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information id14}@anchor{1cf}@anchor{gnat_ugn/platform_specific_information mixed-language-programming-on-windows}@anchor{1d0}
+@anchor{gnat_ugn/platform_specific_information id14}@anchor{1d1}@anchor{gnat_ugn/platform_specific_information mixed-language-programming-on-windows}@anchor{1d2}
 @subsection Mixed-Language Programming on Windows
 
 
@@ -23275,12 +23327,12 @@ to use the Microsoft tools for your C++ code, you have two choices:
 Encapsulate your C++ code in a DLL to be linked with your Ada
 application. In this case, use the Microsoft or whatever environment to
 build the DLL and use GNAT to build your executable
-(@ref{1d1,,Using DLLs with GNAT}).
+(@ref{1d3,,Using DLLs with GNAT}).
 
 @item 
 Or you can encapsulate your Ada code in a DLL to be linked with the
 other part of your application. In this case, use GNAT to build the DLL
-(@ref{1d2,,Building DLLs with GNAT Project files}) and use the Microsoft
+(@ref{1d4,,Building DLLs with GNAT Project files}) and use the Microsoft
 or whatever environment to build your executable.
 @end itemize
 
@@ -23337,7 +23389,7 @@ native SEH support is used.
 @end menu
 
 @node Windows Calling Conventions,Introduction to Dynamic Link Libraries DLLs,,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information id15}@anchor{1d3}@anchor{gnat_ugn/platform_specific_information windows-calling-conventions}@anchor{1d4}
+@anchor{gnat_ugn/platform_specific_information id15}@anchor{1d5}@anchor{gnat_ugn/platform_specific_information windows-calling-conventions}@anchor{1d6}
 @subsubsection Windows Calling Conventions
 
 
@@ -23382,7 +23434,7 @@ are available for Windows:
 @end menu
 
 @node C Calling Convention,Stdcall Calling Convention,,Windows Calling Conventions
-@anchor{gnat_ugn/platform_specific_information c-calling-convention}@anchor{1d5}@anchor{gnat_ugn/platform_specific_information id16}@anchor{1d6}
+@anchor{gnat_ugn/platform_specific_information c-calling-convention}@anchor{1d7}@anchor{gnat_ugn/platform_specific_information id16}@anchor{1d8}
 @subsubsection @code{C} Calling Convention
 
 
@@ -23424,10 +23476,10 @@ is missing, as in the above example, this parameter is set to be the
 When importing a variable defined in C, you should always use the @code{C}
 calling convention unless the object containing the variable is part of a
 DLL (in which case you should use the @code{Stdcall} calling
-convention, @ref{1d7,,Stdcall Calling Convention}).
+convention, @ref{1d9,,Stdcall Calling Convention}).
 
 @node Stdcall Calling Convention,Win32 Calling Convention,C Calling Convention,Windows Calling Conventions
-@anchor{gnat_ugn/platform_specific_information id17}@anchor{1d8}@anchor{gnat_ugn/platform_specific_information stdcall-calling-convention}@anchor{1d7}
+@anchor{gnat_ugn/platform_specific_information id17}@anchor{1da}@anchor{gnat_ugn/platform_specific_information stdcall-calling-convention}@anchor{1d9}
 @subsubsection @code{Stdcall} Calling Convention
 
 
@@ -23524,7 +23576,7 @@ Note that to ease building cross-platform bindings this convention
 will be handled as a @code{C} calling convention on non-Windows platforms.
 
 @node Win32 Calling Convention,DLL Calling Convention,Stdcall Calling Convention,Windows Calling Conventions
-@anchor{gnat_ugn/platform_specific_information id18}@anchor{1d9}@anchor{gnat_ugn/platform_specific_information win32-calling-convention}@anchor{1da}
+@anchor{gnat_ugn/platform_specific_information id18}@anchor{1db}@anchor{gnat_ugn/platform_specific_information win32-calling-convention}@anchor{1dc}
 @subsubsection @code{Win32} Calling Convention
 
 
@@ -23532,7 +23584,7 @@ This convention, which is GNAT-specific is fully equivalent to the
 @code{Stdcall} calling convention described above.
 
 @node DLL Calling Convention,,Win32 Calling Convention,Windows Calling Conventions
-@anchor{gnat_ugn/platform_specific_information dll-calling-convention}@anchor{1db}@anchor{gnat_ugn/platform_specific_information id19}@anchor{1dc}
+@anchor{gnat_ugn/platform_specific_information dll-calling-convention}@anchor{1dd}@anchor{gnat_ugn/platform_specific_information id19}@anchor{1de}
 @subsubsection @code{DLL} Calling Convention
 
 
@@ -23540,7 +23592,7 @@ This convention, which is GNAT-specific is fully equivalent to the
 @code{Stdcall} calling convention described above.
 
 @node Introduction to Dynamic Link Libraries DLLs,Using DLLs with GNAT,Windows Calling Conventions,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information id20}@anchor{1dd}@anchor{gnat_ugn/platform_specific_information introduction-to-dynamic-link-libraries-dlls}@anchor{1de}
+@anchor{gnat_ugn/platform_specific_information id20}@anchor{1df}@anchor{gnat_ugn/platform_specific_information introduction-to-dynamic-link-libraries-dlls}@anchor{1e0}
 @subsubsection Introduction to Dynamic Link Libraries (DLLs)
 
 
@@ -23624,10 +23676,10 @@ As a side note, an interesting difference between Microsoft DLLs and
 Unix shared libraries, is the fact that on most Unix systems all public
 routines are exported by default in a Unix shared library, while under
 Windows it is possible (but not required) to list exported routines in
-a definition file (see @ref{1df,,The Definition File}).
+a definition file (see @ref{1e1,,The Definition File}).
 
 @node Using DLLs with GNAT,Building DLLs with GNAT Project files,Introduction to Dynamic Link Libraries DLLs,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information id21}@anchor{1e0}@anchor{gnat_ugn/platform_specific_information using-dlls-with-gnat}@anchor{1d1}
+@anchor{gnat_ugn/platform_specific_information id21}@anchor{1e2}@anchor{gnat_ugn/platform_specific_information using-dlls-with-gnat}@anchor{1d3}
 @subsubsection Using DLLs with GNAT
 
 
@@ -23718,7 +23770,7 @@ example a fictitious DLL called @code{API.dll}.
 @end menu
 
 @node Creating an Ada Spec for the DLL Services,Creating an Import Library,,Using DLLs with GNAT
-@anchor{gnat_ugn/platform_specific_information creating-an-ada-spec-for-the-dll-services}@anchor{1e1}@anchor{gnat_ugn/platform_specific_information id22}@anchor{1e2}
+@anchor{gnat_ugn/platform_specific_information creating-an-ada-spec-for-the-dll-services}@anchor{1e3}@anchor{gnat_ugn/platform_specific_information id22}@anchor{1e4}
 @subsubsection Creating an Ada Spec for the DLL Services
 
 
@@ -23758,7 +23810,7 @@ end API;
 @end quotation
 
 @node Creating an Import Library,,Creating an Ada Spec for the DLL Services,Using DLLs with GNAT
-@anchor{gnat_ugn/platform_specific_information creating-an-import-library}@anchor{1e3}@anchor{gnat_ugn/platform_specific_information id23}@anchor{1e4}
+@anchor{gnat_ugn/platform_specific_information creating-an-import-library}@anchor{1e5}@anchor{gnat_ugn/platform_specific_information id23}@anchor{1e6}
 @subsubsection Creating an Import Library
 
 
@@ -23772,7 +23824,7 @@ as in this case it is possible to link directly against the
 DLL. Otherwise read on.
 
 @geindex Definition file
-@anchor{gnat_ugn/platform_specific_information the-definition-file}@anchor{1df}
+@anchor{gnat_ugn/platform_specific_information the-definition-file}@anchor{1e1}
 @subsubheading The Definition File
 
 
@@ -23820,17 +23872,17 @@ EXPORTS
 @end table
 
 Note that you must specify the correct suffix (@code{@@@var{nn}})
-(see @ref{1d4,,Windows Calling Conventions}) for a Stdcall
+(see @ref{1d6,,Windows Calling Conventions}) for a Stdcall
 calling convention function in the exported symbols list.
 
 There can actually be other sections in a definition file, but these
 sections are not relevant to the discussion at hand.
-@anchor{gnat_ugn/platform_specific_information create-def-file-automatically}@anchor{1e5}
+@anchor{gnat_ugn/platform_specific_information create-def-file-automatically}@anchor{1e7}
 @subsubheading Creating a Definition File Automatically
 
 
 You can automatically create the definition file @code{API.def}
-(see @ref{1df,,The Definition File}) from a DLL.
+(see @ref{1e1,,The Definition File}) from a DLL.
 For that use the @code{dlltool} program as follows:
 
 @quotation
@@ -23840,7 +23892,7 @@ $ dlltool API.dll -z API.def --export-all-symbols
 @end example
 
 Note that if some routines in the DLL have the @code{Stdcall} convention
-(@ref{1d4,,Windows Calling Conventions}) with stripped @code{@@@var{nn}}
+(@ref{1d6,,Windows Calling Conventions}) with stripped @code{@@@var{nn}}
 suffix then you’ll have to edit @code{api.def} to add it, and specify
 @code{-k} to @code{gnatdll} when creating the import library.
 
@@ -23864,13 +23916,13 @@ tells you what symbol is expected. You just have to go back to the
 definition file and add the right suffix.
 @end itemize
 @end quotation
-@anchor{gnat_ugn/platform_specific_information gnat-style-import-library}@anchor{1e6}
+@anchor{gnat_ugn/platform_specific_information gnat-style-import-library}@anchor{1e8}
 @subsubheading GNAT-Style Import Library
 
 
 To create a static import library from @code{API.dll} with the GNAT tools
 you should create the .def file, then use @code{gnatdll} tool
-(see @ref{1e7,,Using gnatdll}) as follows:
+(see @ref{1e9,,Using gnatdll}) as follows:
 
 @quotation
 
@@ -23886,15 +23938,15 @@ definition file name is @code{xyz.def}, the import library name will
 be @code{libxyz.a}. Note that in the previous example option
 @code{-e} could have been removed because the name of the definition
 file (before the @code{.def} suffix) is the same as the name of the
-DLL (@ref{1e7,,Using gnatdll} for more information about @code{gnatdll}).
+DLL (@ref{1e9,,Using gnatdll} for more information about @code{gnatdll}).
 @end quotation
-@anchor{gnat_ugn/platform_specific_information msvs-style-import-library}@anchor{1e8}
+@anchor{gnat_ugn/platform_specific_information msvs-style-import-library}@anchor{1ea}
 @subsubheading Microsoft-Style Import Library
 
 
 A Microsoft import library is needed only if you plan to make an
 Ada DLL available to applications developed with Microsoft
-tools (@ref{1d0,,Mixed-Language Programming on Windows}).
+tools (@ref{1d2,,Mixed-Language Programming on Windows}).
 
 To create a Microsoft-style import library for @code{API.dll} you
 should create the .def file, then build the actual import library using
@@ -23918,7 +23970,7 @@ See the Microsoft documentation for further details about the usage of
 @end quotation
 
 @node Building DLLs with GNAT Project files,Building DLLs with GNAT,Using DLLs with GNAT,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information building-dlls-with-gnat-project-files}@anchor{1d2}@anchor{gnat_ugn/platform_specific_information id24}@anchor{1e9}
+@anchor{gnat_ugn/platform_specific_information building-dlls-with-gnat-project-files}@anchor{1d4}@anchor{gnat_ugn/platform_specific_information id24}@anchor{1eb}
 @subsubsection Building DLLs with GNAT Project files
 
 
@@ -23934,7 +23986,7 @@ when inside the @code{DllMain} routine which is used for auto-initialization
 of shared libraries, so it is not possible to have library level tasks in SALs.
 
 @node Building DLLs with GNAT,Building DLLs with gnatdll,Building DLLs with GNAT Project files,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information building-dlls-with-gnat}@anchor{1ea}@anchor{gnat_ugn/platform_specific_information id25}@anchor{1eb}
+@anchor{gnat_ugn/platform_specific_information building-dlls-with-gnat}@anchor{1ec}@anchor{gnat_ugn/platform_specific_information id25}@anchor{1ed}
 @subsubsection Building DLLs with GNAT
 
 
@@ -23965,7 +24017,7 @@ $ gcc -shared -shared-libgcc -o api.dll obj1.o obj2.o ...
 It is important to note that in this case all symbols found in the
 object files are automatically exported. It is possible to restrict
 the set of symbols to export by passing to @code{gcc} a definition
-file (see @ref{1df,,The Definition File}).
+file (see @ref{1e1,,The Definition File}).
 For example:
 
 @example
@@ -24003,7 +24055,7 @@ $ gnatmake main -Iapilib -bargs -shared -largs -Lapilib -lAPI
 @end quotation
 
 @node Building DLLs with gnatdll,Ada DLLs and Finalization,Building DLLs with GNAT,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information building-dlls-with-gnatdll}@anchor{1ec}@anchor{gnat_ugn/platform_specific_information id26}@anchor{1ed}
+@anchor{gnat_ugn/platform_specific_information building-dlls-with-gnatdll}@anchor{1ee}@anchor{gnat_ugn/platform_specific_information id26}@anchor{1ef}
 @subsubsection Building DLLs with gnatdll
 
 
@@ -24011,8 +24063,8 @@ $ gnatmake main -Iapilib -bargs -shared -largs -Lapilib -lAPI
 @geindex building
 
 Note that it is preferred to use GNAT Project files
-(@ref{1d2,,Building DLLs with GNAT Project files}) or the built-in GNAT
-DLL support (@ref{1ea,,Building DLLs with GNAT}) or to build DLLs.
+(@ref{1d4,,Building DLLs with GNAT Project files}) or the built-in GNAT
+DLL support (@ref{1ec,,Building DLLs with GNAT}) or to build DLLs.
 
 This section explains how to build DLLs containing Ada code using
 @code{gnatdll}. These DLLs will be referred to as Ada DLLs in the
@@ -24028,20 +24080,20 @@ non-Ada applications are as follows:
 You need to mark each Ada entity exported by the DLL with a @code{C} or
 @code{Stdcall} calling convention to avoid any Ada name mangling for the
 entities exported by the DLL
-(see @ref{1ee,,Exporting Ada Entities}). You can
+(see @ref{1f0,,Exporting Ada Entities}). You can
 skip this step if you plan to use the Ada DLL only from Ada applications.
 
 @item 
 Your Ada code must export an initialization routine which calls the routine
 @code{adainit} generated by @code{gnatbind} to perform the elaboration of
-the Ada code in the DLL (@ref{1ef,,Ada DLLs and Elaboration}). The initialization
+the Ada code in the DLL (@ref{1f1,,Ada DLLs and Elaboration}). The initialization
 routine exported by the Ada DLL must be invoked by the clients of the DLL
 to initialize the DLL.
 
 @item 
 When useful, the DLL should also export a finalization routine which calls
 routine @code{adafinal} generated by @code{gnatbind} to perform the
-finalization of the Ada code in the DLL (@ref{1f0,,Ada DLLs and Finalization}).
+finalization of the Ada code in the DLL (@ref{1f2,,Ada DLLs and Finalization}).
 The finalization routine exported by the Ada DLL must be invoked by the
 clients of the DLL when the DLL services are no further needed.
 
@@ -24051,11 +24103,11 @@ of the programming languages to which you plan to make the DLL available.
 
 @item 
 You must provide a definition file listing the exported entities
-(@ref{1df,,The Definition File}).
+(@ref{1e1,,The Definition File}).
 
 @item 
 Finally you must use @code{gnatdll} to produce the DLL and the import
-library (@ref{1e7,,Using gnatdll}).
+library (@ref{1e9,,Using gnatdll}).
 @end itemize
 
 Note that a relocatable DLL stripped using the @code{strip}
@@ -24075,7 +24127,7 @@ chapter of the `GPRbuild User’s Guide'.
 @end menu
 
 @node Limitations When Using Ada DLLs from Ada,Exporting Ada Entities,,Building DLLs with gnatdll
-@anchor{gnat_ugn/platform_specific_information limitations-when-using-ada-dlls-from-ada}@anchor{1f1}
+@anchor{gnat_ugn/platform_specific_information limitations-when-using-ada-dlls-from-ada}@anchor{1f3}
 @subsubsection Limitations When Using Ada DLLs from Ada
 
 
@@ -24096,7 +24148,7 @@ It is completely safe to exchange plain elementary, array or record types,
 Windows object handles, etc.
 
 @node Exporting Ada Entities,Ada DLLs and Elaboration,Limitations When Using Ada DLLs from Ada,Building DLLs with gnatdll
-@anchor{gnat_ugn/platform_specific_information exporting-ada-entities}@anchor{1ee}@anchor{gnat_ugn/platform_specific_information id27}@anchor{1f2}
+@anchor{gnat_ugn/platform_specific_information exporting-ada-entities}@anchor{1f0}@anchor{gnat_ugn/platform_specific_information id27}@anchor{1f4}
 @subsubsection Exporting Ada Entities
 
 
@@ -24196,10 +24248,10 @@ end API;
 Note that if you do not export the Ada entities with a @code{C} or
 @code{Stdcall} convention you will have to provide the mangled Ada names
 in the definition file of the Ada DLL
-(@ref{1f3,,Creating the Definition File}).
+(@ref{1f5,,Creating the Definition File}).
 
 @node Ada DLLs and Elaboration,,Exporting Ada Entities,Building DLLs with gnatdll
-@anchor{gnat_ugn/platform_specific_information ada-dlls-and-elaboration}@anchor{1ef}@anchor{gnat_ugn/platform_specific_information id28}@anchor{1f4}
+@anchor{gnat_ugn/platform_specific_information ada-dlls-and-elaboration}@anchor{1f1}@anchor{gnat_ugn/platform_specific_information id28}@anchor{1f6}
 @subsubsection Ada DLLs and Elaboration
 
 
@@ -24217,7 +24269,7 @@ the Ada elaboration routine @code{adainit} generated by the GNAT binder
 (@ref{a0,,Binding with Non-Ada Main Programs}). See the body of
 @code{Initialize_Api} for an example. Note that the GNAT binder is
 automatically invoked during the DLL build process by the @code{gnatdll}
-tool (@ref{1e7,,Using gnatdll}).
+tool (@ref{1e9,,Using gnatdll}).
 
 When a DLL is loaded, Windows systematically invokes a routine called
 @code{DllMain}. It would therefore be possible to call @code{adainit}
@@ -24230,7 +24282,7 @@ time), which means that the GNAT run-time will deadlock waiting for the
 newly created task to complete its initialization.
 
 @node Ada DLLs and Finalization,Creating a Spec for Ada DLLs,Building DLLs with gnatdll,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information ada-dlls-and-finalization}@anchor{1f0}@anchor{gnat_ugn/platform_specific_information id29}@anchor{1f5}
+@anchor{gnat_ugn/platform_specific_information ada-dlls-and-finalization}@anchor{1f2}@anchor{gnat_ugn/platform_specific_information id29}@anchor{1f7}
 @subsubsection Ada DLLs and Finalization
 
 
@@ -24245,10 +24297,10 @@ routine @code{adafinal} generated by the GNAT binder
 See the body of @code{Finalize_Api} for an
 example. As already pointed out the GNAT binder is automatically invoked
 during the DLL build process by the @code{gnatdll} tool
-(@ref{1e7,,Using gnatdll}).
+(@ref{1e9,,Using gnatdll}).
 
 @node Creating a Spec for Ada DLLs,GNAT and Windows Resources,Ada DLLs and Finalization,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information creating-a-spec-for-ada-dlls}@anchor{1f6}@anchor{gnat_ugn/platform_specific_information id30}@anchor{1f7}
+@anchor{gnat_ugn/platform_specific_information creating-a-spec-for-ada-dlls}@anchor{1f8}@anchor{gnat_ugn/platform_specific_information id30}@anchor{1f9}
 @subsubsection Creating a Spec for Ada DLLs
 
 
@@ -24306,7 +24358,7 @@ end API;
 @end menu
 
 @node Creating the Definition File,Using gnatdll,,Creating a Spec for Ada DLLs
-@anchor{gnat_ugn/platform_specific_information creating-the-definition-file}@anchor{1f3}@anchor{gnat_ugn/platform_specific_information id31}@anchor{1f8}
+@anchor{gnat_ugn/platform_specific_information creating-the-definition-file}@anchor{1f5}@anchor{gnat_ugn/platform_specific_information id31}@anchor{1fa}
 @subsubsection Creating the Definition File
 
 
@@ -24342,7 +24394,7 @@ EXPORTS
 @end quotation
 
 @node Using gnatdll,,Creating the Definition File,Creating a Spec for Ada DLLs
-@anchor{gnat_ugn/platform_specific_information id32}@anchor{1f9}@anchor{gnat_ugn/platform_specific_information using-gnatdll}@anchor{1e7}
+@anchor{gnat_ugn/platform_specific_information id32}@anchor{1fb}@anchor{gnat_ugn/platform_specific_information using-gnatdll}@anchor{1e9}
 @subsubsection Using @code{gnatdll}
 
 
@@ -24553,7 +24605,7 @@ asks @code{gnatlink} to generate the routines @code{DllMain} and
 is loaded into memory.
 
 @item 
-@code{gnatdll} uses @code{dlltool} (see @ref{1fa,,Using dlltool}) to build the
+@code{gnatdll} uses @code{dlltool} (see @ref{1fc,,Using dlltool}) to build the
 export table (@code{api.exp}). The export table contains the relocation
 information in a form which can be used during the final link to ensure
 that the Windows loader is able to place the DLL anywhere in memory.
@@ -24592,7 +24644,7 @@ $ gnatbind -n api
 $ gnatlink api api.exp -o api.dll -mdll
 @end example
 @end itemize
-@anchor{gnat_ugn/platform_specific_information using-dlltool}@anchor{1fa}
+@anchor{gnat_ugn/platform_specific_information using-dlltool}@anchor{1fc}
 @subsubheading Using @code{dlltool}
 
 
@@ -24651,7 +24703,7 @@ DLL in the static import library generated by @code{dlltool} with switch
 @item @code{-k}
 
 Kill @code{@@@var{nn}} from exported names
-(@ref{1d4,,Windows Calling Conventions}
+(@ref{1d6,,Windows Calling Conventions}
 for a discussion about @code{Stdcall}-style symbols).
 @end table
 
@@ -24707,7 +24759,7 @@ Use @code{assembler-name} as the assembler. The default is @code{as}.
 @end table
 
 @node GNAT and Windows Resources,Using GNAT DLLs from Microsoft Visual Studio Applications,Creating a Spec for Ada DLLs,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information gnat-and-windows-resources}@anchor{1fb}@anchor{gnat_ugn/platform_specific_information id33}@anchor{1fc}
+@anchor{gnat_ugn/platform_specific_information gnat-and-windows-resources}@anchor{1fd}@anchor{gnat_ugn/platform_specific_information id33}@anchor{1fe}
 @subsubsection GNAT and Windows Resources
 
 
@@ -24802,7 +24854,7 @@ the corresponding Microsoft documentation.
 @end menu
 
 @node Building Resources,Compiling Resources,,GNAT and Windows Resources
-@anchor{gnat_ugn/platform_specific_information building-resources}@anchor{1fd}@anchor{gnat_ugn/platform_specific_information id34}@anchor{1fe}
+@anchor{gnat_ugn/platform_specific_information building-resources}@anchor{1ff}@anchor{gnat_ugn/platform_specific_information id34}@anchor{200}
 @subsubsection Building Resources
 
 
@@ -24822,7 +24874,7 @@ complete description of the resource script language can be found in the
 Microsoft documentation.
 
 @node Compiling Resources,Using Resources,Building Resources,GNAT and Windows Resources
-@anchor{gnat_ugn/platform_specific_information compiling-resources}@anchor{1ff}@anchor{gnat_ugn/platform_specific_information id35}@anchor{200}
+@anchor{gnat_ugn/platform_specific_information compiling-resources}@anchor{201}@anchor{gnat_ugn/platform_specific_information id35}@anchor{202}
 @subsubsection Compiling Resources
 
 
@@ -24864,7 +24916,7 @@ $ windres -i myres.res -o myres.o
 @end quotation
 
 @node Using Resources,,Compiling Resources,GNAT and Windows Resources
-@anchor{gnat_ugn/platform_specific_information id36}@anchor{201}@anchor{gnat_ugn/platform_specific_information using-resources}@anchor{202}
+@anchor{gnat_ugn/platform_specific_information id36}@anchor{203}@anchor{gnat_ugn/platform_specific_information using-resources}@anchor{204}
 @subsubsection Using Resources
 
 
@@ -24884,7 +24936,7 @@ $ gnatmake myprog -largs myres.o
 @end quotation
 
 @node Using GNAT DLLs from Microsoft Visual Studio Applications,Debugging a DLL,GNAT and Windows Resources,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information using-gnat-dll-from-msvs}@anchor{203}@anchor{gnat_ugn/platform_specific_information using-gnat-dlls-from-microsoft-visual-studio-applications}@anchor{204}
+@anchor{gnat_ugn/platform_specific_information using-gnat-dll-from-msvs}@anchor{205}@anchor{gnat_ugn/platform_specific_information using-gnat-dlls-from-microsoft-visual-studio-applications}@anchor{206}
 @subsubsection Using GNAT DLLs from Microsoft Visual Studio Applications
 
 
@@ -24918,7 +24970,7 @@ $ gprbuild -p mylib.gpr
 @item 
 Produce a .def file for the symbols you need to interface with, either by
 hand or automatically with possibly some manual adjustments
-(see @ref{1e5,,Creating Definition File Automatically}):
+(see @ref{1e7,,Creating Definition File Automatically}):
 @end enumerate
 
 @quotation
@@ -24935,7 +24987,7 @@ $ dlltool libmylib.dll -z libmylib.def --export-all-symbols
 Make sure that MSVS command-line tools are accessible on the path.
 
 @item 
-Create the Microsoft-style import library (see @ref{1e8,,MSVS-Style Import Library}):
+Create the Microsoft-style import library (see @ref{1ea,,MSVS-Style Import Library}):
 @end enumerate
 
 @quotation
@@ -24977,7 +25029,7 @@ or copy the DLL into into the directory containing the .exe.
 @end enumerate
 
 @node Debugging a DLL,Setting Stack Size from gnatlink,Using GNAT DLLs from Microsoft Visual Studio Applications,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information debugging-a-dll}@anchor{205}@anchor{gnat_ugn/platform_specific_information id37}@anchor{206}
+@anchor{gnat_ugn/platform_specific_information debugging-a-dll}@anchor{207}@anchor{gnat_ugn/platform_specific_information id37}@anchor{208}
 @subsubsection Debugging a DLL
 
 
@@ -25015,7 +25067,7 @@ tools suite used to build the DLL.
 @end menu
 
 @node Program and DLL Both Built with GCC/GNAT,Program Built with Foreign Tools and DLL Built with GCC/GNAT,,Debugging a DLL
-@anchor{gnat_ugn/platform_specific_information id38}@anchor{207}@anchor{gnat_ugn/platform_specific_information program-and-dll-both-built-with-gcc-gnat}@anchor{208}
+@anchor{gnat_ugn/platform_specific_information id38}@anchor{209}@anchor{gnat_ugn/platform_specific_information program-and-dll-both-built-with-gcc-gnat}@anchor{20a}
 @subsubsection Program and DLL Both Built with GCC/GNAT
 
 
@@ -25025,7 +25077,7 @@ the process. Let’s suppose here that the main procedure is named
 @code{ada_main} and that in the DLL there is an entry point named
 @code{ada_dll}.
 
-The DLL (@ref{1de,,Introduction to Dynamic Link Libraries (DLLs)}) and
+The DLL (@ref{1e0,,Introduction to Dynamic Link Libraries (DLLs)}) and
 program must have been built with the debugging information (see GNAT -g
 switch). Here are the step-by-step instructions for debugging it:
 
@@ -25062,10 +25114,10 @@ Set a breakpoint inside the DLL
 
 At this stage a breakpoint is set inside the DLL. From there on
 you can use the standard approach to debug the whole program
-(@ref{14d,,Running and Debugging Ada Programs}).
+(@ref{14f,,Running and Debugging Ada Programs}).
 
 @node Program Built with Foreign Tools and DLL Built with GCC/GNAT,,Program and DLL Both Built with GCC/GNAT,Debugging a DLL
-@anchor{gnat_ugn/platform_specific_information id39}@anchor{209}@anchor{gnat_ugn/platform_specific_information program-built-with-foreign-tools-and-dll-built-with-gcc-gnat}@anchor{20a}
+@anchor{gnat_ugn/platform_specific_information id39}@anchor{20b}@anchor{gnat_ugn/platform_specific_information program-built-with-foreign-tools-and-dll-built-with-gcc-gnat}@anchor{20c}
 @subsubsection Program Built with Foreign Tools and DLL Built with GCC/GNAT
 
 
@@ -25082,7 +25134,7 @@ example some C code built with Microsoft Visual C) and that there is a
 DLL named @code{test.dll} containing an Ada entry point named
 @code{ada_dll}.
 
-The DLL (see @ref{1de,,Introduction to Dynamic Link Libraries (DLLs)}) must have
+The DLL (see @ref{1e0,,Introduction to Dynamic Link Libraries (DLLs)}) must have
 been built with debugging information (see the GNAT @code{-g} option).
 
 @subsubheading Debugging the DLL Directly
@@ -25148,7 +25200,7 @@ Continue the program.
 
 This will run the program until it reaches the breakpoint that has been
 set. From that point you can use the standard way to debug a program
-as described in (@ref{14d,,Running and Debugging Ada Programs}).
+as described in (@ref{14f,,Running and Debugging Ada Programs}).
 @end itemize
 
 It is also possible to debug the DLL by attaching to a running process.
@@ -25218,10 +25270,10 @@ Continue process execution.
 This last step will resume the process execution, and stop at
 the breakpoint we have set. From there you can use the standard
 approach to debug a program as described in
-@ref{14d,,Running and Debugging Ada Programs}.
+@ref{14f,,Running and Debugging Ada Programs}.
 
 @node Setting Stack Size from gnatlink,Setting Heap Size from gnatlink,Debugging a DLL,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information id40}@anchor{20b}@anchor{gnat_ugn/platform_specific_information setting-stack-size-from-gnatlink}@anchor{127}
+@anchor{gnat_ugn/platform_specific_information id40}@anchor{20d}@anchor{gnat_ugn/platform_specific_information setting-stack-size-from-gnatlink}@anchor{129}
 @subsubsection Setting Stack Size from @code{gnatlink}
 
 
@@ -25264,7 +25316,7 @@ because the comma is a separator for this option.
 @end itemize
 
 @node Setting Heap Size from gnatlink,,Setting Stack Size from gnatlink,Mixed-Language Programming on Windows
-@anchor{gnat_ugn/platform_specific_information id41}@anchor{20c}@anchor{gnat_ugn/platform_specific_information setting-heap-size-from-gnatlink}@anchor{128}
+@anchor{gnat_ugn/platform_specific_information id41}@anchor{20e}@anchor{gnat_ugn/platform_specific_information setting-heap-size-from-gnatlink}@anchor{12a}
 @subsubsection Setting Heap Size from @code{gnatlink}
 
 
@@ -25297,7 +25349,7 @@ because the comma is a separator for this option.
 @end itemize
 
 @node Windows Specific Add-Ons,,Mixed-Language Programming on Windows,Microsoft Windows Topics
-@anchor{gnat_ugn/platform_specific_information win32-specific-addons}@anchor{20d}@anchor{gnat_ugn/platform_specific_information windows-specific-add-ons}@anchor{20e}
+@anchor{gnat_ugn/platform_specific_information win32-specific-addons}@anchor{20f}@anchor{gnat_ugn/platform_specific_information windows-specific-add-ons}@anchor{210}
 @subsection Windows Specific Add-Ons
 
 
@@ -25310,7 +25362,7 @@ This section describes the Windows specific add-ons.
 @end menu
 
 @node Win32Ada,wPOSIX,,Windows Specific Add-Ons
-@anchor{gnat_ugn/platform_specific_information id42}@anchor{20f}@anchor{gnat_ugn/platform_specific_information win32ada}@anchor{210}
+@anchor{gnat_ugn/platform_specific_information id42}@anchor{211}@anchor{gnat_ugn/platform_specific_information win32ada}@anchor{212}
 @subsubsection Win32Ada
 
 
@@ -25341,7 +25393,7 @@ gprbuild p.gpr
 @end quotation
 
 @node wPOSIX,,Win32Ada,Windows Specific Add-Ons
-@anchor{gnat_ugn/platform_specific_information id43}@anchor{211}@anchor{gnat_ugn/platform_specific_information wposix}@anchor{212}
+@anchor{gnat_ugn/platform_specific_information id43}@anchor{213}@anchor{gnat_ugn/platform_specific_information wposix}@anchor{214}
 @subsubsection wPOSIX
 
 
@@ -25374,7 +25426,7 @@ gprbuild p.gpr
 @end quotation
 
 @node Mac OS Topics,,Microsoft Windows Topics,Platform-Specific Information
-@anchor{gnat_ugn/platform_specific_information id44}@anchor{213}@anchor{gnat_ugn/platform_specific_information mac-os-topics}@anchor{214}
+@anchor{gnat_ugn/platform_specific_information id44}@anchor{215}@anchor{gnat_ugn/platform_specific_information mac-os-topics}@anchor{216}
 @section Mac OS Topics
 
 
@@ -25389,7 +25441,7 @@ platform.
 @end menu
 
 @node Codesigning the Debugger,,,Mac OS Topics
-@anchor{gnat_ugn/platform_specific_information codesigning-the-debugger}@anchor{215}
+@anchor{gnat_ugn/platform_specific_information codesigning-the-debugger}@anchor{217}
 @subsection Codesigning the Debugger
 
 
@@ -25470,7 +25522,7 @@ the location where you installed GNAT.  Also, be sure that users are
 in the Unix group @code{_developer}.
 
 @node Example of Binder Output File,Elaboration Order Handling in GNAT,Platform-Specific Information,Top
-@anchor{gnat_ugn/example_of_binder_output doc}@anchor{216}@anchor{gnat_ugn/example_of_binder_output example-of-binder-output-file}@anchor{e}@anchor{gnat_ugn/example_of_binder_output id1}@anchor{217}
+@anchor{gnat_ugn/example_of_binder_output doc}@anchor{218}@anchor{gnat_ugn/example_of_binder_output example-of-binder-output-file}@anchor{e}@anchor{gnat_ugn/example_of_binder_output id1}@anchor{219}
 @chapter Example of Binder Output File
 
 
@@ -26222,7 +26274,7 @@ elaboration code in your own application).
 @c -- Example: A |withing| unit has a |with| clause, it |withs| a |withed| unit
 
 @node Elaboration Order Handling in GNAT,Inline Assembler,Example of Binder Output File,Top
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat doc}@anchor{218}@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-order-handling-in-gnat}@anchor{f}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id1}@anchor{219}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat doc}@anchor{21a}@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-order-handling-in-gnat}@anchor{f}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id1}@anchor{21b}
 @chapter Elaboration Order Handling in GNAT
 
 
@@ -26252,7 +26304,7 @@ GNAT, either automatically or with explicit programming features.
 @end menu
 
 @node Elaboration Code,Elaboration Order,,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-code}@anchor{21a}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id2}@anchor{21b}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-code}@anchor{21c}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id2}@anchor{21d}
 @section Elaboration Code
 
 
@@ -26400,7 +26452,7 @@ elaborated.
 @end itemize
 
 @node Elaboration Order,Checking the Elaboration Order,Elaboration Code,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-order}@anchor{21c}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id3}@anchor{21d}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-order}@anchor{21e}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id3}@anchor{21f}
 @section Elaboration Order
 
 
@@ -26569,7 +26621,7 @@ however a compiler may not always find such an order due to complications with
 respect to control and data flow.
 
 @node Checking the Elaboration Order,Controlling the Elaboration Order in Ada,Elaboration Order,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat checking-the-elaboration-order}@anchor{21e}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id4}@anchor{21f}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat checking-the-elaboration-order}@anchor{220}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id4}@anchor{221}
 @section Checking the Elaboration Order
 
 
@@ -26630,7 +26682,7 @@ order.
 @end itemize
 
 @node Controlling the Elaboration Order in Ada,Controlling the Elaboration Order in GNAT,Checking the Elaboration Order,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat controlling-the-elaboration-order-in-ada}@anchor{220}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id5}@anchor{221}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat controlling-the-elaboration-order-in-ada}@anchor{222}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id5}@anchor{223}
 @section Controlling the Elaboration Order in Ada
 
 
@@ -26958,7 +27010,7 @@ is that the program continues to stay in the last state (one or more correct
 orders exist) even if maintenance changes the bodies of targets.
 
 @node Controlling the Elaboration Order in GNAT,Mixing Elaboration Models,Controlling the Elaboration Order in Ada,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat controlling-the-elaboration-order-in-gnat}@anchor{222}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id6}@anchor{223}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat controlling-the-elaboration-order-in-gnat}@anchor{224}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id6}@anchor{225}
 @section Controlling the Elaboration Order in GNAT
 
 
@@ -27088,7 +27140,7 @@ The dynamic, legacy, and static models can be relaxed using compiler switch
 may not diagnose certain elaboration issues or install run-time checks.
 
 @node Mixing Elaboration Models,ABE Diagnostics,Controlling the Elaboration Order in GNAT,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat id7}@anchor{224}@anchor{gnat_ugn/elaboration_order_handling_in_gnat mixing-elaboration-models}@anchor{225}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat id7}@anchor{226}@anchor{gnat_ugn/elaboration_order_handling_in_gnat mixing-elaboration-models}@anchor{227}
 @section Mixing Elaboration Models
 
 
@@ -27135,7 +27187,7 @@ warning:   "y.ads" which has static elaboration checks
 The warnings can be suppressed by binder switch @code{-ws}.
 
 @node ABE Diagnostics,SPARK Diagnostics,Mixing Elaboration Models,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat abe-diagnostics}@anchor{226}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id8}@anchor{227}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat abe-diagnostics}@anchor{228}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id8}@anchor{229}
 @section ABE Diagnostics
 
 
@@ -27242,7 +27294,7 @@ declaration @code{Safe} because the body of function @code{ABE} has already been
 elaborated at that point.
 
 @node SPARK Diagnostics,Elaboration Circularities,ABE Diagnostics,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat id9}@anchor{228}@anchor{gnat_ugn/elaboration_order_handling_in_gnat spark-diagnostics}@anchor{229}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat id9}@anchor{22a}@anchor{gnat_ugn/elaboration_order_handling_in_gnat spark-diagnostics}@anchor{22b}
 @section SPARK Diagnostics
 
 
@@ -27268,7 +27320,7 @@ rules.
 @end quotation
 
 @node Elaboration Circularities,Resolving Elaboration Circularities,SPARK Diagnostics,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-circularities}@anchor{22a}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id10}@anchor{22b}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-circularities}@anchor{22c}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id10}@anchor{22d}
 @section Elaboration Circularities
 
 
@@ -27368,7 +27420,7 @@ This section enumerates various tactics for eliminating the circularity.
 @end itemize
 
 @node Resolving Elaboration Circularities,Elaboration-related Compiler Switches,Elaboration Circularities,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat id11}@anchor{22c}@anchor{gnat_ugn/elaboration_order_handling_in_gnat resolving-elaboration-circularities}@anchor{22d}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat id11}@anchor{22e}@anchor{gnat_ugn/elaboration_order_handling_in_gnat resolving-elaboration-circularities}@anchor{22f}
 @section Resolving Elaboration Circularities
 
 
@@ -27640,7 +27692,7 @@ Use the relaxed dynamic-elaboration model, with compiler switches
 @end itemize
 
 @node Elaboration-related Compiler Switches,Summary of Procedures for Elaboration Control,Resolving Elaboration Circularities,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-related-compiler-switches}@anchor{22e}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id12}@anchor{22f}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat elaboration-related-compiler-switches}@anchor{230}@anchor{gnat_ugn/elaboration_order_handling_in_gnat id12}@anchor{231}
 @section Elaboration-related Compiler Switches
 
 
@@ -27821,7 +27873,7 @@ checks. The example above will still fail at run time with an ABE.
 @end table
 
 @node Summary of Procedures for Elaboration Control,Inspecting the Chosen Elaboration Order,Elaboration-related Compiler Switches,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat id13}@anchor{230}@anchor{gnat_ugn/elaboration_order_handling_in_gnat summary-of-procedures-for-elaboration-control}@anchor{231}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat id13}@anchor{232}@anchor{gnat_ugn/elaboration_order_handling_in_gnat summary-of-procedures-for-elaboration-control}@anchor{233}
 @section Summary of Procedures for Elaboration Control
 
 
@@ -27879,7 +27931,7 @@ Use the relaxed dynamic elaboration model, with compiler switches
 @end itemize
 
 @node Inspecting the Chosen Elaboration Order,,Summary of Procedures for Elaboration Control,Elaboration Order Handling in GNAT
-@anchor{gnat_ugn/elaboration_order_handling_in_gnat id14}@anchor{232}@anchor{gnat_ugn/elaboration_order_handling_in_gnat inspecting-the-chosen-elaboration-order}@anchor{233}
+@anchor{gnat_ugn/elaboration_order_handling_in_gnat id14}@anchor{234}@anchor{gnat_ugn/elaboration_order_handling_in_gnat inspecting-the-chosen-elaboration-order}@anchor{235}
 @section Inspecting the Chosen Elaboration Order
 
 
@@ -28022,7 +28074,7 @@ gdbstr (body)
 @end quotation
 
 @node Inline Assembler,GNU Free Documentation License,Elaboration Order Handling in GNAT,Top
-@anchor{gnat_ugn/inline_assembler doc}@anchor{234}@anchor{gnat_ugn/inline_assembler id1}@anchor{235}@anchor{gnat_ugn/inline_assembler inline-assembler}@anchor{10}
+@anchor{gnat_ugn/inline_assembler doc}@anchor{236}@anchor{gnat_ugn/inline_assembler id1}@anchor{237}@anchor{gnat_ugn/inline_assembler inline-assembler}@anchor{10}
 @chapter Inline Assembler
 
 
@@ -28081,7 +28133,7 @@ and with assembly language programming.
 @end menu
 
 @node Basic Assembler Syntax,A Simple Example of Inline Assembler,,Inline Assembler
-@anchor{gnat_ugn/inline_assembler basic-assembler-syntax}@anchor{236}@anchor{gnat_ugn/inline_assembler id2}@anchor{237}
+@anchor{gnat_ugn/inline_assembler basic-assembler-syntax}@anchor{238}@anchor{gnat_ugn/inline_assembler id2}@anchor{239}
 @section Basic Assembler Syntax
 
 
@@ -28197,7 +28249,7 @@ Intel: Destination first; for example @code{mov eax, 4}@w{ }
 
 
 @node A Simple Example of Inline Assembler,Output Variables in Inline Assembler,Basic Assembler Syntax,Inline Assembler
-@anchor{gnat_ugn/inline_assembler a-simple-example-of-inline-assembler}@anchor{238}@anchor{gnat_ugn/inline_assembler id3}@anchor{239}
+@anchor{gnat_ugn/inline_assembler a-simple-example-of-inline-assembler}@anchor{23a}@anchor{gnat_ugn/inline_assembler id3}@anchor{23b}
 @section A Simple Example of Inline Assembler
 
 
@@ -28346,7 +28398,7 @@ If there are no errors, @code{as} will generate an object file
 @code{nothing.out}.
 
 @node Output Variables in Inline Assembler,Input Variables in Inline Assembler,A Simple Example of Inline Assembler,Inline Assembler
-@anchor{gnat_ugn/inline_assembler id4}@anchor{23a}@anchor{gnat_ugn/inline_assembler output-variables-in-inline-assembler}@anchor{23b}
+@anchor{gnat_ugn/inline_assembler id4}@anchor{23c}@anchor{gnat_ugn/inline_assembler output-variables-in-inline-assembler}@anchor{23d}
 @section Output Variables in Inline Assembler
 
 
@@ -28713,7 +28765,7 @@ end Get_Flags_3;
 @end quotation
 
 @node Input Variables in Inline Assembler,Inlining Inline Assembler Code,Output Variables in Inline Assembler,Inline Assembler
-@anchor{gnat_ugn/inline_assembler id5}@anchor{23c}@anchor{gnat_ugn/inline_assembler input-variables-in-inline-assembler}@anchor{23d}
+@anchor{gnat_ugn/inline_assembler id5}@anchor{23e}@anchor{gnat_ugn/inline_assembler input-variables-in-inline-assembler}@anchor{23f}
 @section Input Variables in Inline Assembler
 
 
@@ -28802,7 +28854,7 @@ _increment__incr.1:
 @end quotation
 
 @node Inlining Inline Assembler Code,Other Asm Functionality,Input Variables in Inline Assembler,Inline Assembler
-@anchor{gnat_ugn/inline_assembler id6}@anchor{23e}@anchor{gnat_ugn/inline_assembler inlining-inline-assembler-code}@anchor{23f}
+@anchor{gnat_ugn/inline_assembler id6}@anchor{240}@anchor{gnat_ugn/inline_assembler inlining-inline-assembler-code}@anchor{241}
 @section Inlining Inline Assembler Code
 
 
@@ -28873,7 +28925,7 @@ movl %esi,%eax
 thus saving the overhead of stack frame setup and an out-of-line call.
 
 @node Other Asm Functionality,,Inlining Inline Assembler Code,Inline Assembler
-@anchor{gnat_ugn/inline_assembler id7}@anchor{240}@anchor{gnat_ugn/inline_assembler other-asm-functionality}@anchor{241}
+@anchor{gnat_ugn/inline_assembler id7}@anchor{242}@anchor{gnat_ugn/inline_assembler other-asm-functionality}@anchor{243}
 @section Other @code{Asm} Functionality
 
 
@@ -28888,7 +28940,7 @@ and @code{Volatile}, which inhibits unwanted optimizations.
 @end menu
 
 @node The Clobber Parameter,The Volatile Parameter,,Other Asm Functionality
-@anchor{gnat_ugn/inline_assembler id8}@anchor{242}@anchor{gnat_ugn/inline_assembler the-clobber-parameter}@anchor{243}
+@anchor{gnat_ugn/inline_assembler id8}@anchor{244}@anchor{gnat_ugn/inline_assembler the-clobber-parameter}@anchor{245}
 @subsection The @code{Clobber} Parameter
 
 
@@ -28952,7 +29004,7 @@ Use ‘register’ name @code{memory} if you changed a memory location
 @end itemize
 
 @node The Volatile Parameter,,The Clobber Parameter,Other Asm Functionality
-@anchor{gnat_ugn/inline_assembler id9}@anchor{244}@anchor{gnat_ugn/inline_assembler the-volatile-parameter}@anchor{245}
+@anchor{gnat_ugn/inline_assembler id9}@anchor{246}@anchor{gnat_ugn/inline_assembler the-volatile-parameter}@anchor{247}
 @subsection The @code{Volatile} Parameter
 
 
@@ -28988,7 +29040,7 @@ to @code{True} only if the compiler’s optimizations have created
 problems.
 
 @node GNU Free Documentation License,Index,Inline Assembler,Top
-@anchor{share/gnu_free_documentation_license doc}@anchor{246}@anchor{share/gnu_free_documentation_license gnu-fdl}@anchor{1}@anchor{share/gnu_free_documentation_license gnu-free-documentation-license}@anchor{247}
+@anchor{share/gnu_free_documentation_license doc}@anchor{248}@anchor{share/gnu_free_documentation_license gnu-fdl}@anchor{1}@anchor{share/gnu_free_documentation_license gnu-free-documentation-license}@anchor{249}
 @chapter GNU Free Documentation License
 
 
@@ -29476,8 +29528,8 @@ to permit their use in free software.
 
 @printindex ge
 
+@anchor{d1}@w{                              }
 @anchor{gnat_ugn/gnat_utility_programs switches-related-to-project-files}@w{                              }
-@anchor{cf}@w{                              }
 
 @c %**end of body
 @bye
diff --git a/gcc/ada/lib-load.adb b/gcc/ada/lib-load.adb
index d79ee43..72196b4 100644
--- a/gcc/ada/lib-load.adb
+++ b/gcc/ada/lib-load.adb
@@ -645,11 +645,16 @@ package body Lib.Load is
                   if Is_Predefined_File_Name (Fname) then
                      Error_Msg_Unit_1 := Uname_Actual;
                      Error_Msg
-                       ("$$ is not a language defined unit", Load_Msg_Sloc);
+                       ("$$ is not a language defined unit",
+                        Load_Msg_Sloc,
+                        Error_Node);
                   else
                      Error_Msg_File_1 := Fname;
                      Error_Msg_Unit_1 := Uname_Actual;
-                     Error_Msg ("file{ does not contain unit$", Load_Msg_Sloc);
+                     Error_Msg
+                       ("file{ does not contain unit$",
+                        Load_Msg_Sloc,
+                        Error_Node);
                   end if;
 
                   Write_Dependency_Chain;
@@ -697,7 +702,8 @@ package body Lib.Load is
             end if;
 
             if Present (Error_Node) then
-               Error_Msg ("circular unit dependency", Load_Msg_Sloc);
+               Error_Msg
+                 ("circular unit dependency", Load_Msg_Sloc, Error_Node);
                Write_Dependency_Chain;
             else
                Load_Stack.Decrement_Last;
@@ -798,11 +804,14 @@ package body Lib.Load is
             then
                Error_Msg_File_1 := Unit_File_Name (Corr_Body);
                Error_Msg
-                 ("cannot compile subprogram in file {!", Load_Msg_Sloc);
+                 ("cannot compile subprogram in file {!",
+                  Load_Msg_Sloc,
+                  Error_Node);
                Error_Msg_File_1 := Unit_File_Name (Unum);
                Error_Msg
                  ("\incorrect spec in file { must be removed first!",
-                  Load_Msg_Sloc);
+                  Load_Msg_Sloc,
+                  Error_Node);
                Unum := No_Unit;
                goto Done;
             end if;
@@ -879,15 +888,21 @@ package body Lib.Load is
 
                   Error_Msg_Unit_1 := Uname_Actual;
                   Error_Msg -- CODEFIX
-                    ("$$ is not a predefined library unit", Load_Msg_Sloc);
+                    ("$$ is not a predefined library unit",
+                     Load_Msg_Sloc,
+                     Error_Node);
 
                else
                   Error_Msg_File_1 := Fname;
 
                   if Src_Ind = No_Access_To_Source_File then
-                     Error_Msg ("no read access to file{", Load_Msg_Sloc);
+                     Error_Msg
+                       ("no read access to file{",
+                        Load_Msg_Sloc,
+                        Error_Node
+                        );
                   else
-                     Error_Msg ("file{ not found", Load_Msg_Sloc);
+                     Error_Msg ("file{ not found", Load_Msg_Sloc, Error_Node);
                   end if;
                end if;
 
diff --git a/gcc/ada/libgnarl/a-reatim.ads b/gcc/ada/libgnarl/a-reatim.ads
index c5009d2..a616d57 100644
--- a/gcc/ada/libgnarl/a-reatim.ads
+++ b/gcc/ada/libgnarl/a-reatim.ads
@@ -39,9 +39,9 @@ pragma Elaborate_All (System.Task_Primitives.Operations);
 package Ada.Real_Time with
   SPARK_Mode,
   Abstract_State => (Clock_Time with Synchronous),
-  Initializes    => Clock_Time
+  Initializes    => Clock_Time,
+  Always_Terminates
 is
-   pragma Annotate (GNATprove, Always_Return, Real_Time);
 
    pragma Compile_Time_Error
      (Duration'Size /= 64,
diff --git a/gcc/ada/libgnarl/s-mudido.ads b/gcc/ada/libgnarl/s-mudido.ads
index 06e48bd..cc97463 100644
--- a/gcc/ada/libgnarl/s-mudido.ads
+++ b/gcc/ada/libgnarl/s-mudido.ads
@@ -20,10 +20,6 @@ with Ada.Task_Identification;
 private with System.Tasking;
 
 package System.Multiprocessors.Dispatching_Domains is
-   --  pragma Preelaborate (Dispatching_Domains);
-   --  ??? According to AI 167 this unit should be preelaborate, but it cannot
-   --  be preelaborate because it depends on Ada.Real_Time which is not
-   --  preelaborate.
 
    Dispatching_Domain_Error : exception;
 
diff --git a/gcc/ada/libgnat/a-calfor.adb b/gcc/ada/libgnat/a-calfor.adb
index 3325e56..18f4e73 100644
--- a/gcc/ada/libgnat/a-calfor.adb
+++ b/gcc/ada/libgnat/a-calfor.adb
@@ -590,10 +590,6 @@ package body Ada.Calendar.Formatting is
       Leap_Second : Boolean := False;
       Time_Zone   : Time_Zones.Time_Offset := 0) return Time
    is
-      Adj_Year  : Year_Number  := Year;
-      Adj_Month : Month_Number := Month;
-      Adj_Day   : Day_Number   := Day;
-
       H  : constant Integer := 1;
       M  : constant Integer := 1;
       Se : constant Integer := 1;
@@ -612,32 +608,11 @@ package body Ada.Calendar.Formatting is
          raise Constraint_Error;
       end if;
 
-      --  A Seconds value of 86_400 denotes a new day. This case requires an
-      --  adjustment to the input values.
-
-      if Seconds = 86_400.0 then
-         if Day < Days_In_Month (Month)
-           or else (Is_Leap (Year)
-                      and then Month = 2)
-         then
-            Adj_Day := Day + 1;
-         else
-            Adj_Day := 1;
-
-            if Month < 12 then
-               Adj_Month := Month + 1;
-            else
-               Adj_Month := 1;
-               Adj_Year  := Year + 1;
-            end if;
-         end if;
-      end if;
-
       return
         Formatting_Operations.Time_Of
-          (Year         => Adj_Year,
-           Month        => Adj_Month,
-           Day          => Adj_Day,
+          (Year         => Year,
+           Month        => Month,
+           Day          => Day,
            Day_Secs     => Seconds,
            Hour         => H,
            Minute       => M,
diff --git a/gcc/ada/libgnat/a-chahan.ads b/gcc/ada/libgnat/a-chahan.ads
index 159cd70..89b2d68 100644
--- a/gcc/ada/libgnat/a-chahan.ads
+++ b/gcc/ada/libgnat/a-chahan.ads
@@ -40,14 +40,13 @@ pragma Assertion_Policy (Post => Ignore);
 
 with Ada.Characters.Latin_1;
 
-package Ada.Characters.Handling
-  with SPARK_Mode
+package Ada.Characters.Handling with
+  SPARK_Mode,
+  Always_Terminates
 is
    pragma Pure;
    --  In accordance with Ada 2005 AI-362
 
-   pragma Annotate (GNATprove, Always_Return, Handling);
-
    ----------------------------------------
    -- Character Classification Functions --
    ----------------------------------------
diff --git a/gcc/ada/libgnat/a-nbnbig.ads b/gcc/ada/libgnat/a-nbnbig.ads
index f83bf52..382a7b6 100644
--- a/gcc/ada/libgnat/a-nbnbig.ads
+++ b/gcc/ada/libgnat/a-nbnbig.ads
@@ -30,9 +30,9 @@ pragma Assertion_Policy (Ghost => Ignore);
 package Ada.Numerics.Big_Numbers.Big_Integers_Ghost with
    SPARK_Mode,
    Ghost,
-   Pure
+   Pure,
+   Always_Terminates
 is
-   pragma Annotate (GNATprove, Always_Return, Big_Integers_Ghost);
 
    type Big_Integer is private
      with Integer_Literal => From_Universal_Image;
diff --git a/gcc/ada/libgnat/a-nbnbin.ads b/gcc/ada/libgnat/a-nbnbin.ads
index ffb96d4..c4d74ee 100644
--- a/gcc/ada/libgnat/a-nbnbin.ads
+++ b/gcc/ada/libgnat/a-nbnbin.ads
@@ -18,10 +18,10 @@ with Ada.Strings.Text_Buffers; use Ada.Strings.Text_Buffers;
 private with Ada.Finalization;
 private with System;
 
-package Ada.Numerics.Big_Numbers.Big_Integers
-  with Preelaborate
+package Ada.Numerics.Big_Numbers.Big_Integers with
+  Preelaborate,
+  Always_Terminates
 is
-   pragma Annotate (GNATprove, Always_Return, Big_Integers);
 
    type Big_Integer is private
      with Integer_Literal => From_Universal_Image,
diff --git a/gcc/ada/libgnat/a-nbnbre.ads b/gcc/ada/libgnat/a-nbnbre.ads
index 350d049..d342eeb 100644
--- a/gcc/ada/libgnat/a-nbnbre.ads
+++ b/gcc/ada/libgnat/a-nbnbre.ads
@@ -17,10 +17,10 @@ with Ada.Numerics.Big_Numbers.Big_Integers;
 
 with Ada.Strings.Text_Buffers; use Ada.Strings.Text_Buffers;
 
-package Ada.Numerics.Big_Numbers.Big_Reals
-  with Preelaborate
+package Ada.Numerics.Big_Numbers.Big_Reals with
+  Preelaborate,
+  Always_Terminates
 is
-   pragma Annotate (GNATprove, Always_Return, Big_Reals);
 
    type Big_Real is private with
      Real_Literal => From_Universal_Image,
diff --git a/gcc/ada/libgnat/a-ngelfu.ads b/gcc/ada/libgnat/a-ngelfu.ads
index f6d6c96..444d1a3 100644
--- a/gcc/ada/libgnat/a-ngelfu.ads
+++ b/gcc/ada/libgnat/a-ngelfu.ads
@@ -37,10 +37,10 @@ generic
    type Float_Type is digits <>;
 
 package Ada.Numerics.Generic_Elementary_Functions with
-  SPARK_Mode => On
+  SPARK_Mode => On,
+  Always_Terminates
 is
    pragma Pure;
-   pragma Annotate (GNATprove, Always_Return, Generic_Elementary_Functions);
 
    --  Preconditions in this unit are meant for analysis only, not for run-time
    --  checking, so that the expected exceptions are raised when calling
diff --git a/gcc/ada/libgnat/a-nlelfu.ads b/gcc/ada/libgnat/a-nlelfu.ads
index b3afd1f..10b33e9 100644
--- a/gcc/ada/libgnat/a-nlelfu.ads
+++ b/gcc/ada/libgnat/a-nlelfu.ads
@@ -19,4 +19,3 @@ package Ada.Numerics.Long_Elementary_Functions is
   new Ada.Numerics.Generic_Elementary_Functions (Long_Float);
 
 pragma Pure (Long_Elementary_Functions);
-pragma Annotate (GNATprove, Always_Return, Long_Elementary_Functions);
diff --git a/gcc/ada/libgnat/a-nllefu.ads b/gcc/ada/libgnat/a-nllefu.ads
index e137c67..7089fc3 100644
--- a/gcc/ada/libgnat/a-nllefu.ads
+++ b/gcc/ada/libgnat/a-nllefu.ads
@@ -19,4 +19,3 @@ package Ada.Numerics.Long_Long_Elementary_Functions is
   new Ada.Numerics.Generic_Elementary_Functions (Long_Long_Float);
 
 pragma Pure (Long_Long_Elementary_Functions);
-pragma Annotate (GNATprove, Always_Return, Long_Long_Elementary_Functions);
diff --git a/gcc/ada/libgnat/a-nselfu.ads b/gcc/ada/libgnat/a-nselfu.ads
index 6797efd..10b04ac 100644
--- a/gcc/ada/libgnat/a-nselfu.ads
+++ b/gcc/ada/libgnat/a-nselfu.ads
@@ -19,4 +19,3 @@ package Ada.Numerics.Short_Elementary_Functions is
   new Ada.Numerics.Generic_Elementary_Functions (Short_Float);
 
 pragma Pure (Short_Elementary_Functions);
-pragma Annotate (GNATprove, Always_Return, Short_Elementary_Functions);
diff --git a/gcc/ada/libgnat/a-nuelfu.ads b/gcc/ada/libgnat/a-nuelfu.ads
index d4fe745..149939b 100644
--- a/gcc/ada/libgnat/a-nuelfu.ads
+++ b/gcc/ada/libgnat/a-nuelfu.ads
@@ -19,4 +19,3 @@ package Ada.Numerics.Elementary_Functions is
   new Ada.Numerics.Generic_Elementary_Functions (Float);
 
 pragma Pure (Elementary_Functions);
-pragma Annotate (GNATprove, Always_Return, Elementary_Functions);
diff --git a/gcc/ada/libgnat/a-strbou.ads b/gcc/ada/libgnat/a-strbou.ads
index 1e4a366..ea0cc3f 100644
--- a/gcc/ada/libgnat/a-strbou.ads
+++ b/gcc/ada/libgnat/a-strbou.ads
@@ -47,9 +47,11 @@ with Ada.Strings.Maps; use type Ada.Strings.Maps.Character_Mapping_Function;
 with Ada.Strings.Superbounded;
 with Ada.Strings.Search;
 
-package Ada.Strings.Bounded with SPARK_Mode is
+package Ada.Strings.Bounded with
+  SPARK_Mode,
+  Always_Terminates
+is
    pragma Preelaborate;
-   pragma Annotate (GNATprove, Always_Return, Bounded);
 
    generic
       Max : Positive;
@@ -57,7 +59,8 @@ package Ada.Strings.Bounded with SPARK_Mode is
 
    package Generic_Bounded_Length with SPARK_Mode,
      Initial_Condition => Length (Null_Bounded_String) = 0,
-     Abstract_State    => null
+     Abstract_State    => null,
+     Always_Terminates
    is
       --  Preconditions in this unit are meant for analysis only, not for
       --  run-time checking, so that the expected exceptions are raised. This
@@ -69,7 +72,6 @@ package Ada.Strings.Bounded with SPARK_Mode is
                                Post           => Ignore,
                                Contract_Cases => Ignore,
                                Ghost          => Ignore);
-      pragma Annotate (GNATprove, Always_Return, Generic_Bounded_Length);
 
       Max_Length : constant Positive := Max;
 
diff --git a/gcc/ada/libgnat/a-strfix.ads b/gcc/ada/libgnat/a-strfix.ads
index 0838d59..9d5e9d9 100644
--- a/gcc/ada/libgnat/a-strfix.ads
+++ b/gcc/ada/libgnat/a-strfix.ads
@@ -46,7 +46,10 @@ pragma Assertion_Policy (Pre            => Ignore,
 with Ada.Strings.Maps; use type Ada.Strings.Maps.Character_Mapping_Function;
 with Ada.Strings.Search;
 
-package Ada.Strings.Fixed with SPARK_Mode is
+package Ada.Strings.Fixed with
+  SPARK_Mode,
+  Always_Terminates
+is
    pragma Preelaborate;
 
    --------------------------------------------------------------
@@ -60,11 +63,9 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment  := Left;
       Pad     : Character  := Space)
    with
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases =>
+       (Length_Error => Target'Length'Old < Source'Length and Drop = Error);
    --  The Move procedure copies characters from Source to Target. If Source
    --  has the same length as Target, then the effect is to assign Source to
    --  Target. If Source is shorter than Target then:
@@ -169,8 +170,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
         others
         =>
           Index'Result = 0),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    pragma Ada_05 (Index);
 
    function Index
@@ -233,8 +233,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
         others
         =>
           Index'Result = 0),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    pragma Ada_05 (Index);
 
    --  Each Index function searches, starting from From, for a slice of
@@ -303,8 +302,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
         others
         =>
           Index'Result = 0),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
 
    function Index
      (Source  : String;
@@ -359,8 +357,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
         others
         =>
           Index'Result = 0),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
 
    --  If Going = Forward, returns:
    --
@@ -413,8 +410,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                        and then (J < Index'Result) = (Going = Forward)
                   then (Test = Inside)
                        /= Ada.Strings.Maps.Is_In (Source (J), Set)))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
 
    function Index
      (Source  : String;
@@ -470,8 +466,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                                 or else (J > From) = (Going = Forward))
                   then (Test = Inside)
                        /= Ada.Strings.Maps.Is_In (Source (J), Set)))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    pragma Ada_05 (Index);
    --  Index searches for the first or last occurrence of any of a set of
    --  characters (when Test=Inside), or any of the complement of a set of
@@ -531,8 +526,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                        and then (J = From or else (J > From)
                                 = (Going = Forward))
                   then Source (J) = ' '))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    pragma Ada_05 (Index_Non_Blank);
    --  Returns Index (Source, Maps.To_Set(Space), From, Outside, Going)
 
@@ -570,8 +564,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                        and then (J < Index_Non_Blank'Result)
                               = (Going = Forward)
                   then Source (J) = ' '))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    --  Returns Index (Source, Maps.To_Set(Space), Outside, Going)
 
    function Count
@@ -579,18 +572,16 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Pattern : String;
       Mapping : Maps.Character_Mapping := Maps.Identity) return Natural
    with
-     Pre      => Pattern'Length /= 0,
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Pre    => Pattern'Length /= 0,
+     Global => null;
 
    function Count
      (Source  : String;
       Pattern : String;
       Mapping : Maps.Character_Mapping_Function) return Natural
    with
-     Pre      => Pattern'Length /= 0 and then Mapping /= null,
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Pre    => Pattern'Length /= 0 and then Mapping /= null,
+     Global => null;
 
    --  Returns the maximum number of nonoverlapping slices of Source that match
    --  Pattern with respect to Mapping. If Pattern is the null string then
@@ -600,8 +591,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
      (Source : String;
       Set    : Maps.Character_Set) return Natural
    with
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
    --  Returns the number of occurrences in Source of characters that are in
    --  Set.
 
@@ -659,8 +649,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                then
                  (Test = Inside)
                  /= Ada.Strings.Maps.Is_In (Source (Last + 1), Set))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    pragma Ada_2012 (Find_Token);
    --  If Source is not the null string and From is not in Source'Range, then
    --  Index_Error is raised. Otherwise, First is set to the index of the first
@@ -722,8 +711,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                then
                  (Test = Inside)
                  /= Ada.Strings.Maps.Is_In (Source (Last + 1), Set))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    --  Equivalent to Find_Token (Source, Set, Source'First, Test, First, Last)
 
    ------------------------------------
@@ -752,8 +740,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
            (for all J in Source'Range =>
               Translate'Result (J - Source'First + 1)
               = Mapping (Source (J))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global => null;
    pragma Annotate (GNATprove, False_Positive,
                     "call via access-to-subprogram",
                     "function Mapping must always terminate");
@@ -779,8 +766,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
            (for all J in Source'Range =>
               Translate'Result (J - Source'First + 1)
               = Ada.Strings.Maps.Value (Mapping, Source (J))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global => null;
 
    --  Returns the string S whose length is Source'Length and such that S (I)
    --  is the character to which Mapping maps the corresponding element of
@@ -790,15 +776,14 @@ package Ada.Strings.Fixed with SPARK_Mode is
      (Source  : in out String;
       Mapping : Maps.Character_Mapping_Function)
    with
-     Pre      => Mapping /= null,
-     Post     =>
+     Pre    => Mapping /= null,
+     Post   =>
 
        --  Each character in Source after the call is the translation of the
        --  character at the same position before the call, through Mapping.
 
        (for all J in Source'Range => Source (J) = Mapping (Source'Old (J))),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
    pragma Annotate (GNATprove, False_Positive,
                     "call via access-to-subprogram",
                     "function Mapping must always terminate");
@@ -807,15 +792,14 @@ package Ada.Strings.Fixed with SPARK_Mode is
      (Source  : in out String;
       Mapping : Maps.Character_Mapping)
    with
-     Post     =>
+     Post   =>
 
        --  Each character in Source after the call is the translation of the
        --  character at the same position before the call, through Mapping.
 
        (for all J in Source'Range =>
           Source (J) = Ada.Strings.Maps.Value (Mapping, Source'Old (J))),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
 
    --  Equivalent to Source := Translate(Source, Mapping)
 
@@ -908,8 +892,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                   (Low - Source'First + By'Length + 1
                    .. Replace_Slice'Result'Last)
                 = Source (Low .. Source'Last))),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    --  If Low > Source'Last + 1, or High < Source'First - 1, then Index_Error
    --  is propagated. Otherwise:
    --
@@ -929,7 +912,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment  := Left;
       Pad     : Character  := Space)
    with
-     Pre      =>
+     Pre               =>
        Low - 1 <= Source'Last
          and then High >= Source'First - 1
          and then (if High >= Low
@@ -938,11 +921,8 @@ package Ada.Strings.Fixed with SPARK_Mode is
                            - By'Length
                            - Natural'Max (Source'Last - High, 0)
                    else Source'Length <= Natural'Last - By'Length),
-
-   --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Length_Error => Drop = Error);
    --  Equivalent to:
    --
    --    Move (Replace_Slice (Source, Low, High, By),
@@ -988,8 +968,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                 (Before - Source'First + New_Item'Length + 1
                  .. Insert'Result'Last)
               = Source (Before .. Source'Last)),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    --  Propagates Index_Error if Before is not in
    --  Source'First .. Source'Last + 1; otherwise, returns
    --  Source (Source'First .. Before - 1)
@@ -1001,14 +980,11 @@ package Ada.Strings.Fixed with SPARK_Mode is
       New_Item : String;
       Drop     : Truncation := Error)
    with
-     Pre      =>
+     Pre               =>
        Before - 1 in Source'First - 1 .. Source'Last
          and then Source'Length <= Natural'Last - New_Item'Length,
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Length_Error => Drop = Error);
    --  Equivalent to Move (Insert (Source, Before, New_Item), Source, Drop)
 
    function Overwrite
@@ -1057,8 +1033,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                 (Position - Source'First + New_Item'Length + 1
                  .. Overwrite'Result'Last)
               = Source (Position + New_Item'Length .. Source'Last)),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global   => null;
    --  Propagates Index_Error if Position is not in
    --  Source'First .. Source'Last + 1; otherwise, returns the string obtained
    --  from Source by consecutively replacing characters starting at Position
@@ -1072,16 +1047,13 @@ package Ada.Strings.Fixed with SPARK_Mode is
       New_Item : String;
       Drop     : Truncation := Right)
    with
-     Pre      =>
+     Pre               =>
        Position - 1 in Source'First - 1 .. Source'Last
          and then
            (if Position - Source'First >= Source'Length - New_Item'Length
             then Position - Source'First <= Natural'Last - New_Item'Length),
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Length_Error => Drop = Error);
    --  Equivalent to Move(Overwrite(Source, Position, New_Item), Source, Drop)
 
    function Delete
@@ -1129,8 +1101,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
         others          =>
           Delete'Result'Length = Source'Length
             and then Delete'Result = Source),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    --  If From <= Through, the returned string is
    --  Replace_Slice(Source, From, Through, ""); otherwise, it is Source with
    --  lower bound 1.
@@ -1142,14 +1113,10 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment := Left;
       Pad     : Character := Space)
    with
-     Pre      => (if From <= Through
+     Pre    => (if From <= Through
                   then (From in Source'Range
                           and then Through <= Source'Last)),
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global => null;
    --  Equivalent to:
    --
    --     Move (Delete (Source, From, Through),
@@ -1163,7 +1130,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
      (Source : String;
       Side   : Trim_End) return String
    with
-     Post     =>
+     Post   =>
 
        --  Lower bound of the returned string is 1
 
@@ -1188,8 +1155,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                     else Index_Non_Blank (Source, Backward));
                begin
                  Trim'Result = Source (Low .. High))),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
    --  Returns the string obtained by removing from Source all leading Space
    --  characters (if Side = Left), all trailing Space characters (if
    --  Side = Right), or all leading and trailing Space characters (if
@@ -1201,11 +1167,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment := Left;
       Pad     : Character := Space)
    with
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global => null;
    --  Equivalent to:
    --
    --     Move (Trim (Source, Side), Source, Justify=>Justify, Pad=>Pad).
@@ -1242,8 +1204,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                 Index (Source, Right, Outside, Backward);
             begin
               Trim'Result = Source (Low .. High))),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
    --  Returns the string obtained by removing from Source all leading
    --  characters in Left and all trailing characters in Right.
 
@@ -1254,11 +1215,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment := Strings.Left;
       Pad     : Character := Space)
    with
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global => null;
    --  Equivalent to:
    --
    --     Move (Trim (Source, Left, Right),
@@ -1295,8 +1252,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
             and then
               Head'Result (Source'Length + 1 .. Count)
               = [1 .. Count - Source'Length => Pad]),
-     Global         => null,
-     Annotate       => (GNATprove, Always_Return);
+     Global         => null;
    --  Returns a string of length Count. If Count <= Source'Length, the string
    --  comprises the first Count characters of Source. Otherwise, its contents
    --  are Source concatenated with Count - Source'Length Pad characters.
@@ -1307,11 +1263,8 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment := Left;
       Pad     : Character := Space)
    with
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Length_Error => Count > Source'Length'Old);
    --  Equivalent to:
    --
    --     Move (Head (Source, Count, Pad),
@@ -1360,8 +1313,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
                and then
                  Tail'Result (Count - Source'Length + 1 .. Tail'Result'Last)
                  = Source)),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global         => null;
    --  Returns a string of length Count. If Count <= Source'Length, the string
    --  comprises the last Count characters of Source. Otherwise, its contents
    --  are Count-Source'Length Pad characters concatenated with Source.
@@ -1372,11 +1324,8 @@ package Ada.Strings.Fixed with SPARK_Mode is
       Justify : Alignment := Left;
       Pad     : Character := Space)
    with
-
-     --  Incomplete contract
-
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Length_Error => Count > Source'Length'Old);
    --  Equivalent to:
    --
    --     Move (Tail (Source, Count, Pad),
@@ -1390,7 +1339,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
      (Left  : Natural;
       Right : Character) return String
    with
-     Post     =>
+     Post   =>
 
        --  Lower bound of the returned string is 1
 
@@ -1403,8 +1352,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
          --  All characters of the returned string are Right
 
          and then (for all C of "*"'Result => C = Right),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
 
    function "*"
      (Left  : Natural;
@@ -1427,8 +1375,7 @@ package Ada.Strings.Fixed with SPARK_Mode is
          and then
            (for all K in "*"'Result'Range =>
               "*"'Result (K) = Right (Right'First + (K - 1) mod Right'Length)),
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
 
    --  These functions replicate a character or string a specified number of
    --  times. The first function returns a string whose length is Left and each
diff --git a/gcc/ada/libgnat/a-strmap.ads b/gcc/ada/libgnat/a-strmap.ads
index 73dd3d9..a070da0 100644
--- a/gcc/ada/libgnat/a-strmap.ads
+++ b/gcc/ada/libgnat/a-strmap.ads
@@ -48,14 +48,13 @@ pragma Assertion_Policy (Pre   => Ignore,
 
 with Ada.Characters.Latin_1;
 
-package Ada.Strings.Maps
-  with SPARK_Mode
+package Ada.Strings.Maps with
+  SPARK_Mode,
+  Always_Terminates
 is
    pragma Pure;
    --  In accordance with Ada 2005 AI-362
 
-   pragma Annotate (GNATprove, Always_Return, Maps);
-
    --------------------------------
    -- Character Set Declarations --
    --------------------------------
diff --git a/gcc/ada/libgnat/a-strsea.ads b/gcc/ada/libgnat/a-strsea.ads
index 5651bdc..df1b342 100644
--- a/gcc/ada/libgnat/a-strsea.ads
+++ b/gcc/ada/libgnat/a-strsea.ads
@@ -50,9 +50,11 @@ pragma Assertion_Policy (Pre            => Ignore,
 
 with Ada.Strings.Maps; use type Ada.Strings.Maps.Character_Mapping_Function;
 
-package Ada.Strings.Search with SPARK_Mode is
+package Ada.Strings.Search with
+  SPARK_Mode,
+  Always_Terminates
+is
    pragma Preelaborate;
-   pragma Annotate (GNATprove, Always_Return, Search);
 
    --  The ghost function Match tells whether the slice of Source starting at
    --  From and of length Pattern'Length matches with Pattern with respect to
diff --git a/gcc/ada/libgnat/a-strsup.ads b/gcc/ada/libgnat/a-strsup.ads
index 2e0cd98..339cb17 100644
--- a/gcc/ada/libgnat/a-strsup.ads
+++ b/gcc/ada/libgnat/a-strsup.ads
@@ -51,9 +51,11 @@ with Ada.Strings.Maps; use type Ada.Strings.Maps.Character_Mapping_Function;
 with Ada.Strings.Search;
 with Ada.Strings.Text_Buffers;
 
-package Ada.Strings.Superbounded with SPARK_Mode is
+package Ada.Strings.Superbounded with
+  SPARK_Mode,
+  Always_Terminates
+is
    pragma Preelaborate;
-   pragma Annotate (GNATprove, Always_Return, Superbounded);
 
    --  Type Bounded_String in Ada.Strings.Bounded.Generic_Bounded_Length is
    --  derived from Super_String, with the constraint of the maximum length.
diff --git a/gcc/ada/libgnat/a-strunb.ads b/gcc/ada/libgnat/a-strunb.ads
index d3e88d0..be76ad2 100644
--- a/gcc/ada/libgnat/a-strunb.ads
+++ b/gcc/ada/libgnat/a-strunb.ads
@@ -54,10 +54,10 @@ private with Ada.Strings.Text_Buffers;
 
 package Ada.Strings.Unbounded with
   SPARK_Mode,
-  Initial_Condition => Length (Null_Unbounded_String) = 0
+  Initial_Condition => Length (Null_Unbounded_String) = 0,
+  Always_Terminates
 is
    pragma Preelaborate;
-   pragma Annotate (GNATprove, Always_Return, Unbounded);
 
    type Unbounded_String is private with
      Default_Initial_Condition => Length (Unbounded_String) = 0;
diff --git a/gcc/ada/libgnat/a-strunb__shared.ads b/gcc/ada/libgnat/a-strunb__shared.ads
index 3f5d56e..2da9dc7 100644
--- a/gcc/ada/libgnat/a-strunb__shared.ads
+++ b/gcc/ada/libgnat/a-strunb__shared.ads
@@ -83,10 +83,10 @@ private with System.Atomic_Counters;
 private with Ada.Strings.Text_Buffers;
 
 package Ada.Strings.Unbounded with
-  Initial_Condition => Length (Null_Unbounded_String) = 0
+  Initial_Condition => Length (Null_Unbounded_String) = 0,
+  Always_Terminates
 is
    pragma Preelaborate;
-   pragma Annotate (GNATprove, Always_Return, Unbounded);
 
    type Unbounded_String is private with
      Default_Initial_Condition => Length (Unbounded_String) = 0;
diff --git a/gcc/ada/libgnat/a-textio.ads b/gcc/ada/libgnat/a-textio.ads
index 9cedab6..ddbbd85 100644
--- a/gcc/ada/libgnat/a-textio.ads
+++ b/gcc/ada/libgnat/a-textio.ads
@@ -59,7 +59,8 @@ package Ada.Text_IO with
   SPARK_Mode,
   Abstract_State    => File_System,
   Initializes       => File_System,
-  Initial_Condition => Line_Length = 0 and Page_Length = 0
+  Initial_Condition => Line_Length = 0 and Page_Length = 0,
+  Always_Terminates
 is
    pragma Elaborate_Body;
 
@@ -101,15 +102,15 @@ is
       Name : String := "";
       Form : String := "")
    with
-     Pre      => not Is_Open (File),
-     Post     =>
+     Pre               => not Is_Open (File),
+     Post              =>
        Is_Open (File)
        and then Ada.Text_IO.Mode (File) = Mode
        and then (if Mode /= In_File
                    then (Line_Length (File) = 0
                          and then Page_Length (File) = 0)),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Name_Error | Use_Error => Standard.True);
 
    procedure Open
      (File : in out File_Type;
@@ -117,57 +118,56 @@ is
       Name : String;
       Form : String := "")
    with
-     Pre      => not Is_Open (File),
-     Post     =>
+     Pre               => not Is_Open (File),
+     Post              =>
       Is_Open (File)
       and then Ada.Text_IO.Mode (File) = Mode
       and then (if Mode /= In_File
                   then (Line_Length (File) = 0
                         and then Page_Length (File) = 0)),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Name_Error | Use_Error => Standard.True);
 
    procedure Close  (File : in out File_Type) with
-     Pre      => Is_Open (File),
-     Post     => not Is_Open (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Pre    => Is_Open (File),
+     Post   => not Is_Open (File),
+     Global => (In_Out => File_System);
 
    procedure Delete (File : in out File_Type) with
-     Pre      => Is_Open (File),
-     Post     => not Is_Open (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File),
+     Post              => not Is_Open (File),
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    procedure Reset  (File : in out File_Type; Mode : File_Mode) with
-     Pre      => Is_Open (File),
-     Post     =>
+     Pre               => Is_Open (File),
+     Post              =>
        Is_Open (File)
        and then Ada.Text_IO.Mode (File) = Mode
        and then (if Mode /= In_File
                    then (Line_Length (File) = 0
                          and then Page_Length (File) = 0)),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    procedure Reset  (File : in out File_Type) with
-     Pre      => Is_Open (File),
-     Post     =>
+     Pre               => Is_Open (File),
+     Post              =>
        Is_Open (File)
        and Mode (File)'Old = Mode (File)
        and (if Mode (File) /= In_File
                 then (Line_Length (File) = 0
                       and then Page_Length (File) = 0)),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    function Mode (File : File_Type) return File_Mode with
      Pre    => Is_Open (File),
      Global => null;
 
    function Name (File : File_Type) return String with
-     Pre    => Is_Open (File),
-     Global => null;
+     Pre        => Is_Open (File),
+     SPARK_Mode => Off;
 
    function Form (File : File_Type) return String with
      Pre    => Is_Open (File),
@@ -210,53 +210,51 @@ is
    --  an oversight, and was intended to be IN, see AI95-00057.
 
    procedure Flush (File : File_Type) with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre    => Is_Open (File) and then Mode (File) /= In_File,
+     Post   =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Flush with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    --------------------------------------------
    -- Specification of line and page lengths --
    --------------------------------------------
 
    procedure Set_Line_Length (File : File_Type; To : Count) with
-     Pre      => Is_Open (File)  and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File)  and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File) = To
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    procedure Set_Line_Length (To : Count) with
-     Post     =>
+     Post              =>
        Line_Length = To
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    procedure Set_Page_Length (File : File_Type; To : Count) with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Page_Length (File) = To
        and Line_Length (File)'Old = Line_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    procedure Set_Page_Length (To : Count) with
-     Post     =>
+     Post              =>
        Page_Length = To
        and Line_Length'Old = Line_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Use_Error => Standard.True);
 
    function Line_Length (File : File_Type) return Count with
      Pre    => Is_Open (File) and then Mode (File) /= In_File,
@@ -277,31 +275,29 @@ is
    ------------------------------------
 
    procedure New_Line (File : File_Type; Spacing : Positive_Count := 1) with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre    => Is_Open (File) and then Mode (File) /= In_File,
+     Post   =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure New_Line (Spacing : Positive_Count := 1) with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Skip_Line (File : File_Type; Spacing : Positive_Count := 1) with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Skip_Line (Spacing : Positive_Count := 1) with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    function End_Of_Line (File : File_Type) return Boolean with
      Pre    => Is_Open (File) and then Mode (File) = In_File,
@@ -311,31 +307,29 @@ is
      Global => (Input => File_System);
 
    procedure New_Page (File : File_Type) with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre    => Is_Open (File) and then Mode (File) /= In_File,
+     Post   =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure New_Page with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Skip_Page (File : File_Type) with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Skip_Page with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    function End_Of_Page (File : File_Type) return Boolean with
      Pre    => Is_Open (File) and then Mode (File) = In_File,
@@ -352,209 +346,201 @@ is
      Global => (Input => File_System);
 
    procedure Set_Col (File : File_Type;  To : Positive_Count) with
-     Pre            =>
+     Pre               =>
        Is_Open (File)
        and then (if Mode (File) /= In_File
                      then (Line_Length (File) = 0
                            or else To <= Line_Length (File))),
-     Contract_Cases =>
+     Contract_Cases    =>
        (Mode (File) /= In_File =>
               Line_Length (File)'Old = Line_Length (File)
               and Page_Length (File)'Old = Page_Length (File),
         others                 => True),
-     Global         => (In_Out => File_System),
-     Annotate       => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Set_Col (To : Positive_Count) with
-     Pre      => Line_Length = 0 or To <= Line_Length,
-     Post     =>
+     Pre               => Line_Length = 0 or To <= Line_Length,
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Set_Line (File : File_Type; To : Positive_Count) with
-     Pre            =>
+     Pre               =>
        Is_Open (File)
        and then (if Mode (File) /= In_File
                      then (Page_Length (File) = 0
                            or else To <= Page_Length (File))),
-     Contract_Cases =>
+     Contract_Cases    =>
        (Mode (File) /= In_File =>
               Line_Length (File)'Old = Line_Length (File)
               and Page_Length (File)'Old = Page_Length (File),
         others                 => True),
-     Global         => (In_Out => File_System),
-     Annotate       => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Set_Line (To : Positive_Count) with
-     Pre      => Page_Length = 0 or To <= Page_Length,
-     Post     =>
+     Pre               => Page_Length = 0 or To <= Page_Length,
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    function Col (File : File_Type) return Positive_Count with
-     Pre    => Is_Open (File),
-     Global => (Input => File_System);
+     SPARK_Mode => Off;
 
    function Col return Positive_Count with
-     Global => (Input => File_System);
+     SPARK_Mode => Off;
 
    function Line (File : File_Type) return Positive_Count with
-     Pre    => Is_Open (File),
-     Global => (Input => File_System);
+     SPARK_Mode => Off;
 
    function Line return Positive_Count with
-     Global => (Input => File_System);
+     SPARK_Mode => Off;
 
    function Page (File : File_Type) return Positive_Count with
-     Pre    => Is_Open (File),
-     Global => (Input => File_System);
+     SPARK_Mode => Off;
 
    function Page return Positive_Count with
-     Global => (Input => File_System);
+     SPARK_Mode => Off;
 
    ----------------------------
    -- Character Input-Output --
    ----------------------------
 
    procedure Get (File : File_Type; Item : out Character) with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Get (Item : out Character) with
-     Post   =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Put (File : File_Type; Item : Character) with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre    => Is_Open (File) and then Mode (File) /= In_File,
+     Post   =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Put (Item : Character) with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Look_Ahead
      (File        : File_Type;
       Item        : out Character;
       End_Of_Line : out Boolean)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (Input => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Pre    => Is_Open (File) and then Mode (File) = In_File,
+     Global => (Input => File_System);
 
    procedure Look_Ahead
      (Item        : out Character;
       End_Of_Line : out Boolean)
    with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (Input => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (Input => File_System);
 
    procedure Get_Immediate
      (File : File_Type;
       Item : out Character)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Get_Immediate
      (Item : out Character)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Get_Immediate
      (File      : File_Type;
       Item      : out Character;
       Available : out Boolean)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    procedure Get_Immediate
      (Item      : out Character;
       Available : out Boolean)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Standard.True);
 
    -------------------------
    -- String Input-Output --
    -------------------------
 
    procedure Get (File : File_Type; Item : out String) with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Item'Length'Old > 0);
 
    procedure Get (Item : out String) with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Item'Length'Old > 0);
 
    procedure Put (File : File_Type; Item : String) with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre    => Is_Open (File) and then Mode (File) /= In_File,
+     Post   =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Put (Item : String) with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Get_Line
      (File : File_Type;
       Item : out String;
       Last : out Natural)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Post     => (if Item'Length > 0 then Last in Item'First - 1 .. Item'Last
-               else Last = Item'First - 1),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Post              =>
+       (if Item'Length > 0 then Last in Item'First - 1 .. Item'Last
+        else Last = Item'First - 1),
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Item'Length'Old > 0);
 
    procedure Get_Line
      (Item : out String;
       Last : out Natural)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length
        and (if Item'Length > 0 then Last in Item'First - 1 .. Item'Last
             else Last = Item'First - 1),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (End_Error => Item'Length'Old > 0);
 
    function Get_Line (File : File_Type) return String with SPARK_Mode => Off;
    pragma Ada_05 (Get_Line);
@@ -566,21 +552,19 @@ is
      (File : File_Type;
       Item : String)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre    => Is_Open (File) and then Mode (File) /= In_File,
+     Post   =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    procedure Put_Line
      (Item : String)
    with
-     Post     =>
+     Post   =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Always_Return);
+     Global => (In_Out => File_System);
 
    ---------------------------------------
    -- Generic packages for Input-Output --
diff --git a/gcc/ada/libgnat/a-tideio.ads b/gcc/ada/libgnat/a-tideio.ads
index b62d251..7f8fa19 100644
--- a/gcc/ada/libgnat/a-tideio.ads
+++ b/gcc/ada/libgnat/a-tideio.ads
@@ -43,7 +43,9 @@
 private generic
    type Num is delta <> digits <>;
 
-package Ada.Text_IO.Decimal_IO is
+package Ada.Text_IO.Decimal_IO with
+  Always_Terminates
+is
 
    Default_Fore : Field := Num'Fore;
    Default_Aft  : Field := Num'Aft;
@@ -54,19 +56,19 @@ package Ada.Text_IO.Decimal_IO is
       Item  : out Num;
       Width : Field := 0)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Get
      (Item  : out Num;
       Width : Field := 0)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Put
      (File : File_Type;
@@ -75,12 +77,12 @@ package Ada.Text_IO.Decimal_IO is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length (File) /= 0);
 
    procedure Put
      (Item : Num;
@@ -88,11 +90,11 @@ package Ada.Text_IO.Decimal_IO is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Ada.Text_IO.Line_Length /= 0);
 
    procedure Get
      (From : String;
@@ -100,7 +102,7 @@ package Ada.Text_IO.Decimal_IO is
       Last : out Positive)
    with
      Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Exceptional_Cases => (Data_Error => Standard.True);
 
    procedure Put
      (To   : out String;
@@ -108,8 +110,8 @@ package Ada.Text_IO.Decimal_IO is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Layout_Error => Standard.True);
 
 private
    pragma Inline (Get);
diff --git a/gcc/ada/libgnat/a-tienio.ads b/gcc/ada/libgnat/a-tienio.ads
index aac90f7..e4cdaee 100644
--- a/gcc/ada/libgnat/a-tienio.ads
+++ b/gcc/ada/libgnat/a-tienio.ads
@@ -23,21 +23,24 @@
 private generic
    type Enum is (<>);
 
-package Ada.Text_IO.Enumeration_IO is
+package Ada.Text_IO.Enumeration_IO with
+  Always_Terminates
+is
 
    Default_Width : Field := 0;
    Default_Setting : Type_Set := Upper_Case;
 
    procedure Get (File : File_Type; Item : out Enum) with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
+
    procedure Get (Item : out Enum) with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Put
      (File  : File_Type;
@@ -45,38 +48,38 @@ package Ada.Text_IO.Enumeration_IO is
       Width : Field := Default_Width;
       Set   : Type_Set := Default_Setting)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length (File) /= 0);
 
    procedure Put
      (Item  : Enum;
       Width : Field := Default_Width;
       Set   : Type_Set := Default_Setting)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Ada.Text_IO.Line_Length /= 0);
 
    procedure Get
      (From : String;
       Item : out Enum;
       Last : out Positive)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Data_Error => Standard.True);
 
    procedure Put
      (To   : out String;
       Item : Enum;
       Set  : Type_Set := Default_Setting)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Layout_Error => Standard.True);
 
 end Ada.Text_IO.Enumeration_IO;
diff --git a/gcc/ada/libgnat/a-tifiio.ads b/gcc/ada/libgnat/a-tifiio.ads
index bbf8e90..0e3e71c 100644
--- a/gcc/ada/libgnat/a-tifiio.ads
+++ b/gcc/ada/libgnat/a-tifiio.ads
@@ -23,7 +23,10 @@
 private generic
    type Num is delta <>;
 
-package Ada.Text_IO.Fixed_IO with SPARK_Mode => On is
+package Ada.Text_IO.Fixed_IO with
+  SPARK_Mode => On,
+  Always_Terminates
+is
 
    Default_Fore : Field := Num'Fore;
    Default_Aft  : Field := Num'Aft;
@@ -34,19 +37,19 @@ package Ada.Text_IO.Fixed_IO with SPARK_Mode => On is
       Item  : out Num;
       Width : Field := 0)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Get
      (Item  : out Num;
       Width : Field := 0)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Put
      (File : File_Type;
@@ -55,12 +58,12 @@ package Ada.Text_IO.Fixed_IO with SPARK_Mode => On is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length (File) /= 0);
 
    procedure Put
      (Item : Num;
@@ -68,19 +71,19 @@ package Ada.Text_IO.Fixed_IO with SPARK_Mode => On is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Ada.Text_IO.Line_Length /= 0);
 
    procedure Get
      (From : String;
       Item : out Num;
       Last : out Positive)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Data_Error => Standard.True);
 
    procedure Put
      (To   : out String;
@@ -88,8 +91,8 @@ package Ada.Text_IO.Fixed_IO with SPARK_Mode => On is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Layout_Error => Standard.True);
 
 private
    pragma Inline (Get);
diff --git a/gcc/ada/libgnat/a-tiflio.ads b/gcc/ada/libgnat/a-tiflio.ads
index 82ff84b..fcfa76a 100644
--- a/gcc/ada/libgnat/a-tiflio.ads
+++ b/gcc/ada/libgnat/a-tiflio.ads
@@ -43,7 +43,10 @@
 private generic
    type Num is digits <>;
 
-package Ada.Text_IO.Float_IO with SPARK_Mode => On is
+package Ada.Text_IO.Float_IO with
+  SPARK_Mode => On,
+  Always_Terminates
+is
 
    Default_Fore : Field := 2;
    Default_Aft  : Field := Num'Digits - 1;
@@ -54,19 +57,19 @@ package Ada.Text_IO.Float_IO with SPARK_Mode => On is
       Item  : out Num;
       Width : Field := 0)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Get
      (Item  : out Num;
       Width : Field := 0)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Put
      (File : File_Type;
@@ -75,12 +78,12 @@ package Ada.Text_IO.Float_IO with SPARK_Mode => On is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length (File) /= 0);
 
    procedure Put
      (Item : Num;
@@ -88,19 +91,19 @@ package Ada.Text_IO.Float_IO with SPARK_Mode => On is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length /= 0);
 
    procedure Get
      (From : String;
       Item : out Num;
       Last : out Positive)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Data_Error => Standard.True);
 
    procedure Put
      (To   : out String;
@@ -108,8 +111,8 @@ package Ada.Text_IO.Float_IO with SPARK_Mode => On is
       Aft  : Field := Default_Aft;
       Exp  : Field := Default_Exp)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Layout_Error => Standard.True);
 
 private
    pragma Inline (Get);
diff --git a/gcc/ada/libgnat/a-tiinio.ads b/gcc/ada/libgnat/a-tiinio.ads
index 0299cc0..60f21cc 100644
--- a/gcc/ada/libgnat/a-tiinio.ads
+++ b/gcc/ada/libgnat/a-tiinio.ads
@@ -43,7 +43,9 @@
 private generic
    type Num is range <>;
 
-package Ada.Text_IO.Integer_IO is
+package Ada.Text_IO.Integer_IO with
+  Always_Terminates
+is
 
    Default_Width : Field := Num'Width;
    Default_Base  : Number_Base := 10;
@@ -53,19 +55,19 @@ package Ada.Text_IO.Integer_IO is
       Item  : out Num;
       Width : Field := 0)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Get
      (Item  : out Num;
       Width : Field := 0)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Put
      (File  : File_Type;
@@ -73,39 +75,39 @@ package Ada.Text_IO.Integer_IO is
       Width : Field := Default_Width;
       Base  : Number_Base := Default_Base)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length (File) /= 0);
 
    procedure Put
      (Item  : Num;
       Width : Field := Default_Width;
       Base  : Number_Base := Default_Base)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length /= 0);
 
    procedure Get
      (From : String;
       Item : out Num;
       Last : out Positive)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Data_Error => Standard.True);
 
    procedure Put
      (To   : out String;
       Item : Num;
       Base : Number_Base := Default_Base)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Layout_Error => Standard.True);
 
 private
    pragma Inline (Get);
diff --git a/gcc/ada/libgnat/a-timoio.ads b/gcc/ada/libgnat/a-timoio.ads
index c8554b8..40d91ed 100644
--- a/gcc/ada/libgnat/a-timoio.ads
+++ b/gcc/ada/libgnat/a-timoio.ads
@@ -43,7 +43,9 @@
 private generic
    type Num is mod <>;
 
-package Ada.Text_IO.Modular_IO is
+package Ada.Text_IO.Modular_IO with
+  Always_Terminates
+is
 
    Default_Width : Field := Num'Width;
    Default_Base  : Number_Base := 10;
@@ -53,19 +55,19 @@ package Ada.Text_IO.Modular_IO is
       Item  : out Num;
       Width : Field := 0)
    with
-     Pre      => Is_Open (File) and then Mode (File) = In_File,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Pre               => Is_Open (File) and then Mode (File) = In_File,
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Get
      (Item  : out Num;
       Width : Field := 0)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Data_Error | End_Error => Standard.True);
 
    procedure Put
      (File  : File_Type;
@@ -73,39 +75,39 @@ package Ada.Text_IO.Modular_IO is
       Width : Field := Default_Width;
       Base  : Number_Base := Default_Base)
    with
-     Pre      => Is_Open (File) and then Mode (File) /= In_File,
-     Post     =>
+     Pre               => Is_Open (File) and then Mode (File) /= In_File,
+     Post              =>
        Line_Length (File)'Old = Line_Length (File)
        and Page_Length (File)'Old = Page_Length (File),
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length (File) /= 0);
 
    procedure Put
      (Item  : Num;
       Width : Field := Default_Width;
       Base  : Number_Base := Default_Base)
    with
-     Post     =>
+     Post              =>
        Line_Length'Old = Line_Length
        and Page_Length'Old = Page_Length,
-     Global   => (In_Out => File_System),
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => (In_Out => File_System),
+     Exceptional_Cases => (Layout_Error => Line_Length /= 0);
 
    procedure Get
      (From : String;
       Item : out Num;
       Last : out Positive)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Data_Error => Standard.True);
 
    procedure Put
      (To   : out String;
       Item : Num;
       Base : Number_Base := Default_Base)
    with
-     Global   => null,
-     Annotate => (GNATprove, Might_Not_Return);
+     Global            => null,
+     Exceptional_Cases => (Layout_Error => Standard.True);
 
 private
    pragma Inline (Get);
diff --git a/gcc/ada/libgnat/g-souinf.ads b/gcc/ada/libgnat/g-souinf.ads
index b6598b5..ea65c73 100644
--- a/gcc/ada/libgnat/g-souinf.ads
+++ b/gcc/ada/libgnat/g-souinf.ads
@@ -41,7 +41,7 @@ package GNAT.Source_Info with
    Abstract_State =>
      (Source_Code_Information with
          External => (Async_Writers, Async_Readers)),
-   Annotate => (GNATprove, Always_Return)
+   Always_Terminates
 is
    pragma Preelaborate;
    --  Note that this unit is Preelaborate, but not Pure, that's because the
diff --git a/gcc/ada/libgnat/i-c.ads b/gcc/ada/libgnat/i-c.ads
index 70af56a..fe87fba 100644
--- a/gcc/ada/libgnat/i-c.ads
+++ b/gcc/ada/libgnat/i-c.ads
@@ -27,10 +27,11 @@ pragma Assertion_Policy (Pre            => Ignore,
 with System;
 with System.Parameters;
 
-package Interfaces.C
-  with SPARK_Mode, Pure
+package Interfaces.C with
+  SPARK_Mode,
+  Pure,
+  Always_Terminates
 is
-   pragma Annotate (GNATprove, Always_Return, C);
 
    --  Each of the types declared in Interfaces.C is C-compatible.
 
diff --git a/gcc/ada/libgnat/i-cheri.adb b/gcc/ada/libgnat/i-cheri.adb
new file mode 100644
index 0000000..174fdcc
--- /dev/null
+++ b/gcc/ada/libgnat/i-cheri.adb
@@ -0,0 +1,75 @@
+------------------------------------------------------------------------------
+--                                                                          --
+--                         GNAT COMPILER COMPONENTS                         --
+--                                                                          --
+--                       I N T E R F A C E S . C H E R I                    --
+--                                                                          --
+--                                  S p e c                                 --
+--                                                                          --
+--                        Copyright (C) 2023, AdaCore                       --
+--                                                                          --
+-- GNAT is free software;  you can  redistribute it  and/or modify it under --
+-- terms of the  GNU General Public License as published  by the Free Soft- --
+-- ware  Foundation;  either version 3,  or (at your option) any later ver- --
+-- sion.  GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE.                                     --
+--                                                                          --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception,   --
+-- version 3.1, as published by the Free Software Foundation.               --
+--                                                                          --
+-- You should have received a copy of the GNU General Public License and    --
+-- a copy of the GCC Runtime Library Exception along with this program;     --
+-- see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see    --
+-- <http://www.gnu.org/licenses/>.                                          --
+--                                                                          --
+-- GNAT was originally developed  by the GNAT team at  New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc.      --
+--                                                                          --
+------------------------------------------------------------------------------
+
+package body Interfaces.CHERI is
+
+   ----------------------------
+   -- Set_Address_And_Bounds --
+   ----------------------------
+
+   procedure Set_Address_And_Bounds
+     (Cap     : in out Capability;
+      Address :        System.Storage_Elements.Integer_Address;
+      Length  :        Bounds_Length)
+   is
+   begin
+      Cap := Capability_With_Address_And_Bounds (Cap, Address, Length);
+   end Set_Address_And_Bounds;
+
+   ----------------------------------
+   -- Set_Address_And_Exact_Bounds --
+   ----------------------------------
+
+   procedure Set_Address_And_Exact_Bounds
+     (Cap     : in out Capability;
+      Address :        System.Storage_Elements.Integer_Address;
+      Length  :        Bounds_Length)
+   is
+   begin
+      Cap := Capability_With_Address_And_Exact_Bounds (Cap, Address, Length);
+   end Set_Address_And_Exact_Bounds;
+
+   ----------------------
+   -- Align_Address_Up --
+   ----------------------
+
+   function Align_Address_Up
+     (Address : System.Storage_Elements.Integer_Address;
+      Length  : Bounds_Length)
+      return System.Storage_Elements.Integer_Address
+   is
+      Mask : constant System.Storage_Elements.Integer_Address :=
+        Representable_Alignment_Mask (Length);
+   begin
+      return (Address + (not Mask)) and Mask;
+   end Align_Address_Up;
+
+end Interfaces.CHERI;
diff --git a/gcc/ada/libgnat/i-cheri.ads b/gcc/ada/libgnat/i-cheri.ads
new file mode 100644
index 0000000..547b033
--- /dev/null
+++ b/gcc/ada/libgnat/i-cheri.ads
@@ -0,0 +1,470 @@
+------------------------------------------------------------------------------
+--                                                                          --
+--                         GNAT COMPILER COMPONENTS                         --
+--                                                                          --
+--                       I N T E R F A C E S . C H E R I                    --
+--                                                                          --
+--                                  S p e c                                 --
+--                                                                          --
+--                        Copyright (C) 2023, AdaCore                       --
+--                                                                          --
+-- GNAT is free software;  you can  redistribute it  and/or modify it under --
+-- terms of the  GNU General Public License as published  by the Free Soft- --
+-- ware  Foundation;  either version 3,  or (at your option) any later ver- --
+-- sion.  GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE.                                     --
+--                                                                          --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception,   --
+-- version 3.1, as published by the Free Software Foundation.               --
+--                                                                          --
+-- You should have received a copy of the GNU General Public License and    --
+-- a copy of the GCC Runtime Library Exception along with this program;     --
+-- see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see    --
+-- <http://www.gnu.org/licenses/>.                                          --
+--                                                                          --
+-- GNAT was originally developed  by the GNAT team at  New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc.      --
+--                                                                          --
+------------------------------------------------------------------------------
+
+--  This package provides bindings to CHERI intrinsics and some common
+--  operations on capabilities.
+
+with System;
+with System.Storage_Elements;
+
+package Interfaces.CHERI with
+  Preelaborate,
+  No_Elaboration_Code_All
+is
+
+   use type System.Storage_Elements.Integer_Address;
+
+   subtype Capability is System.Address;
+
+   type Bounds_Length is range 0 .. System.Memory_Size - 1 with
+     Size => System.Word_Size;
+
+   ----------------------------
+   -- Capability Permissions --
+   ----------------------------
+
+   type Permissions_Mask is mod System.Memory_Size with
+     Size => System.Word_Size;
+
+   Global                  : constant Permissions_Mask := 16#0001#;
+   Executive               : constant Permissions_Mask := 16#0002#;
+   Mutable_Load            : constant Permissions_Mask := 16#0040#;
+   Compartment_Id          : constant Permissions_Mask := 16#0080#;
+   Branch_Sealed_Pair      : constant Permissions_Mask := 16#0100#;
+   Access_System_Registers : constant Permissions_Mask := 16#0200#;
+   Permit_Unseal           : constant Permissions_Mask := 16#0400#;
+   Permit_Seal             : constant Permissions_Mask := 16#0800#;
+   Permit_Store_Local      : constant Permissions_Mask := 16#1000#;
+   Permit_Store_Capability : constant Permissions_Mask := 16#2000#;
+   Permit_Load_Capability  : constant Permissions_Mask := 16#4000#;
+   Permit_Execute          : constant Permissions_Mask := 16#8000#;
+   Permit_Store            : constant Permissions_Mask := 16#1_0000#;
+   Permit_Load             : constant Permissions_Mask := 16#2_0000#;
+
+   function "and"
+     (Cap  : Capability;
+      Mask : Permissions_Mask)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_perms_and";
+   --  Perform a bitwise-AND of a capability permissions and the specified
+   --  mask, returning the new capability.
+
+   function Get_Permissions (Cap : Capability) return Permissions_Mask with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_perms_get";
+   --  Get the permissions of a capability
+
+   function Clear_Permissions
+     (Cap  : Capability;
+      Mask : Permissions_Mask)
+      return Capability is
+        (Cap and not Mask);
+   --  Clear the specified permissions of a capability, returning the new
+   --  capability.
+
+   function Has_All_Permissions
+     (Cap         : Capability;
+      Permissions : Permissions_Mask)
+      return Boolean is
+        ((Get_Permissions (Cap) and Permissions) = Permissions);
+   --  Query whether all of the specified permission bits are set in a
+   --  capability's permissions flags.
+
+   -----------------------
+   -- Common Intrinsics --
+   -----------------------
+
+   function Capability_With_Address
+     (Cap  : Capability;
+      Addr : System.Storage_Elements.Integer_Address)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_address_set";
+   --  Return a new capability with the same bounds and permissions as Cap,
+   --  with the address set to Addr.
+
+   function Get_Address
+     (Cap : Capability)
+      return System.Storage_Elements.Integer_Address
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_address_get";
+   --  Get the address of a capability
+
+   procedure Set_Address
+     (Cap  : in out Capability;
+      Addr :        System.Storage_Elements.Integer_Address)
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_address_set";
+   --  Set the address of a capability
+
+   function Get_Base
+     (Cap : Capability)
+      return System.Storage_Elements.Integer_Address
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_base_get";
+   --  Get the lower bound of a capability
+
+   function Get_Offset (Cap : Capability) return Bounds_Length with
+     Import,  Convention => Intrinsic,
+     External_Name => "__builtin_cheri_offset_get";
+   --  Get the difference between the address and the lower bound of a
+   --  capability.
+
+   procedure Set_Offset
+     (Cap    : in out Capability;
+      Offset :        Bounds_Length)
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_offset_set";
+   --  Set the address relative to the lower bound of a capability
+
+   function Capability_With_Offset
+     (Cap   : Capability;
+      Value : Bounds_Length)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_offset_set";
+   --  Set the address relative to the lower bound of a capability, returning
+   --  the new capability.
+
+   function Increment_Offset
+     (Cap   : Capability;
+      Value : Bounds_Length)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_offset_increment";
+   --  Increment the address of a capability by the specified amount,
+   --  returning the new capability.
+
+   function Get_Length (Cap : Capability) return Bounds_Length with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_length_get";
+   --  Get the length of a capability's bounds
+
+   function Clear_Tag (Cap : Capability) return Capability with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_tag_clear";
+   --  Clear the capability validity tag, returning the new capability
+
+   function Get_Tag (Cap : Capability) return Boolean with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_tag_get";
+   --  Get the validty tag of a capability
+
+   function Is_Valid (Cap : Capability) return Boolean is (Get_Tag (Cap));
+   --  Check whether a capability is valid
+
+   function Is_Invalid (Cap : Capability) return Boolean is
+     (not Is_Valid (Cap));
+   --  Check whether a capability is invalid
+
+   function Is_Equal_Exact (A, B : Capability) return Boolean with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_equal_exact";
+   --  Check for bit equality between two capabilities
+
+   function Is_Subset (A, B : Capability) return Boolean with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_subset_test";
+   --  Returns True if capability A is a subset or equal to capability B
+
+   --------------------
+   -- Bounds Setting --
+   --------------------
+
+   function Capability_With_Bounds
+     (Cap    : Capability;
+      Length : Bounds_Length)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_bounds_set";
+   --  Narrow the bounds of a capability so that the lower bound is the
+   --  current address and the upper bound is suitable for the Length,
+   --  returning the new capability.
+   --
+   --  Note that the effective bounds of the returned capability may be wider
+   --  than the range Get_Address (Cap) .. Get_Address (Cap) + Length - 1 due
+   --  to capability compression, but they will always be a subset of the
+   --  original bounds.
+
+   function Capability_With_Exact_Bounds
+     (Cap    : Capability;
+      Length : Bounds_Length)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_bounds_set_exact";
+   --  Narrow the bounds of a capability so that the lower bound is the
+   --  current address and the upper bound is suitable for the Length,
+   --  returning the new capability.
+   --
+   --  This is similar to Capability_With_Bounds but will clear the capability
+   --  tag in the returned capability if the bounds cannot be set exactly, due
+   --  to capability compression.
+
+   function Capability_With_Address_And_Bounds
+     (Cap     : Capability;
+      Address : System.Storage_Elements.Integer_Address;
+      Length  : Bounds_Length)
+      return Capability is
+        (Capability_With_Bounds
+           (Capability_With_Address (Cap, Address), Length));
+   --  Set the address and narrow the bounds of the capability so that the
+   --  lower bound is Address and the upper bound is Address + Length,
+   --  returning the new capability.
+   --
+   --  Note that the effective bounds of the returned capability may be wider
+   --  than the range Address .. Address + Length - 1 due to capability
+   --  compression, but they will always be a subset of the original bounds.
+
+   function Capability_With_Address_And_Exact_Bounds
+     (Cap     : Capability;
+      Address : System.Storage_Elements.Integer_Address;
+      Length  : Bounds_Length)
+      return Capability is
+        (Capability_With_Exact_Bounds
+           (Capability_With_Address (Cap, Address), Length));
+   --  Set the address and narrow the bounds of the capability so that the
+   --  lower bound is Address and the upper bound is Address + Length,
+   --  returning the new capability.
+   --
+   --  This is similar to Capability_With_Address_And_Bounds but will clear the
+   --  capability tag in the returned capability if the bounds cannot be set
+   --  exactly, due to capability compression.
+
+   procedure Set_Bounds
+     (Cap    : in out Capability;
+      Length :        Bounds_Length)
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_bounds_set";
+   --  Narrow the bounds of a capability so that the lower bound is the
+   --  current address and the upper bound is suitable for the Length.
+   --
+   --  Note that the effective bounds of the output capability may be wider
+   --  than the range Get_Address (Cap) .. Get_Address (Cap) + Length - 1 due
+   --  to capability compression, but they will always be a subset of the
+   --  original bounds.
+
+   procedure Set_Exact_Bounds
+     (Cap    : in out Capability;
+      Length :        Bounds_Length)
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_bounds_set_exact";
+   --  Narrow the bounds of a capability so that the lower bound is the
+   --  current address and the upper bound is suitable for the Length.
+   --
+   --  This is similar to Set_Bounds but will clear the capability tag if the
+   --  bounds cannot be set exactly, due to capability compression.
+
+   procedure Set_Address_And_Bounds
+     (Cap     : in out Capability;
+      Address :        System.Storage_Elements.Integer_Address;
+      Length  :        Bounds_Length)
+   with
+     Inline_Always;
+   --  Set the address and narrow the bounds of the capability so that the
+   --  lower bound is Address and the upper bound is Address + Length.
+   --
+   --  Note that the effective bounds of the output capability may be wider
+   --  than the range Address .. Address + Length - 1 due to capability
+   --  compression, but they will always be a subset of the original bounds.
+
+   procedure Set_Address_And_Exact_Bounds
+     (Cap     : in out Capability;
+      Address :        System.Storage_Elements.Integer_Address;
+      Length  :        Bounds_Length)
+   with
+     Inline_Always;
+   --  Set the address and narrow the bounds of the capability so that the
+   --  lower bound is Address and the upper bound is Address + Length.
+   --
+   --  This is similar to Set_Address_And_Bounds but will clear the capability
+   --  tag if the bounds cannot be set exactly, due to capability compression.
+
+   function Representable_Length (Length : Bounds_Length) return Bounds_Length
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_round_representable_length";
+   --  Returns the length that a capability would have after using Set_Bounds
+   --  to set the Length (assuming appropriate alignment of the base).
+
+   function Representable_Alignment_Mask
+     (Length : Bounds_Length)
+      return System.Storage_Elements.Integer_Address
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_representable_alignment_mask";
+   --  Returns a bitmask that can be used to align an address downwards such
+   --  that it is sufficiently aligned to create a precisely bounded
+   --  capability.
+
+   function Align_Address_Down
+     (Address : System.Storage_Elements.Integer_Address;
+      Length  : Bounds_Length)
+      return System.Storage_Elements.Integer_Address is
+        (Address and Representable_Alignment_Mask (Length));
+   --  Align an address such that it is sufficiently aligned to create a
+   --  precisely bounded capability, rounding down if necessary.
+   --
+   --  Due to capability compression, the upper and lower bounds of a
+   --  capability must be aligned based on the length of the bounds to ensure
+   --  that the capability is representable. This function aligns an address
+   --  down to the next boundary if it is not already aligned.
+
+   function Capability_With_Address_Aligned_Down
+     (Cap    : Capability;
+      Length : Bounds_Length)
+      return Capability is
+        (Capability_With_Address
+          (Cap, Align_Address_Down (Get_Address (Cap), Length)));
+   --  Align a capability's address such that it is sufficiently aligned to
+   --  create a precisely bounded capability, rounding down if necessary.
+   --
+   --  Due to capability compression, the upper and lower bounds of a
+   --  capability must be aligned based on the length of the bounds to ensure
+   --  that the capability is representable. This function aligns an address
+   --  down to the next boundary if it is not already aligned.
+
+   function Align_Address_Up
+     (Address : System.Storage_Elements.Integer_Address;
+      Length  : Bounds_Length)
+      return System.Storage_Elements.Integer_Address
+   with
+     Inline;
+   --  Align an address such that it is sufficiently aligned to create a
+   --  precisely bounded capability, rounding upwards if necessary.
+   --
+   --  Due to capability compression, the upper and lower bounds of a
+   --  capability must be aligned based on the length of the bounds to ensure
+   --  that the capability is representable. This function aligns an address up
+   --  to the next boundary if it is not already aligned.
+
+   function Capability_With_Address_Aligned_Up
+     (Cap    : Capability;
+      Length : Bounds_Length)
+      return Capability is
+        (Capability_With_Address
+           (Cap, Align_Address_Up (Get_Address (Cap), Length)));
+   --  Align a capability's address such that it is sufficiently aligned to
+   --  create a precisely bounded capability, rounding upwards if necessary.
+   --
+   --  Due to capability compression, the upper and lower bounds of a
+   --  capability must be aligned based on the length of the bounds to ensure
+   --  that the capability is representable. This function aligns an address up
+   --  to the next boundary if it is not already aligned.
+
+   ------------------------------------------
+   -- Object Types, Sealing, and Unsealing --
+   ------------------------------------------
+
+   type Object_Type is
+     range -2**(System.Word_Size - 1) .. +2**(System.Word_Size - 1) - 1 with
+     Size => System.Word_Size;
+
+   Type_Unsealed : constant Object_Type := 0;
+   Type_Sentry   : constant Object_Type := 1;
+
+   function Get_Object_Type (Cap : Capability) return Object_Type with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_type_get";
+   --  Get the object type of a capability
+
+   function Is_Sealed (Cap : Capability) return Boolean with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_sealed_get";
+   --  Check whether a capability is sealed
+
+   function Is_Unsealed (Cap : Capability) return Boolean is
+     (not Is_Sealed (Cap));
+   --  Check whether a capability is unsealed
+
+   function Is_Sentry (Cap : Capability) return Boolean is
+     (Get_Object_Type (Cap) = Type_Sentry);
+   --  Check whether a capability is a sealed entry
+
+   function Create_Sentry (Cap : Capability) return Capability with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_seal_entry";
+   --  Create a sealed entry and return the new capability.
+
+   function Seal
+     (Cap         : Capability;
+      Sealing_Cap : Capability)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_seal";
+   --  Seal a capability with a sealing capability, by setting the object type
+   --  of the capability to the Sealing_Cap's value, returning the sealed
+   --  capability.
+
+   function Unseal
+     (Cap           : Capability;
+      Unsealing_Cap : Capability)
+      return Capability
+   with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_unseal";
+   --  Unseal a capability with an unsealing capability, by checking the object
+   --  type of the capability against the Sealing_Cap's value, returning the
+   --  unsealed capability.
+
+   -----------------------------------
+   -- Capability Register Accessors --
+   -----------------------------------
+
+   function Get_PCC return System.Address with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_program_counter_get";
+   --  Get the Program Counter Capablity (PCC)
+
+   function Get_DDC return System.Address with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_global_data_get";
+   --  Get the Default Data Capability (DDC)
+
+   function Get_CSP return System.Address with
+     Import, Convention => Intrinsic,
+     External_Name => "__builtin_cheri_stack_get";
+   --  Get the Capability Stack Pointer (CSP)
+
+end Interfaces.CHERI;
diff --git a/gcc/ada/libgnat/i-cstrin.ads b/gcc/ada/libgnat/i-cstrin.ads
index 49b1f13..e486f03 100644
--- a/gcc/ada/libgnat/i-cstrin.ads
+++ b/gcc/ada/libgnat/i-cstrin.ads
@@ -44,7 +44,8 @@ pragma Assertion_Policy (Pre => Ignore);
 package Interfaces.C.Strings with
   SPARK_Mode     => On,
   Abstract_State => (C_Memory),
-  Initializes    => (C_Memory)
+  Initializes    => (C_Memory),
+  Always_Terminates
 is
    pragma Preelaborate;
 
@@ -118,16 +119,11 @@ is
       Chars  : char_array;
       Check  : Boolean := True)
    with
-     Pre      =>
+     Pre    =>
        Item /= Null_Ptr
-         and then
-      (if Check then
-         Strlen (Item) <= size_t'Last - Offset
-           and then Strlen (Item) + Offset <= Chars'Length),
-     Global   => (In_Out => C_Memory),
-     Annotate => (GNATprove, Might_Not_Return);
-     --  Update may not return if Check is False and the null terminator
-     --  is overwritten or skipped with Offset.
+         and then Strlen (Item) <= size_t'Last - Offset
+         and then Strlen (Item) + Offset <= Chars'Length,
+     Global => (In_Out => C_Memory);
 
    procedure Update
      (Item   : chars_ptr;
@@ -135,16 +131,11 @@ is
       Str    : String;
       Check  : Boolean := True)
    with
-     Pre      =>
+     Pre    =>
        Item /= Null_Ptr
-         and then
-      (if Check then
-         Strlen (Item) <= size_t'Last - Offset
-           and then Strlen (Item) + Offset <= Str'Length),
-     Global   => (In_Out => C_Memory),
-     Annotate => (GNATprove, Might_Not_Return);
-     --  Update may not return if Check is False and the null terminator
-     --  is overwritten or skipped with Offset.
+         and then Strlen (Item) <= size_t'Last - Offset
+         and then Strlen (Item) + Offset <= Str'Length,
+     Global => (In_Out => C_Memory);
 
    Update_Error : exception;
 
diff --git a/gcc/ada/libgnat/interfac.ads b/gcc/ada/libgnat/interfac.ads
index edd3f36..bc37a8e 100644
--- a/gcc/ada/libgnat/interfac.ads
+++ b/gcc/ada/libgnat/interfac.ads
@@ -35,10 +35,11 @@
 
 --  This is the compiler version of this unit
 
-package Interfaces is
+package Interfaces with
+  Always_Terminates
+is
    pragma No_Elaboration_Code_All;
    pragma Pure;
-   pragma Annotate (GNATprove, Always_Return, Interfaces);
 
    --  All identifiers in this unit are implementation defined
 
diff --git a/gcc/ada/libgnat/interfac__2020.ads b/gcc/ada/libgnat/interfac__2020.ads
index 89557bf..70d82be 100644
--- a/gcc/ada/libgnat/interfac__2020.ads
+++ b/gcc/ada/libgnat/interfac__2020.ads
@@ -35,10 +35,11 @@
 
 --  This is the runtime version of this unit (not used during GNAT build)
 
-package Interfaces is
+package Interfaces with
+  Always_Terminates
+is
    pragma No_Elaboration_Code_All;
    pragma Pure;
-   pragma Annotate (GNATprove, Always_Return, Interfaces);
 
    --  All identifiers in this unit are implementation defined
 
diff --git a/gcc/ada/libgnat/s-aridou.adb b/gcc/ada/libgnat/s-aridou.adb
index 0414785..831590c 100644
--- a/gcc/ada/libgnat/s-aridou.adb
+++ b/gcc/ada/libgnat/s-aridou.adb
@@ -165,9 +165,8 @@ is
 
    function To_Neg_Int (A : Double_Uns) return Double_Int
    with
-     Annotate => (GNATprove, Always_Return),
-     Pre      => In_Double_Int_Range (-Big (A)),
-     Post     => Big (To_Neg_Int'Result) = -Big (A);
+     Pre  => In_Double_Int_Range (-Big (A)),
+     Post => Big (To_Neg_Int'Result) = -Big (A);
    --  Convert to negative integer equivalent. If the input is in the range
    --  0 .. 2 ** (Double_Size - 1), then the corresponding nonpositive signed
    --  integer (obtained by negating the given value) is returned, otherwise
@@ -175,9 +174,8 @@ is
 
    function To_Pos_Int (A : Double_Uns) return Double_Int
    with
-     Annotate => (GNATprove, Always_Return),
-     Pre      => In_Double_Int_Range (Big (A)),
-     Post     => Big (To_Pos_Int'Result) = Big (A);
+     Pre  => In_Double_Int_Range (Big (A)),
+     Post => Big (To_Pos_Int'Result) = Big (A);
    --  Convert to positive integer equivalent. If the input is in the range
    --  0 .. 2 ** (Double_Size - 1) - 1, then the corresponding non-negative
    --  signed integer is returned, otherwise constraint error is raised.
@@ -2582,8 +2580,19 @@ is
             pragma Assert
               (Big (Double_Uns (Hi (T2))) + Big (Double_Uns (Hi (T1))) =
                    Big (Double_Uns (D (1))));
+            pragma Assert
+              (Is_Mult_Decomposition (D1 => Big (Double_Uns (D (1))),
+                                      D2 => Big (Double_Uns (D (2))),
+                                      D3 => Big (Double_Uns (D (3))),
+                                      D4 => Big (Double_Uns (D (4)))));
          else
             D (1) := 0;
+
+            pragma Assert
+              (Is_Mult_Decomposition (D1 => Big (Double_Uns (D (1))),
+                                      D2 => Big (Double_Uns (D (2))),
+                                      D3 => Big (Double_Uns (D (3))),
+                                      D4 => Big (Double_Uns (D (4)))));
          end if;
 
       else
diff --git a/gcc/ada/libgnat/s-arit32.adb b/gcc/ada/libgnat/s-arit32.adb
index 219523b..d19b9e1 100644
--- a/gcc/ada/libgnat/s-arit32.adb
+++ b/gcc/ada/libgnat/s-arit32.adb
@@ -104,9 +104,8 @@ is
 
    function To_Neg_Int (A : Uns32) return Int32
    with
-     Annotate => (GNATprove, Always_Return),
-     Pre      => In_Int32_Range (-Big (A)),
-     Post     => Big (To_Neg_Int'Result) = -Big (A);
+     Pre  => In_Int32_Range (-Big (A)),
+     Post => Big (To_Neg_Int'Result) = -Big (A);
    --  Convert to negative integer equivalent. If the input is in the range
    --  0 .. 2**31, then the corresponding nonpositive signed integer (obtained
    --  by negating the given value) is returned, otherwise constraint error is
@@ -114,9 +113,8 @@ is
 
    function To_Pos_Int (A : Uns32) return Int32
    with
-     Annotate => (GNATprove, Always_Return),
-     Pre      => In_Int32_Range (Big (A)),
-     Post     => Big (To_Pos_Int'Result) = Big (A);
+     Pre  => In_Int32_Range (Big (A)),
+     Post => Big (To_Pos_Int'Result) = Big (A);
    --  Convert to positive integer equivalent. If the input is in the range
    --  0 .. 2**31 - 1, then the corresponding nonnegative signed integer is
    --  returned, otherwise constraint error is raised.
diff --git a/gcc/ada/libgnat/s-atacco.ads b/gcc/ada/libgnat/s-atacco.ads
index bd920cc..157ca52 100644
--- a/gcc/ada/libgnat/s-atacco.ads
+++ b/gcc/ada/libgnat/s-atacco.ads
@@ -55,11 +55,9 @@ package System.Address_To_Access_Conversions is
    --  of no strict aliasing.
 
    function To_Pointer (Value : Address)        return Object_Pointer with
-     Global   => null,
-     Annotate => (GNATprove, Always_Return);
+     Global => null;
    function To_Address (Value : Object_Pointer) return Address with
-     SPARK_Mode => Off,
-     Annotate => (GNATprove, Always_Return);
+     SPARK_Mode => Off;
 
    pragma Import (Intrinsic, To_Pointer);
    pragma Import (Intrinsic, To_Address);
diff --git a/gcc/ada/libgnat/s-spcuop.ads b/gcc/ada/libgnat/s-spcuop.ads
index daf550b6..642ded7 100644
--- a/gcc/ada/libgnat/s-spcuop.ads
+++ b/gcc/ada/libgnat/s-spcuop.ads
@@ -45,7 +45,7 @@
 package System.SPARK.Cut_Operations with
   SPARK_Mode,
   Pure,
-  Annotate => (GNATprove, Always_Return)
+  Always_Terminates
 is
 
    function By (Consequence, Premise : Boolean) return Boolean with
diff --git a/gcc/ada/libgnat/s-stoele.ads b/gcc/ada/libgnat/s-stoele.ads
index 7de150d..d5d7042 100644
--- a/gcc/ada/libgnat/s-stoele.ads
+++ b/gcc/ada/libgnat/s-stoele.ads
@@ -37,7 +37,9 @@
 --  extra declarations that can be introduced into System using Extend_System.
 --  It is a good idea to avoid use clauses for this package.
 
-package System.Storage_Elements is
+package System.Storage_Elements with
+  Always_Terminates
+is
    pragma Pure;
    --  Note that we take advantage of the implementation permission to make
    --  this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada 2005,
@@ -46,8 +48,6 @@ package System.Storage_Elements is
    pragma No_Elaboration_Code_All;
    --  Allow the use of that restriction in units that WITH this unit
 
-   pragma Annotate (GNATprove, Always_Return, Storage_Elements);
-
    type Storage_Offset is range -Memory_Size / 2 .. Memory_Size / 2 - 1;
 
    subtype Storage_Count is Storage_Offset range 0 .. Storage_Offset'Last;
diff --git a/gcc/ada/libgnat/s-vaispe.ads b/gcc/ada/libgnat/s-vaispe.ads
index 28efced..e74202d7 100644
--- a/gcc/ada/libgnat/s-vaispe.ads
+++ b/gcc/ada/libgnat/s-vaispe.ads
@@ -62,7 +62,7 @@ generic
 package System.Value_I_Spec with
    Ghost,
    SPARK_Mode,
-   Annotate => (GNATprove, Always_Return)
+   Always_Terminates
 is
    pragma Preelaborate;
    use all type Uns_Params.Uns_Option;
diff --git a/gcc/ada/libgnat/s-valuti.adb b/gcc/ada/libgnat/s-valuti.adb
index ec6fdb0..ee37c1a 100644
--- a/gcc/ada/libgnat/s-valuti.adb
+++ b/gcc/ada/libgnat/s-valuti.adb
@@ -123,6 +123,7 @@ is
       while F < L and then S (F) = ' ' loop
          pragma Loop_Invariant (F in S'First .. L - 1);
          pragma Loop_Invariant (for all J in S'First .. F => S (J) = ' ');
+         pragma Loop_Variant (Increases => F);
          F := F + 1;
       end loop;
 
@@ -139,6 +140,7 @@ is
       while S (L) = ' ' loop
          pragma Loop_Invariant (L in F + 1 .. S'Last);
          pragma Loop_Invariant (for all J in L .. S'Last => S (J) = ' ');
+         pragma Loop_Variant (Decreases => L);
          L := L - 1;
       end loop;
 
diff --git a/gcc/ada/libgnat/s-valuti.ads b/gcc/ada/libgnat/s-valuti.ads
index 1faa647..22d0612 100644
--- a/gcc/ada/libgnat/s-valuti.ads
+++ b/gcc/ada/libgnat/s-valuti.ads
@@ -51,7 +51,8 @@ is
 
    procedure Bad_Value (S : String)
    with
-     Depends => (null => S);
+     Depends => (null => S),
+     Exceptional_Cases => (others => Standard.False);
    pragma No_Return (Bad_Value);
    --  Raises constraint error with message: bad input for 'Value: "xxx"
 
diff --git a/gcc/ada/libgnat/s-vauspe.ads b/gcc/ada/libgnat/s-vauspe.ads
index 960ad8e..bdd97b5 100644
--- a/gcc/ada/libgnat/s-vauspe.ads
+++ b/gcc/ada/libgnat/s-vauspe.ads
@@ -53,7 +53,7 @@ generic
 package System.Value_U_Spec with
    Ghost,
    SPARK_Mode,
-   Annotate => (GNATprove, Always_Return)
+   Always_Terminates
 is
    pragma Preelaborate;
 
diff --git a/gcc/ada/opt.ads b/gcc/ada/opt.ads
index bcafba9..87399c8 100644
--- a/gcc/ada/opt.ads
+++ b/gcc/ada/opt.ads
@@ -1342,6 +1342,11 @@ package Opt is
    --  GNATPREP
    --  Set to True if -C switch used.
 
+   Reverse_Bit_Order_Threshold : Int := -1;
+   --  GNAT
+   --  Set to the threshold from which the RM 13.5.1(13.3/2) clause applies,
+   --  or -1 if the size of the largest machine scalar is to be used.
+
    RTS_Lib_Path_Name : String_Ptr := null;
    RTS_Src_Path_Name : String_Ptr := null;
    --  GNAT
diff --git a/gcc/ada/sem_ch12.adb b/gcc/ada/sem_ch12.adb
index f584a9f..d5280ce 100644
--- a/gcc/ada/sem_ch12.adb
+++ b/gcc/ada/sem_ch12.adb
@@ -660,6 +660,9 @@ package body Sem_Ch12 is
    --  the instance and the generic, so that the back-end can establish the
    --  proper order of elaboration.
 
+   function Get_Associated_Entity (Id : Entity_Id) return Entity_Id;
+   --  Similar to Get_Associated_Node below, but for entities
+
    function Get_Associated_Node (N : Node_Id) return Node_Id;
    --  In order to propagate semantic information back from the analyzed copy
    --  to the original generic, we maintain links between selected nodes in the
@@ -6119,6 +6122,25 @@ package body Sem_Ch12 is
          Restore_SPARK_Mode   (Saved_SM, Saved_SMP);
    end Analyze_Subprogram_Instantiation;
 
+   ---------------------------
+   -- Get_Associated_Entity --
+   ---------------------------
+
+   function Get_Associated_Entity (Id : Entity_Id) return Entity_Id is
+      Assoc : Entity_Id;
+
+   begin
+      Assoc := Associated_Entity (Id);
+
+      if Present (Assoc) then
+         while Present (Associated_Entity (Assoc)) loop
+            Assoc := Associated_Entity (Assoc);
+         end loop;
+      end if;
+
+      return Assoc;
+   end Get_Associated_Entity;
+
    -------------------------
    -- Get_Associated_Node --
    -------------------------
@@ -6964,8 +6986,63 @@ package body Sem_Ch12 is
      (Instance      : Entity_Id;
       Is_Formal_Box : Boolean)
    is
-      E      : Entity_Id;
+      Gen_Id : constant Entity_Id
+        := (if Is_Generic_Unit (Instance) then
+              Instance
+            elsif Is_Wrapper_Package (Instance) then
+              Generic_Parent
+                (Specification
+                  (Unit_Declaration_Node (Related_Instance (Instance))))
+            else
+              Generic_Parent (Package_Specification (Instance)));
+      --  The generic unit
+
+      Parent_Scope : constant Entity_Id := Scope (Gen_Id);
+      --  The enclosing scope of the generic unit
+
+      procedure Check_Actual_Type (Typ : Entity_Id);
+      --  If the type of the actual is a private type declared in the
+      --  enclosing scope of the generic unit, but not a derived type
+      --  of a private type declared elsewhere, the body of the generic
+      --  sees the full view of the type (because it has to appear in
+      --  the corresponding package body). If the type is private now,
+      --  exchange views to restore the proper visibility in the instance.
+
+      -----------------------
+      -- Check_Actual_Type --
+      -----------------------
+
+      procedure Check_Actual_Type (Typ : Entity_Id) is
+         Btyp : constant Entity_Id := Base_Type (Typ);
+
+      begin
+         --  The exchange is only needed if the generic is defined
+         --  within a package which is not a common ancestor of the
+         --  scope of the instance, and is not already in scope.
+
+         if Is_Private_Type (Btyp)
+           and then Scope (Btyp) = Parent_Scope
+           and then not Has_Private_Ancestor (Btyp)
+           and then Ekind (Parent_Scope) in E_Package | E_Generic_Package
+           and then Scope (Instance) /= Parent_Scope
+           and then not Is_Child_Unit (Gen_Id)
+         then
+            Switch_View (Btyp);
+
+            --  If the type of the entity is a subtype, it may also have
+            --  to be made visible, together with the base type of its
+            --  full view, after exchange.
+
+            if Is_Private_Type (Typ) then
+               Switch_View (Typ);
+               Switch_View (Base_Type (Typ));
+            end if;
+         end if;
+      end Check_Actual_Type;
+
       Astype : Entity_Id;
+      E      : Entity_Id;
+      Formal : Node_Id;
 
    begin
       E := First_Entity (Instance);
@@ -7083,60 +7160,22 @@ package body Sem_Ch12 is
             Set_Is_Hidden (E, False);
          end if;
 
-         if Ekind (E) = E_Constant then
+         --  Check directly the type of the actual objects
 
-            --  If the type of the actual is a private type declared in the
-            --  enclosing scope of the generic unit, the body of the generic
-            --  sees the full view of the type (because it has to appear in
-            --  the corresponding package body). If the type is private now,
-            --  exchange views to restore the proper visiblity in the instance.
+         if Ekind (E) in E_Constant | E_Variable then
+            Check_Actual_Type (Etype (E));
 
-            declare
-               Typ : constant Entity_Id := Base_Type (Etype (E));
-               --  The type of the actual
-
-               Gen_Id : Entity_Id;
-               --  The generic unit
-
-               Parent_Scope : Entity_Id;
-               --  The enclosing scope of the generic unit
-
-            begin
-               if Is_Wrapper_Package (Instance) then
-                  Gen_Id :=
-                    Generic_Parent
-                      (Specification
-                        (Unit_Declaration_Node
-                          (Related_Instance (Instance))));
-               else
-                  Gen_Id :=
-                    Generic_Parent (Package_Specification (Instance));
-               end if;
+         --  As well as the type of formal parameters of actual subprograms
 
-               Parent_Scope := Scope (Gen_Id);
-
-               --  The exchange is only needed if the generic is defined
-               --  within a package which is not a common ancestor of the
-               --  scope of the instance, and is not already in scope.
-
-               if Is_Private_Type (Typ)
-                 and then Scope (Typ) = Parent_Scope
-                 and then Scope (Instance) /= Parent_Scope
-                 and then Ekind (Parent_Scope) = E_Package
-                 and then not Is_Child_Unit (Gen_Id)
-               then
-                  Switch_View (Typ);
-
-                  --  If the type of the entity is a subtype, it may also have
-                  --  to be made visible, together with the base type of its
-                  --  full view, after exchange.
-
-                  if Is_Private_Type (Etype (E)) then
-                     Switch_View (Etype (E));
-                     Switch_View (Base_Type (Etype (E)));
-                  end if;
-               end if;
-            end;
+         elsif Ekind (E) in E_Function | E_Procedure
+           and then Is_Generic_Actual_Subprogram (E)
+           and then Present (Alias (E))
+         then
+            Formal := First_Formal (Alias (E));
+            while Present (Formal) loop
+               Check_Actual_Type (Etype (Formal));
+               Next_Formal (Formal);
+            end loop;
          end if;
 
          Next_Entity (E);
@@ -7602,46 +7641,36 @@ package body Sem_Ch12 is
    ------------------------
 
    procedure Check_Private_View (N : Node_Id) is
-      T : constant Entity_Id := Etype (N);
-      BT : Entity_Id;
+      Typ : constant Entity_Id := Etype (N);
 
-   begin
-      --  Exchange views if the type was not private in the generic but is
-      --  private at the point of instantiation. Do not exchange views if
-      --  the scope of the type is in scope. This can happen if both generic
-      --  and instance are sibling units, or if type is defined in a parent.
-      --  In this case the visibility of the type will be correct for all
-      --  semantic checks.
+      procedure Check_Private_Type (T : Entity_Id; Private_View : Boolean);
+      --  Check that the available view of T matches Private_View and, if not,
+      --  switch the view of T or of its base type.
+
+      procedure Check_Private_Type (T : Entity_Id; Private_View : Boolean) is
+         BT : constant Entity_Id := Base_Type (T);
+
+      begin
+         --  If the full declaration was not visible in the generic, stop here
+
+         if Private_View then
+            return;
+         end if;
 
-      if Present (T) then
-         BT := Base_Type (T);
+         --  Exchange views if the type was not private in the generic but is
+         --  private at the point of instantiation. Do not exchange views if
+         --  the scope of the type is in scope. This can happen if both generic
+         --  and instance are sibling units, or if type is defined in a parent.
+         --  In this case the visibility of the type will be correct for all
+         --  semantic checks.
 
          if Is_Private_Type (T)
-           and then not Has_Private_View (N)
            and then Present (Full_View (T))
            and then not In_Open_Scopes (Scope (T))
          then
-            --  In the generic, the full declaration was visible
-
             Switch_View (T);
 
-         elsif Has_Private_View (N)
-           and then not Is_Private_Type (T)
-           and then not Has_Been_Exchanged (T)
-           and then (not In_Open_Scopes (Scope (T))
-                      or else Nkind (Parent (N)) = N_Subtype_Declaration)
-         then
-            --  In the generic, only the private declaration was visible
-
-            --  If the type appears in a subtype declaration, the subtype in
-            --  instance must have a view compatible with that of its parent,
-            --  which must be exchanged (see corresponding code in Restore_
-            --  Private_Views) so we make an exception to the open scope rule.
-
-            Prepend_Elmt (T, Exchanged_Views);
-            Exchange_Declarations (Etype (Get_Associated_Node (N)));
-
-         --  Finally, a non-private subtype may have a private base type, which
+         --  Finally, a nonprivate subtype may have a private base type, which
          --  must be exchanged for consistency. This can happen when a package
          --  body is instantiated, when the scope stack is empty but in fact
          --  the subtype and the base type are declared in an enclosing scope.
@@ -7653,15 +7682,46 @@ package body Sem_Ch12 is
          --  provision for that case in Switch_View).
 
          elsif not Is_Private_Type (T)
-           and then not Has_Private_View (N)
            and then Is_Private_Type (BT)
            and then Present (Full_View (BT))
-           and then not Is_Generic_Type (BT)
            and then not In_Open_Scopes (BT)
          then
             Prepend_Elmt (Full_View (BT), Exchanged_Views);
             Exchange_Declarations (BT);
          end if;
+      end Check_Private_Type;
+
+   begin
+      if Present (Typ) then
+         --  If the type appears in a subtype declaration, the subtype in
+         --  instance must have a view compatible with that of its parent,
+         --  which must be exchanged (see corresponding code in Restore_
+         --  Private_Views) so we make an exception to the open scope rule
+         --  implemented by Check_Private_Type above.
+
+         if Has_Private_View (N)
+           and then not Is_Private_Type (Typ)
+           and then not Has_Been_Exchanged (Typ)
+           and then (not In_Open_Scopes (Scope (Typ))
+                      or else Nkind (Parent (N)) = N_Subtype_Declaration)
+         then
+            --  In the generic, only the private declaration was visible
+
+            Prepend_Elmt (Typ, Exchanged_Views);
+            Exchange_Declarations (Etype (Get_Associated_Node (N)));
+
+         else
+            Check_Private_Type (Typ, Has_Private_View (N));
+
+            if Is_Access_Type (Typ) then
+               Check_Private_Type
+                 (Designated_Type (Typ), Has_Secondary_Private_View (N));
+
+            elsif Is_Array_Type (Typ) then
+               Check_Private_Type
+                 (Component_Type (Typ), Has_Secondary_Private_View (N));
+            end if;
+         end if;
       end if;
    end Check_Private_View;
 
@@ -8037,115 +8097,34 @@ package body Sem_Ch12 is
                      Set_Entity (New_N, Entity (Assoc));
                      Check_Private_View (N);
 
-                     --  Here we deal with a very peculiar case for which the
-                     --  Has_Private_View mechanism is not sufficient, because
-                     --  the reference to the type is implicit in the tree,
-                     --  that is to say, it's not referenced from a node but
-                     --  only from another type, namely through Component_Type.
-
-                     --    package P is
-
-                     --      type Pt is private;
-
-                     --      generic
-                     --        type Ft is array (Positive range <>) of Pt;
-                     --      package G is
-                     --        procedure Check (F1, F2 : Ft; Lt : Boolean);
-                     --      end G;
-
-                     --    private
-                     --      type Pt is new Boolean;
-                     --    end P;
-
-                     --    package body P is
-                     --      package body G is
-                     --        procedure Check (F1, F2 : Ft; Lt : Boolean) is
-                     --        begin
-                     --          if (F1 < F2) /= Lt then
-                     --            null;
-                     --          end if;
-                     --        end Check;
-                     --      end G;
-                     --    end P;
-
-                     --    type Arr is array (Positive range <>) of P.Pt;
-
-                     --    package Inst is new P.G (Arr);
-
-                     --  Pt is a global type for the generic package G and it
-                     --  is not referenced in its body, but only as component
-                     --  type of Ft, which is a local type. This means that no
-                     --  references to Pt or Ft are seen during the copy of the
-                     --  body, the only reference to Pt being seen is when the
-                     --  actuals are checked by Check_Generic_Actuals, but Pt
-                     --  is still private at this point. In the end, the views
-                     --  of Pt are not switched in the body and, therefore, the
-                     --  array comparison is rejected because the component is
-                     --  still private.
-
-                     --  Adding e.g. a dummy variable of type Pt in the body is
-                     --  sufficient to make everything work, so we generate an
-                     --  artificial reference to Pt on the fly and thus force
-                     --  the switching of views on the grounds that, if the
-                     --  comparison was accepted during the semantic analysis
-                     --  of the generic, this means that the component cannot
-                     --  have been private (see Sem_Type.Valid_Comparison_Arg).
-
-                     if Nkind (Assoc) in N_Op_Compare
-                       and then Present (Etype (Left_Opnd (Assoc)))
-                       and then Is_Array_Type (Etype (Left_Opnd (Assoc)))
-                       and then Present (Etype (Right_Opnd (Assoc)))
-                       and then Is_Array_Type (Etype (Right_Opnd (Assoc)))
+                     --  For the comparison and equality operators, the Etype
+                     --  of the operator does not provide any information so,
+                     --  if one of the operands is of a universal type, we need
+                     --  to manually restore the full view of private types.
+
+                     if Nkind (N) in N_Op_Eq
+                                   | N_Op_Ge
+                                   | N_Op_Gt
+                                   | N_Op_Le
+                                   | N_Op_Lt
+                                   | N_Op_Ne
                      then
-                        declare
-                           Ltyp : constant Entity_Id :=
-                                                     Etype (Left_Opnd (Assoc));
-                           Rtyp : constant Entity_Id :=
-                                                    Etype (Right_Opnd (Assoc));
-                        begin
-                           if Is_Private_Type (Component_Type (Ltyp)) then
-                              Check_Private_View
-                                (New_Occurrence_Of (Component_Type (Ltyp),
-                                 Sloc (N)));
-                           end if;
-                           if Is_Private_Type (Component_Type (Rtyp)) then
-                              Check_Private_View
-                                (New_Occurrence_Of (Component_Type (Rtyp),
-                                 Sloc (N)));
+                        if Yields_Universal_Type (Left_Opnd (Assoc)) then
+                           if Present (Etype (Right_Opnd (Assoc)))
+                             and then
+                               Is_Private_Type (Etype (Right_Opnd (Assoc)))
+                           then
+                              Switch_View (Etype (Right_Opnd (Assoc)));
                            end if;
-                        end;
-
-                     --  Here is a similar case, for the Designated_Type of an
-                     --  access type that is present as target type in a type
-                     --  conversion from another access type. In this case, if
-                     --  the base types of the designated types are different
-                     --  and the conversion was accepted during the semantic
-                     --  analysis of the generic, this means that the target
-                     --  type cannot have been private (see Valid_Conversion).
-
-                     elsif Nkind (Assoc) = N_Identifier
-                       and then Nkind (Parent (Assoc)) = N_Type_Conversion
-                       and then Subtype_Mark (Parent (Assoc)) = Assoc
-                       and then Present (Etype (Assoc))
-                       and then Is_Access_Type (Etype (Assoc))
-                       and then Present (Etype (Expression (Parent (Assoc))))
-                       and then
-                         Is_Access_Type (Etype (Expression (Parent (Assoc))))
-                     then
-                        declare
-                           Targ_Desig : constant Entity_Id :=
-                             Designated_Type (Etype (Assoc));
-                           Expr_Desig : constant Entity_Id :=
-                             Designated_Type
-                               (Etype (Expression (Parent (Assoc))));
-                        begin
-                           if Base_Type (Targ_Desig) /= Base_Type (Expr_Desig)
-                             and then Is_Private_Type (Targ_Desig)
+
+                        elsif Yields_Universal_Type (Right_Opnd (Assoc)) then
+                           if Present (Etype (Left_Opnd (Assoc)))
+                             and then
+                               Is_Private_Type (Etype (Left_Opnd (Assoc)))
                            then
-                              Check_Private_View
-                                (New_Occurrence_Of (Targ_Desig, Sloc (N)));
+                              Switch_View (Etype (Left_Opnd (Assoc)));
                            end if;
-                        end;
+                        end if;
                      end if;
 
                   --  The node is a reference to a global type and acts as the
@@ -8406,7 +8385,7 @@ package body Sem_Ch12 is
                --  install the full view (and that of its ancestors, if any).
 
                declare
-                  T   : Entity_Id := (Etype (Get_Associated_Node (New_N)));
+                  T   : Entity_Id := Etype (Get_Associated_Node (N));
                   Rt  : Entity_Id;
 
                begin
@@ -8492,6 +8471,32 @@ package body Sem_Ch12 is
             Copy_Descendants;
          end;
 
+      --  Iterator and loop parameter specifications do not have an identifier
+      --  denoting the index type, so we must locate it through the expression
+      --  to check whether the views are consistent.
+
+      elsif Nkind (N) in N_Iterator_Specification
+                       | N_Loop_Parameter_Specification
+         and then Instantiating
+      then
+         declare
+            Id : constant Entity_Id :=
+                   Get_Associated_Entity (Defining_Identifier (N));
+
+            Index_T : Entity_Id;
+
+         begin
+            if Present (Id) and then Present (Etype (Id)) then
+               Index_T := First_Subtype (Etype (Id));
+
+               if Present (Index_T) and then Is_Private_Type (Index_T) then
+                  Switch_View (Index_T);
+               end if;
+            end if;
+
+            Copy_Descendants;
+         end;
+
       --  For a proper body, we must catch the case of a proper body that
       --  replaces a stub. This represents the point at which a separate
       --  compilation unit, and hence template file, may be referenced, so we
@@ -14311,6 +14316,13 @@ package body Sem_Ch12 is
 
       if Is_Private_Type (Act_T) then
          Set_Has_Private_View (Subtype_Indication (Decl_Node));
+
+      elsif (Is_Access_Type (Act_T)
+              and then Is_Private_Type (Designated_Type (Act_T)))
+        or else (Is_Array_Type (Act_T)
+                  and then Is_Private_Type (Component_Type (Act_T)))
+      then
+         Set_Has_Secondary_Private_View (Subtype_Indication (Decl_Node));
       end if;
 
       --  In Ada 2012 the actual may be a limited view. Indicate that
@@ -16362,7 +16374,7 @@ package body Sem_Ch12 is
                   return
                     Is_Generic_Declaration_Or_Body
                       (Unit_Declaration_Node
-                        (Associated_Entity (Defining_Entity (Nod))));
+                        (Get_Associated_Entity (Defining_Entity (Nod))));
 
                --  Otherwise the generic unit being processed is not the top
                --  level template. It is safe to capture of global references
@@ -16561,8 +16573,10 @@ package body Sem_Ch12 is
                     and then Is_Global (Entity (Prefix (N2)))
                   then
                      Set_Associated_Node (N, Prefix (N2));
+                     Set_Global_Type (N, Prefix (N2));
 
                   elsif Nkind (Prefix (N2)) = N_Function_Call
+                    and then Is_Entity_Name (Name (Prefix (N2)))
                     and then Present (Entity (Name (Prefix (N2))))
                     and then Is_Global (Entity (Name (Prefix (N2))))
                   then
@@ -16573,6 +16587,9 @@ package body Sem_Ch12 is
                              Name =>
                                New_Occurrence_Of
                                  (Entity (Name (Prefix (N2))), Loc))));
+                     Set_Associated_Node
+                       (Name (Prefix (N)), Name (Prefix (N2)));
+                     Set_Global_Type (Name (Prefix (N)), Name (Prefix (N2)));
 
                   else
                      Set_Associated_Node (N, Empty);
@@ -16598,15 +16615,16 @@ package body Sem_Ch12 is
 
          procedure Save_References_In_Operator (N : Node_Id) is
          begin
+            N2 := Get_Associated_Node (N);
+
             --  The node did not undergo a transformation
 
-            if Nkind (N) = Nkind (Get_Associated_Node (N)) then
+            if Nkind (N) = Nkind (N2) then
                if Nkind (N) = N_Op_Concat then
-                  Set_Is_Component_Left_Opnd (N,
-                    Is_Component_Left_Opnd (Get_Associated_Node (N)));
-
-                  Set_Is_Component_Right_Opnd (N,
-                    Is_Component_Right_Opnd (Get_Associated_Node (N)));
+                  Set_Is_Component_Left_Opnd
+                    (N, Is_Component_Left_Opnd (N2));
+                  Set_Is_Component_Right_Opnd
+                    (N, Is_Component_Right_Opnd (N2));
                end if;
 
                Reset_Entity (N);
@@ -16616,8 +16634,6 @@ package body Sem_Ch12 is
             --  applicable.
 
             else
-               N2 := Get_Associated_Node (N);
-
                --  The operator resoved to a function call
 
                if Nkind (N2) = N_Function_Call then
@@ -16814,14 +16830,26 @@ package body Sem_Ch12 is
          --  type is already the full view (see below). Indicate that the
          --  original node has a private view.
 
-         if Entity (N) /= N2 and then Has_Private_View (Entity (N)) then
-            Set_Has_Private_View (N);
+         if Entity (N) /= N2 then
+            if Has_Private_View (Entity (N)) then
+               Set_Has_Private_View (N);
+            end if;
+
+            if Has_Secondary_Private_View (Entity (N)) then
+               Set_Has_Secondary_Private_View (N);
+            end if;
          end if;
 
-         --  If not a private type, nothing else to do
+         --  If not a private type, deal with a secondary private view
 
          if not Is_Private_Type (Typ) then
-            null;
+            if (Is_Access_Type (Typ)
+                 and then Is_Private_Type (Designated_Type (Typ)))
+              or else (Is_Array_Type (Typ)
+                        and then Is_Private_Type (Component_Type (Typ)))
+            then
+               Set_Has_Secondary_Private_View (N);
+            end if;
 
          --  If it is a derivation of a private type in a context where no
          --  full view is needed, nothing to do either.
diff --git a/gcc/ada/sem_ch12.ads b/gcc/ada/sem_ch12.ads
index 52e100e..3bf8fe9 100644
--- a/gcc/ada/sem_ch12.ads
+++ b/gcc/ada/sem_ch12.ads
@@ -204,7 +204,9 @@ package Sem_Ch12 is
    --  the current view after instantiation. The processing is driven by the
    --  current private status of the type of the node, and Has_Private_View,
    --  a flag that is set at the point of generic compilation. If view and
-   --  flag are inconsistent then the type is updated appropriately.
+   --  flag are inconsistent then the type is updated appropriately. A second
+   --  flag Has_Secondary_Private_View is used to update a second type related
+   --  to this type if need be.
    --
    --  This subprogram is used in Check_Generic_Actuals and Copy_Generic_Node,
    --  and is exported here for the purpose of front-end inlining (see Exp_Ch6.
diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index 6562732..c3ea8d63 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -426,7 +426,9 @@ package body Sem_Ch13 is
 
    procedure Adjust_Record_For_Reverse_Bit_Order (R : Entity_Id) is
       Max_Machine_Scalar_Size : constant Uint :=
-                                  UI_From_Int (System_Max_Integer_Size);
+        UI_From_Int (if Reverse_Bit_Order_Threshold >= 0
+                     then Reverse_Bit_Order_Threshold
+                     else System_Max_Integer_Size);
       --  We use this as the maximum machine scalar size
 
       SSU : constant Uint := UI_From_Int (System_Storage_Unit);
diff --git a/gcc/ada/sem_ch3.adb b/gcc/ada/sem_ch3.adb
index a067711..85019df 100644
--- a/gcc/ada/sem_ch3.adb
+++ b/gcc/ada/sem_ch3.adb
@@ -4690,6 +4690,16 @@ package body Sem_Ch3 is
          elsif No (E) and then Is_Null_Record_Type (T) then
             null;
 
+         --  If there is an address clause for this object, do not generate a
+         --  predicate check here. It will be generated later, at the freezng
+         --  point. It would be wrong to generate references to the object
+         --  here, before the address has been determined.
+
+         elsif Has_Aspect (Id, Aspect_Address)
+           or else Present (Following_Address_Clause (N))
+         then
+            null;
+
          --  Do not generate a predicate check if the initialization expression
          --  is a type conversion whose target subtype statically matches the
          --  object's subtype because the conversion has been subjected to the
@@ -4709,7 +4719,6 @@ package body Sem_Ch3 is
             declare
                Check : constant Node_Id :=
                          Make_Predicate_Check (T, New_Occurrence_Of (Id, Loc));
-
             begin
                if No (Next_Decl) then
                   Append_To (List_Containing (N), Check);
@@ -5540,7 +5549,7 @@ package body Sem_Ch3 is
       --  avoided here, when the created subtype declaration is analyzed. (See
       --  Build_Derived_Types)
 
-      --  This also happens when the full view of a private type is derived
+      --  This also happens when the full view of a private type is a derived
       --  type with constraints. In this case the entity has been introduced
       --  in the private declaration.
 
@@ -8669,7 +8678,7 @@ package body Sem_Ch3 is
 
    --  5. FIRST TRANSFORMATION FOR DERIVED RECORDS
    --
-   --  Regardless of whether we dealing with a tagged or untagged type
+   --  Regardless of whether we are dealing with a tagged or untagged type
    --  we will transform all derived type declarations of the form
    --
    --               type T is new R (...) [with ...];
@@ -9037,9 +9046,16 @@ package body Sem_Ch3 is
    --  Start of processing for Build_Derived_Record_Type
 
    begin
+      --  If the parent type is a private extension with discriminants, we
+      --  need to have an unconstrained type on which to apply the inherited
+      --  constraint, so we get to the full view. However, this means that the
+      --  derived type and its implicit base type created below will not point
+      --  to the same view of their respective parent type and, thus, special
+      --  glue code like Exp_Ch7.Convert_View is needed to bridge this gap.
+
       if Ekind (Parent_Type) = E_Record_Type_With_Private
-        and then Present (Full_View (Parent_Type))
         and then Has_Discriminants (Parent_Type)
+        and then Present (Full_View (Parent_Type))
       then
          Parent_Base := Base_Type (Full_View (Parent_Type));
       else
@@ -9056,6 +9072,36 @@ package body Sem_Ch3 is
          Parent_Base := Base_Type (Parent_Base);
       end if;
 
+      --  If the parent base is a private type and only its full view has
+      --  discriminants, use the full view's base type.
+
+      --  This can happen when we are deriving from a subtype of a derived type
+      --  of a private type derived from a discriminated type with known
+      --  discriminant:
+      --
+      --  package Pkg;
+      --     type Root_Type(I: Positive) is record
+      --       ...
+      --     end record;
+      --     type Bounded_Root_Type is private;
+      --  private
+      --     type Bounded_Root_Type is new Root_Type(10);
+      --  end Pkg;
+      --
+      --  package Pkg2 is
+      --     type Constrained_Root_Type is new Pkg.Bounded_Root_Type;
+      --  end Pkg2;
+      --  subtype Sub_Base is Pkg2.Constrained_Root_Type;
+      --  type New_Der_Type is new Sub_Base;
+
+      if Is_Private_Type (Parent_Base)
+        and then Present (Full_View (Parent_Base))
+        and then not Has_Discriminants (Parent_Base)
+        and then Has_Discriminants (Full_View (Parent_Base))
+      then
+         Parent_Base := Base_Type (Full_View (Parent_Base));
+      end if;
+
       --  AI05-0115: if this is a derivation from a private type in some
       --  other scope that may lead to invisible components for the derived
       --  type, mark it accordingly.
@@ -9287,7 +9333,7 @@ package body Sem_Ch3 is
             Is_Completion => False, Derive_Subps => False);
 
          --  ??? This needs re-examination to determine whether the
-         --  above call can simply be replaced by a call to Analyze.
+         --  following call can simply be replaced by a call to Analyze.
 
          Set_Analyzed (New_Decl);
 
diff --git a/gcc/ada/sem_ch4.adb b/gcc/ada/sem_ch4.adb
index b4b158a..fafb7e6 100644
--- a/gcc/ada/sem_ch4.adb
+++ b/gcc/ada/sem_ch4.adb
@@ -4913,16 +4913,6 @@ package body Sem_Ch4 is
       --  the discriminant values for a discriminant constraint)
       --  are unprefixed discriminant names.
 
-      procedure Find_Component_In_Instance (Rec : Entity_Id);
-      --  In an instance, a component of a private extension may not be visible
-      --  while it was visible in the generic. Search candidate scope for a
-      --  component with the proper identifier. This is only done if all other
-      --  searches have failed. If a match is found, the Etype of both N and
-      --  Sel are set from this component, and the entity of Sel is set to
-      --  reference this component. If no match is found, Entity (Sel) remains
-      --  unset. For a derived type that is an actual of the instance, the
-      --  desired component may be found in any ancestor.
-
       function Has_Mode_Conformant_Spec (Comp : Entity_Id) return Boolean;
       --  It is known that the parent of N denotes a subprogram call. Comp
       --  is an overloadable component of the concurrent type of the prefix.
@@ -4941,6 +4931,14 @@ package body Sem_Ch4 is
       --  _Procedure, and collect all its interpretations (since it may be an
       --  overloaded interface primitive); otherwise return False.
 
+      function Try_Selected_Component_In_Instance
+        (Typ : Entity_Id) return Boolean;
+      --  If Typ is the actual for a formal derived type, or a derived type
+      --  thereof, the component inherited from the generic parent may not
+      --  be visible in the actual, but the selected component is legal. Climb
+      --  up the derivation chain of the generic parent type and return True if
+      --  we find the proper ancestor type; otherwise return False.
+
       ------------------------------------------------------
       -- Constraint_Has_Unprefixed_Discriminant_Reference --
       ------------------------------------------------------
@@ -4990,49 +4988,6 @@ package body Sem_Ch4 is
          return False;
       end Constraint_Has_Unprefixed_Discriminant_Reference;
 
-      --------------------------------
-      -- Find_Component_In_Instance --
-      --------------------------------
-
-      procedure Find_Component_In_Instance (Rec : Entity_Id) is
-         Comp : Entity_Id;
-         Typ  : Entity_Id;
-
-      begin
-         Typ := Rec;
-         while Present (Typ) loop
-            Comp := First_Component (Typ);
-            while Present (Comp) loop
-               if Chars (Comp) = Chars (Sel) then
-                  Set_Entity_With_Checks (Sel, Comp);
-                  Set_Etype (Sel, Etype (Comp));
-                  Set_Etype (N,   Etype (Comp));
-                  return;
-               end if;
-
-               Next_Component (Comp);
-            end loop;
-
-            --  If not found, the component may be declared in the parent
-            --  type or its full view, if any.
-
-            if Is_Derived_Type (Typ) then
-               Typ := Etype (Typ);
-
-               if Is_Private_Type (Typ) then
-                  Typ := Full_View (Typ);
-               end if;
-
-            else
-               return;
-            end if;
-         end loop;
-
-         --  If we fall through, no match, so no changes made
-
-         return;
-      end Find_Component_In_Instance;
-
       ------------------------------
       -- Has_Mode_Conformant_Spec --
       ------------------------------
@@ -5170,6 +5125,122 @@ package body Sem_Ch4 is
          return Present (Candidate);
       end Try_By_Protected_Procedure_Prefixed_View;
 
+      ----------------------------------------
+      -- Try_Selected_Component_In_Instance --
+      ----------------------------------------
+
+      function Try_Selected_Component_In_Instance
+        (Typ : Entity_Id) return Boolean
+      is
+         procedure Find_Component_In_Instance (Rec : Entity_Id);
+         --  In an instance, a component of a private extension may not be
+         --  visible while it was visible in the generic. Search candidate
+         --  scope for a component with the proper identifier. If a match is
+         --  found, the Etype of both N and Sel are set from this component,
+         --  and the entity of Sel is set to reference this component. If no
+         --  match is found, Entity (Sel) remains unset. For a derived type
+         --  that is an actual of the instance, the desired component may be
+         --  found in any ancestor.
+
+         --------------------------------
+         -- Find_Component_In_Instance --
+         --------------------------------
+
+         procedure Find_Component_In_Instance (Rec : Entity_Id) is
+            Comp : Entity_Id;
+            Typ  : Entity_Id;
+
+         begin
+            Typ := Rec;
+            while Present (Typ) loop
+               Comp := First_Component (Typ);
+               while Present (Comp) loop
+                  if Chars (Comp) = Chars (Sel) then
+                     Set_Entity_With_Checks (Sel, Comp);
+                     Set_Etype (Sel, Etype (Comp));
+                     Set_Etype (N,   Etype (Comp));
+                     return;
+                  end if;
+
+                  Next_Component (Comp);
+               end loop;
+
+               --  If not found, the component may be declared in the parent
+               --  type or its full view, if any.
+
+               if Is_Derived_Type (Typ) then
+                  Typ := Etype (Typ);
+
+                  if Is_Private_Type (Typ) then
+                     Typ := Full_View (Typ);
+                  end if;
+
+               else
+                  return;
+               end if;
+            end loop;
+
+            --  If we fall through, no match, so no changes made
+
+            return;
+         end Find_Component_In_Instance;
+
+         --  Local variables
+
+         Par : Entity_Id;
+
+      --  Start of processing for Try_Selected_Component_In_Instance
+
+      begin
+         pragma Assert (In_Instance and then Is_Tagged_Type (Typ));
+         pragma Assert (Etype (N) = Any_Type);
+
+         --  Climb up derivation chain to generic actual subtype
+
+         Par := Typ;
+         while not Is_Generic_Actual_Type (Par) loop
+            if Ekind (Par) = E_Record_Type then
+               Par := Parent_Subtype (Par);
+               exit when No (Par);
+            else
+               exit when Par = Etype (Par);
+               Par := Etype (Par);
+            end if;
+         end loop;
+
+         if Present (Par) and then Is_Generic_Actual_Type (Par) then
+
+            --  Now look for component in ancestor types
+
+            Par := Generic_Parent_Type (Declaration_Node (Par));
+            loop
+               Find_Component_In_Instance (Par);
+               exit when Present (Entity (Sel))
+                 or else Par = Etype (Par);
+               Par := Etype (Par);
+            end loop;
+
+         --  Another special case: the type is an extension of a private
+         --  type T, either is an actual in an instance or is immediately
+         --  visible, and we are in the body of the instance, which means
+         --  the generic body had a full view of the type declaration for
+         --  T or some ancestor that defines the component in question.
+         --  This happens because Is_Visible_Component returned False on
+         --  this component, as T or the ancestor is still private since
+         --  the Has_Private_View mechanism is bypassed because T or the
+         --  ancestor is not directly referenced in the generic body.
+
+         elsif Is_Derived_Type (Typ)
+           and then (Used_As_Generic_Actual (Typ)
+                      or else Is_Immediately_Visible (Typ))
+           and then In_Instance_Body
+         then
+            Find_Component_In_Instance (Parent_Subtype (Typ));
+         end if;
+
+         return Etype (N) /= Any_Type;
+      end Try_Selected_Component_In_Instance;
+
    --  Start of processing for Analyze_Selected_Component
 
    begin
@@ -5523,6 +5594,22 @@ package body Sem_Ch4 is
             elsif Try_By_Protected_Procedure_Prefixed_View then
                return;
 
+            --  If the prefix type is the actual for a formal derived type,
+            --  or a derived type thereof, the component inherited from the
+            --  generic parent may not be visible in the actual, but the
+            --  selected component is legal. This case must be handled before
+            --  trying the object.operation notation to avoid reporting
+            --  spurious errors, but must be skipped when Is_Prefixed_Call has
+            --  been set (because that means that this node was resolved to an
+            --  Object.Operation call when the generic unit was analyzed).
+
+            elsif In_Instance
+              and then not Is_Prefixed_Call (N)
+              and then Is_Tagged_Type (Prefix_Type)
+              and then Try_Selected_Component_In_Instance (Type_To_Use)
+            then
+               return;
+
             elsif Try_Object_Operation (N) then
                return;
             end if;
@@ -5883,65 +5970,23 @@ package body Sem_Ch4 is
          --  Similarly, if this is the actual for a formal derived type, or
          --  a derived type thereof, the component inherited from the generic
          --  parent may not be visible in the actual, but the selected
-         --  component is legal. Climb up the derivation chain of the generic
-         --  parent type until we find the proper ancestor type.
+         --  component is legal.
 
          elsif In_Instance and then Is_Tagged_Type (Prefix_Type) then
-            declare
-               Par : Entity_Id := Prefix_Type;
-            begin
-               --  Climb up derivation chain to generic actual subtype
-
-               while not Is_Generic_Actual_Type (Par) loop
-                  if Ekind (Par) = E_Record_Type then
-                     Par := Parent_Subtype (Par);
-                     exit when No (Par);
-                  else
-                     exit when Par = Etype (Par);
-                     Par := Etype (Par);
-                  end if;
-               end loop;
-
-               if Present (Par) and then Is_Generic_Actual_Type (Par) then
 
-                  --  Now look for component in ancestor types
+            --  Climb up the derivation chain of the generic parent type until
+            --  we find the proper ancestor type.
 
-                  Par := Generic_Parent_Type (Declaration_Node (Par));
-                  loop
-                     Find_Component_In_Instance (Par);
-                     exit when Present (Entity (Sel))
-                       or else Par = Etype (Par);
-                     Par := Etype (Par);
-                  end loop;
-
-               --  Another special case: the type is an extension of a private
-               --  type T, either is an actual in an instance or is immediately
-               --  visible, and we are in the body of the instance, which means
-               --  the generic body had a full view of the type declaration for
-               --  T or some ancestor that defines the component in question.
-               --  This happens because Is_Visible_Component returned False on
-               --  this component, as T or the ancestor is still private since
-               --  the Has_Private_View mechanism is bypassed because T or the
-               --  ancestor is not directly referenced in the generic body.
-
-               elsif Is_Derived_Type (Type_To_Use)
-                 and then (Used_As_Generic_Actual (Type_To_Use)
-                            or else Is_Immediately_Visible (Type_To_Use))
-                 and then In_Instance_Body
-               then
-                  Find_Component_In_Instance (Parent_Subtype (Type_To_Use));
-               end if;
-            end;
+            if Try_Selected_Component_In_Instance (Type_To_Use) then
+               return;
 
             --  The search above must have eventually succeeded, since the
             --  selected component was legal in the generic.
 
-            if No (Entity (Sel)) then
+            else
                raise Program_Error;
             end if;
 
-            return;
-
          --  Component not found, specialize error message when appropriate
 
          else
diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 17c50f6..62ca985 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -8410,21 +8410,14 @@ package body Sem_Ch6 is
            Ctype <= Mode_Conformant
              or else Subtypes_Statically_Match (Type_1, Full_View (Type_2));
 
-      elsif Is_Private_Type (Type_2)
-        and then In_Instance
-        and then Present (Full_View (Type_2))
-        and then Base_Types_Match (Type_1, Full_View (Type_2))
-      then
-         return
-           Ctype <= Mode_Conformant
-             or else Subtypes_Statically_Match (Type_1, Full_View (Type_2));
-
-      --  Another confusion between views in a nested instance with an
-      --  actual private type whose full view is not in scope.
+      --  The subtype declared for the formal type in an instantiation and the
+      --  actual type are conforming. Note that testing Is_Generic_Actual_Type
+      --  here is not sufficient because the flag is only set in the bodies of
+      --  instances, which is too late for formal subprograms.
 
       elsif Ekind (Type_2) = E_Private_Subtype
-        and then In_Instance
         and then Etype (Type_2) = Type_1
+        and then Present (Generic_Parent_Type (Declaration_Node (Type_2)))
       then
          return True;
 
diff --git a/gcc/ada/sem_elab.adb b/gcc/ada/sem_elab.adb
index dc81e47..46bad04 100644
--- a/gcc/ada/sem_elab.adb
+++ b/gcc/ada/sem_elab.adb
@@ -15316,9 +15316,10 @@ package body Sem_Elab is
 
             if Earlier_In_Extended_Unit (FNode, Region) then
                Error_Msg_Node_2 := Prim;
+               Error_Msg_Code := GEC_Type_Early_Call_Region;
                Error_Msg_NE
                  ("first freezing point of type & must appear within early "
-                  & "call region of primitive body & (SPARK RM 7.7(8))",
+                  & "call region of primitive body '[[]']",
                   Typ_Decl, Typ);
 
                Error_Msg_Sloc := Sloc (Region);
diff --git a/gcc/ada/sem_prag.adb b/gcc/ada/sem_prag.adb
index bcae43f..c581068 100644
--- a/gcc/ada/sem_prag.adb
+++ b/gcc/ada/sem_prag.adb
@@ -30974,9 +30974,10 @@ package body Sem_Prag is
          --  All other cases require Part_Of
 
          else
+            Error_Msg_Code := GEC_Required_Part_Of;
             Error_Msg_N
-              ("indicator Part_Of is required in this context "
-               & "(SPARK RM 7.2.6(2))", Item_Id);
+              ("indicator Part_Of is required in this context '[[]']",
+               Item_Id);
             Error_Msg_Name_1 := Chars (Pack_Id);
             Error_Msg_N
               ("\& is declared in the private part of package %", Item_Id);
diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb
index 41787f3..2c8efec 100644
--- a/gcc/ada/sem_res.adb
+++ b/gcc/ada/sem_res.adb
@@ -3914,9 +3914,10 @@ package body Sem_Res is
                                                   Obj_Ref       => N,
                                                   Check_Actuals => True)
                   then
+                     Error_Msg_Code := GEC_Volatile_Non_Interfering_Context;
                      Error_Msg_N
-                       ("volatile object cannot appear in this context"
-                        & " (SPARK RM 7.1.3(10))", N);
+                       ("volatile object cannot appear in this context '[[]']",
+                        N);
                   end if;
 
                   return Skip;
@@ -7299,6 +7300,15 @@ package body Sem_Res is
                   ("cannot inline & (in potentially unevaluated context)?",
                    N, Nam_UA);
 
+            --  Calls are not inlined inside the loop_parameter_specification
+            --  or iterator_specification of the quantified expression, as they
+            --  are only preanalyzed. Calls in the predicate part are handled
+            --  by the previous test on potentially unevaluated expressions.
+
+            elsif In_Quantified_Expression (N) then
+               Cannot_Inline
+                 ("cannot inline & (in quantified expression)?", N, Nam_UA);
+
             --  Inlining should not be performed during preanalysis
 
             elsif Full_Analysis then
@@ -8103,9 +8113,9 @@ package body Sem_Res is
               and then
                 not Is_OK_Volatile_Context (Par, N, Check_Actuals => False)
             then
+               Error_Msg_Code := GEC_Volatile_Non_Interfering_Context;
                SPARK_Msg_N
-                 ("volatile object cannot appear in this context "
-                  & "(SPARK RM 7.1.3(10))", N);
+                 ("volatile object cannot appear in this context '[[]']", N);
             end if;
 
             --  Parameters of modes OUT or IN OUT of the subprogram shall not
@@ -8116,7 +8126,7 @@ package body Sem_Res is
             --  data from the object.
 
             if Ekind (E) in E_Out_Parameter | E_In_Out_Parameter
-              and then Scope (E) = Current_Scope
+              and then Scope (E) = Current_Scope_No_Loops
               and then Within_Exceptional_Cases_Consequence (N)
               and then not In_Attribute_Old (N)
               and then not (Nkind (Parent (N)) = N_Attribute_Reference
@@ -8124,7 +8134,8 @@ package body Sem_Res is
                             Attribute_Name (Parent (N)) in Name_Constrained
                                                          | Name_First
                                                          | Name_Last
-                                                         | Name_Length)
+                                                         | Name_Length
+                                                         | Name_Range)
               and then not Is_By_Reference_Type (Etype (E))
               and then not Is_Aliased (E)
             then
@@ -9601,17 +9612,6 @@ package body Sem_Res is
       Desig_Typ : Entity_Id;
 
    begin
-      --  In an instance the proper view may not always be correct for
-      --  private types, see e.g. Sem_Type.Covers for similar handling.
-
-      if Is_Private_Type (Etype (P))
-        and then Present (Full_View (Etype (P)))
-        and then Is_Access_Type (Full_View (Etype (P)))
-        and then In_Instance
-      then
-         Set_Etype (P, Full_View (Etype (P)));
-      end if;
-
       if Is_Access_Type (Etype (P)) then
          Desig_Typ := Implicitly_Designated_Type (Etype (P));
          Insert_Explicit_Dereference (P);
diff --git a/gcc/ada/sem_type.adb b/gcc/ada/sem_type.adb
index 8519b97..00a6415 100644
--- a/gcc/ada/sem_type.adb
+++ b/gcc/ada/sem_type.adb
@@ -884,6 +884,16 @@ package body Sem_Type is
             end;
          end if;
 
+      --  This test may seem to be redundant with the above one, but it catches
+      --  peculiar cases where a private type declared in a package is used in
+      --  a generic construct declared in another package, and the body of the
+      --  former package contains an instantiation of the generic construct on
+      --  an object whose type is a subtype of the private type; in this case,
+      --  the subtype is not private but the type is private in the instance.
+
+      elsif Is_Subtype_Of (T1 => T2, T2 => T1) then
+         return True;
+
       --  Literals are compatible with types in a given "class"
 
       elsif     (T2 = Universal_Integer and then Is_Integer_Type (T1))
@@ -1161,20 +1171,20 @@ package body Sem_Type is
       then
          return True;
 
-      --  In instances, or with types exported from instantiations, check
-      --  whether a partial and a full view match. Verify that types are
-      --  legal, to prevent cascaded errors.
+      --  With types exported from instantiations, check whether a partial and
+      --  a full view match. Verify that types are legal, to prevent cascaded
+      --  errors.
 
       elsif Is_Private_Type (T1)
-        and then (In_Instance
-                   or else (Is_Type (T2) and then Is_Generic_Actual_Type (T2)))
+        and then Is_Type (T2)
+        and then Is_Generic_Actual_Type (T2)
         and then Full_View_Covers (T1, T2)
       then
          return True;
 
       elsif Is_Private_Type (T2)
-        and then (In_Instance
-                   or else (Is_Type (T1) and then Is_Generic_Actual_Type (T1)))
+        and then Is_Type (T1)
+        and then Is_Generic_Actual_Type (T1)
         and then Full_View_Covers (T2, T1)
       then
          return True;
@@ -3457,9 +3467,10 @@ package body Sem_Type is
       then
          return T2;
 
-      --  In instances, also check private views the same way as Covers
+      --  With types exported from instantiation, also check private views the
+      --  same way as Covers
 
-      elsif Is_Private_Type (T1) and then In_Instance then
+      elsif Is_Private_Type (T1) and then Is_Generic_Actual_Type (T2) then
          if Present (Full_View (T1)) then
             return Specific_Type (Full_View (T1), T2);
 
@@ -3467,7 +3478,7 @@ package body Sem_Type is
             return Specific_Type (Underlying_Full_View (T1), T2);
          end if;
 
-      elsif Is_Private_Type (T2) and then In_Instance then
+      elsif Is_Private_Type (T2) and then Is_Generic_Actual_Type (T1) then
          if Present (Full_View (T2)) then
             return Specific_Type (T1, Full_View (T2));
 
diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 3a64047d..d9ea00e 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -4566,6 +4566,38 @@ package body Sem_Util is
 
       elsif No (Items) then
          return;
+
+      --  If the subprogram has a contract Exceptional_Cases, it is often
+      --  useful to refer only to the pre-state in the postcondition, to
+      --  indicate when the subprogram might terminate normally.
+
+      elsif Present (Get_Pragma (Subp_Id, Pragma_Exceptional_Cases)) then
+         return;
+
+      --  Same if the subprogram has a contract Always_Terminates => Cond,
+      --  where Cond is not syntactically True.
+
+      else
+         declare
+            Prag : constant Node_Id :=
+              Get_Pragma (Subp_Id, Pragma_Always_Terminates);
+         begin
+            if Present (Prag)
+              and then Present (Pragma_Argument_Associations (Prag))
+            then
+               declare
+                  Cond : constant Node_Id :=
+                    Get_Pragma_Arg
+                      (First (Pragma_Argument_Associations (Prag)));
+               begin
+                  if not Compile_Time_Known_Value (Cond)
+                    or else not Is_True (Expr_Value (Cond))
+                  then
+                     return;
+                  end if;
+               end;
+            end if;
+         end;
       end if;
 
       --  Examine all postconditions for attribute 'Result and a post-state
@@ -29478,56 +29510,6 @@ package body Sem_Util is
         and then Full_View (Etype (Expr)) = Expec_Type
       then
          return;
-
-      --  In an instance, there is an ongoing problem with completion of
-      --  types derived from private types. Their structure is what Gigi
-      --  expects, but the Etype is the parent type rather than the derived
-      --  private type itself. Do not flag error in this case. The private
-      --  completion is an entity without a parent, like an Itype. Similarly,
-      --  full and partial views may be incorrect in the instance.
-      --  There is no simple way to insure that it is consistent ???
-
-      --  A similar view discrepancy can happen in an inlined body, for the
-      --  same reason: inserted body may be outside of the original package
-      --  and only partial views are visible at the point of insertion.
-
-      --  If In_Generic_Actual (Expr) is True then we cannot assume that
-      --  the successful semantic analysis of the generic guarantees anything
-      --  useful about type checking of this instance, so we ignore
-      --  In_Instance in that case. There may be cases where this is not
-      --  right (the symptom would probably be rejecting something
-      --  that ought to be accepted) but we don't currently have any
-      --  concrete examples of this.
-
-      elsif (In_Instance and then not In_Generic_Actual (Expr))
-        or else In_Inlined_Body
-      then
-         if Etype (Etype (Expr)) = Etype (Expected_Type)
-           and then
-             (Has_Private_Declaration (Expected_Type)
-               or else Has_Private_Declaration (Etype (Expr)))
-           and then No (Parent (Expected_Type))
-         then
-            return;
-
-         elsif Nkind (Parent (Expr)) = N_Qualified_Expression
-           and then Entity (Subtype_Mark (Parent (Expr))) = Expected_Type
-         then
-            return;
-
-         elsif Is_Private_Type (Expected_Type)
-           and then Present (Full_View (Expected_Type))
-           and then Covers (Full_View (Expected_Type), Etype (Expr))
-         then
-            return;
-
-         --  Conversely, type of expression may be the private one
-
-         elsif Is_Private_Type (Base_Type (Etype (Expr)))
-           and then Full_View (Base_Type (Etype (Expr))) = Expected_Type
-         then
-            return;
-         end if;
       end if;
 
       --  Avoid printing internally generated subtypes in error messages and
diff --git a/gcc/ada/sinfo.ads b/gcc/ada/sinfo.ads
index 8040a59..57fd704 100644
--- a/gcc/ada/sinfo.ads
+++ b/gcc/ada/sinfo.ads
@@ -389,21 +389,23 @@ package Sinfo is
    --  abbreviations are used:
 
    --    "plus fields for binary operator"
-   --       Chars                     Name_Id for the operator
-   --       Left_Opnd                 left operand expression
-   --       Right_Opnd                right operand expression
-   --       Entity                    defining entity for operator
-   --       Associated_Node           for generic processing
-   --       Do_Overflow_Check         set if overflow check needed
-   --       Has_Private_View          set in generic units.
+   --       Chars                       Name_Id for the operator
+   --       Left_Opnd                   left operand expression
+   --       Right_Opnd                  right operand expression
+   --       Entity                      defining entity for operator
+   --       Associated_Node             for generic processing
+   --       Do_Overflow_Check           set if overflow check needed
+   --       Has_Private_View            set in generic units
+   --       Has_Secondary_Private_View  set in generic units
 
    --    "plus fields for unary operator"
-   --       Chars                     Name_Id for the operator
-   --       Right_Opnd                right operand expression
-   --       Entity                    defining entity for operator
-   --       Associated_Node           for generic processing
-   --       Do_Overflow_Check         set if overflow check needed
-   --       Has_Private_View          set in generic units.
+   --       Chars                       Name_Id for the operator
+   --       Right_Opnd                  right operand expression
+   --       Entity                      defining entity for operator
+   --       Associated_Node             for generic processing
+   --       Do_Overflow_Check           set if overflow check needed
+   --       Has_Private_View            set in generic units
+   --       Has_Secondary_Private_View  set in generic units
 
    --    "plus fields for expression"
    --       Paren_Count               number of parentheses levels
@@ -1457,6 +1459,13 @@ package Sinfo is
    --    A flag present in N_Subprogram_Body and N_Task_Definition nodes to
    --    flag the presence of a pragma Relative_Deadline.
 
+   --  Has_Secondary_Private_View
+   --    A flag present in generic nodes that have an entity, to indicate that
+   --    the node is either of an access type whose Designated_Type is private
+   --    or of an array type whose Component_Type is private. Used to exchange
+   --    private and full declarations if the visibility at instantiation is
+   --    different from the visibility at generic definition.
+
    --  Has_Self_Reference
    --    Present in N_Aggregate and N_Extension_Aggregate. Indicates that one
    --    of the expressions contains an access attribute reference to the
@@ -2522,6 +2531,7 @@ package Sinfo is
       --  Is_SPARK_Mode_On_Node
       --  Is_Elaboration_Warnings_OK_Node
       --  Has_Private_View (set in generic units)
+      --  Has_Secondary_Private_View (set in generic units)
       --  Redundant_Use
       --  Atomic_Sync_Required
       --  plus fields for expression
@@ -2605,6 +2615,7 @@ package Sinfo is
       --  Entity
       --  Associated_Node
       --  Has_Private_View (set in generic units)
+      --  Has_Secondary_Private_View (set in generic units)
       --  plus fields for expression
 
       --  Note: the Entity field will be missing (set to Empty) for character
@@ -5388,6 +5399,7 @@ package Sinfo is
       --  Associated_Node Note this is shared with Entity
       --  Etype
       --  Has_Private_View (set in generic units)
+      --  Has_Secondary_Private_View (set in generic units)
 
       --  Note: the Strval field may be set to No_String for generated
       --  operator symbols that are known not to be string literals
@@ -8030,6 +8042,7 @@ package Sinfo is
       --  Is_SPARK_Mode_On_Node
       --  Is_Elaboration_Warnings_OK_Node
       --  Has_Private_View (set in generic units)
+      --  Has_Secondary_Private_View (set in generic units)
       --  Redundant_Use
       --  Atomic_Sync_Required
       --  plus fields for expression
diff --git a/gcc/ada/switch-c.adb b/gcc/ada/switch-c.adb
index f6207e4..bbbb536 100644
--- a/gcc/ada/switch-c.adb
+++ b/gcc/ada/switch-c.adb
@@ -635,6 +635,12 @@ package body Switch.C is
                      Generate_Processed_File := True;
                      Ptr := Ptr + 1;
 
+                  --  -gnateH (set reverse Bit_Order threshold to 64)
+
+                  when 'H' =>
+                     Reverse_Bit_Order_Threshold := 64;
+                     Ptr := Ptr + 1;
+
                   --  -gnatei (max number of instantiations)
 
                   when 'i' =>
diff --git a/gcc/ada/usage.adb b/gcc/ada/usage.adb
index 58cfa78..681ece5 100644
--- a/gcc/ada/usage.adb
+++ b/gcc/ada/usage.adb
@@ -199,6 +199,11 @@ begin
    Write_Switch_Char ("eG");
    Write_Line ("Generate preprocessed source");
 
+   --  Line for -gnateH switch
+
+   Write_Switch_Char ("eH");
+   Write_Line ("Set reverse Bit_Order threshold to 64");
+
    --  Line for -gnatei switch
 
    Write_Switch_Char ("einn");
diff --git a/gcc/builtin-types.def b/gcc/builtin-types.def
index 5cb25ab..43381bc 100644
--- a/gcc/builtin-types.def
+++ b/gcc/builtin-types.def
@@ -842,10 +842,17 @@ DEF_FUNCTION_TYPE_4 (BT_FN_PTR_PTR_INT_SIZE_SIZE,
 		     BT_PTR, BT_PTR, BT_INT, BT_SIZE, BT_SIZE)
 DEF_FUNCTION_TYPE_4 (BT_FN_UINT_UINT_UINT_UINT_UINT,
 		     BT_UINT, BT_UINT, BT_UINT, BT_UINT, BT_UINT)
+DEF_FUNCTION_TYPE_4 (BT_FN_UINT_UINT_UINT_UINT_UINTPTR,
+		     BT_UINT, BT_UINT, BT_UINT, BT_UINT, BT_PTR_UINT)
 DEF_FUNCTION_TYPE_4 (BT_FN_UINT_FLOAT_FLOAT_FLOAT_FLOAT,
 		     BT_UINT, BT_FLOAT, BT_FLOAT, BT_FLOAT, BT_FLOAT)
 DEF_FUNCTION_TYPE_4 (BT_FN_ULONG_ULONG_ULONG_UINT_UINT,
 		     BT_ULONG, BT_ULONG, BT_ULONG, BT_UINT, BT_UINT)
+DEF_FUNCTION_TYPE_4 (BT_FN_ULONG_ULONG_ULONG_ULONG_ULONGPTR,
+		     BT_ULONG, BT_ULONG, BT_ULONG, BT_ULONG, BT_PTR_ULONG)
+DEF_FUNCTION_TYPE_4 (BT_FN_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONGPTR,
+		     BT_ULONGLONG, BT_ULONGLONG, BT_ULONGLONG, BT_ULONGLONG,
+		     BT_PTR_ULONGLONG)
 DEF_FUNCTION_TYPE_4 (BT_FN_STRING_STRING_CONST_STRING_SIZE_SIZE,
 		     BT_STRING, BT_STRING, BT_CONST_STRING, BT_SIZE, BT_SIZE)
 DEF_FUNCTION_TYPE_4 (BT_FN_INT_FILEPTR_INT_CONST_STRING_VALIST_ARG,
diff --git a/gcc/builtins.cc b/gcc/builtins.cc
index 8400ada..6dff521 100644
--- a/gcc/builtins.cc
+++ b/gcc/builtins.cc
@@ -9555,6 +9555,51 @@ fold_builtin_arith_overflow (location_t loc, enum built_in_function fcode,
   return build2_loc (loc, COMPOUND_EXPR, boolean_type_node, store, ovfres);
 }
 
+/* Fold __builtin_{add,sub}c{,l,ll} into pair of internal functions
+   that return both result of arithmetics and overflowed boolean
+   flag in a complex integer result.  */
+
+static tree
+fold_builtin_addc_subc (location_t loc, enum built_in_function fcode,
+			tree *args)
+{
+  enum internal_fn ifn;
+
+  switch (fcode)
+    {
+    case BUILT_IN_ADDC:
+    case BUILT_IN_ADDCL:
+    case BUILT_IN_ADDCLL:
+      ifn = IFN_ADD_OVERFLOW;
+      break;
+    case BUILT_IN_SUBC:
+    case BUILT_IN_SUBCL:
+    case BUILT_IN_SUBCLL:
+      ifn = IFN_SUB_OVERFLOW;
+      break;
+    default:
+      gcc_unreachable ();
+    }
+
+  tree type = TREE_TYPE (args[0]);
+  tree ctype = build_complex_type (type);
+  tree call = build_call_expr_internal_loc (loc, ifn, ctype, 2,
+					    args[0], args[1]);
+  tree tgt = save_expr (call);
+  tree intres = build1_loc (loc, REALPART_EXPR, type, tgt);
+  tree ovfres = build1_loc (loc, IMAGPART_EXPR, type, tgt);
+  call = build_call_expr_internal_loc (loc, ifn, ctype, 2,
+				       intres, args[2]);
+  tgt = save_expr (call);
+  intres = build1_loc (loc, REALPART_EXPR, type, tgt);
+  tree ovfres2 = build1_loc (loc, IMAGPART_EXPR, type, tgt);
+  ovfres = build2_loc (loc, BIT_IOR_EXPR, type, ovfres, ovfres2);
+  tree mem_arg3 = build_fold_indirect_ref_loc (loc, args[3]);
+  tree store
+    = fold_build2_loc (loc, MODIFY_EXPR, void_type_node, mem_arg3, ovfres);
+  return build2_loc (loc, COMPOUND_EXPR, type, store, intres);
+}
+
 /* Fold a call to __builtin_FILE to a constant string.  */
 
 static inline tree
@@ -10843,6 +10888,14 @@ fold_builtin_varargs (location_t loc, tree fndecl, tree *args, int nargs)
       ret = fold_builtin_fpclassify (loc, args, nargs);
       break;
 
+    case BUILT_IN_ADDC:
+    case BUILT_IN_ADDCL:
+    case BUILT_IN_ADDCLL:
+    case BUILT_IN_SUBC:
+    case BUILT_IN_SUBCL:
+    case BUILT_IN_SUBCLL:
+      return fold_builtin_addc_subc (loc, fcode, args);
+
     default:
       break;
     }
diff --git a/gcc/builtins.def b/gcc/builtins.def
index 4ad95a1..76e7200 100644
--- a/gcc/builtins.def
+++ b/gcc/builtins.def
@@ -934,6 +934,12 @@ DEF_GCC_BUILTIN        (BUILT_IN_USUBLL_OVERFLOW, "usubll_overflow", BT_FN_BOOL_
 DEF_GCC_BUILTIN        (BUILT_IN_UMUL_OVERFLOW, "umul_overflow", BT_FN_BOOL_UINT_UINT_UINTPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
 DEF_GCC_BUILTIN        (BUILT_IN_UMULL_OVERFLOW, "umull_overflow", BT_FN_BOOL_ULONG_ULONG_ULONGPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
 DEF_GCC_BUILTIN        (BUILT_IN_UMULLL_OVERFLOW, "umulll_overflow", BT_FN_BOOL_ULONGLONG_ULONGLONG_ULONGLONGPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
+DEF_GCC_BUILTIN        (BUILT_IN_ADDC, "addc", BT_FN_UINT_UINT_UINT_UINT_UINTPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
+DEF_GCC_BUILTIN        (BUILT_IN_ADDCL, "addcl", BT_FN_ULONG_ULONG_ULONG_ULONG_ULONGPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
+DEF_GCC_BUILTIN        (BUILT_IN_ADDCLL, "addcll", BT_FN_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONGPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
+DEF_GCC_BUILTIN        (BUILT_IN_SUBC, "subc", BT_FN_UINT_UINT_UINT_UINT_UINTPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
+DEF_GCC_BUILTIN        (BUILT_IN_SUBCL, "subcl", BT_FN_ULONG_ULONG_ULONG_ULONG_ULONGPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
+DEF_GCC_BUILTIN        (BUILT_IN_SUBCLL, "subcll", BT_FN_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONGPTR, ATTR_NOTHROW_NONNULL_LEAF_LIST)
 
 /* Category: miscellaneous builtins.  */
 DEF_LIB_BUILTIN        (BUILT_IN_ABORT, "abort", BT_FN_VOID, ATTR_TMPURE_NORETURN_NOTHROW_LEAF_COLD_LIST)
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 10c4a59..c78ad9c 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-21  Alexander Monakov  <amonakov@ispras.ru>
+
+	* c-gimplify.cc (fma_supported_p): New helper.
+	(c_gimplify_expr) [PLUS_EXPR, MINUS_EXPR]: Implement FMA
+	contraction.
+
+2023-06-16  Alex Coplan  <alex.coplan@arm.com>
+
+	* c.opt (Welaborated-enum-base): New.
+
 2023-06-13  David Malcolm  <dmalcolm@redhat.com>
 
 	PR c/84890
diff --git a/gcc/c-family/c-gimplify.cc b/gcc/c-family/c-gimplify.cc
index ef5c7d9..17b0610 100644
--- a/gcc/c-family/c-gimplify.cc
+++ b/gcc/c-family/c-gimplify.cc
@@ -41,6 +41,8 @@ along with GCC; see the file COPYING3.  If not see
 #include "c-ubsan.h"
 #include "tree-nested.h"
 #include "context.h"
+#include "tree-pass.h"
+#include "internal-fn.h"
 
 /*  The gimplification pass converts the language-dependent trees
     (ld-trees) emitted by the parser into language-independent trees
@@ -686,6 +688,14 @@ c_build_bind_expr (location_t loc, tree block, tree body)
   return bind;
 }
 
+/* Helper for c_gimplify_expr: test if target supports fma-like FN.  */
+
+static bool
+fma_supported_p (enum internal_fn fn, tree type)
+{
+  return direct_internal_fn_supported_p (fn, type, OPTIMIZE_FOR_BOTH);
+}
+
 /* Gimplification of expression trees.  */
 
 /* Do C-specific gimplification on *EXPR_P.  PRE_P and POST_P are as in
@@ -739,6 +749,75 @@ c_gimplify_expr (tree *expr_p, gimple_seq *pre_p ATTRIBUTE_UNUSED,
 	break;
       }
 
+    case PLUS_EXPR:
+    case MINUS_EXPR:
+      {
+	tree type = TREE_TYPE (*expr_p);
+	/* For -ffp-contract=on we need to attempt FMA contraction only
+	   during initial gimplification.  Late contraction across statement
+	   boundaries would violate language semantics.  */
+	if (SCALAR_FLOAT_TYPE_P (type)
+	    && flag_fp_contract_mode == FP_CONTRACT_ON
+	    && cfun && !(cfun->curr_properties & PROP_gimple_any)
+	    && fma_supported_p (IFN_FMA, type))
+	  {
+	    bool neg_mul = false, neg_add = code == MINUS_EXPR;
+
+	    tree *op0_p = &TREE_OPERAND (*expr_p, 0);
+	    tree *op1_p = &TREE_OPERAND (*expr_p, 1);
+
+	    /* Look for ±(x * y) ± z, swapping operands if necessary.  */
+	    if (TREE_CODE (*op0_p) == NEGATE_EXPR
+		&& TREE_CODE (TREE_OPERAND (*op0_p, 0)) == MULT_EXPR)
+	      /* '*EXPR_P' is '-(x * y) ± z'.  This is fine.  */;
+	    else if (TREE_CODE (*op0_p) != MULT_EXPR)
+	      {
+		std::swap (op0_p, op1_p);
+		std::swap (neg_mul, neg_add);
+	      }
+	    if (TREE_CODE (*op0_p) == NEGATE_EXPR)
+	      {
+		op0_p = &TREE_OPERAND (*op0_p, 0);
+		neg_mul = !neg_mul;
+	      }
+	    if (TREE_CODE (*op0_p) != MULT_EXPR)
+	      break;
+	    auto_vec<tree, 3> ops (3);
+	    ops.quick_push (TREE_OPERAND (*op0_p, 0));
+	    ops.quick_push (TREE_OPERAND (*op0_p, 1));
+	    ops.quick_push (*op1_p);
+
+	    enum internal_fn ifn = IFN_FMA;
+	    if (neg_mul)
+	      {
+		if (fma_supported_p (IFN_FNMA, type))
+		  ifn = IFN_FNMA;
+		else
+		  ops[0] = build1 (NEGATE_EXPR, type, ops[0]);
+	      }
+	    if (neg_add)
+	      {
+		enum internal_fn ifn2 = ifn == IFN_FMA ? IFN_FMS : IFN_FNMS;
+		if (fma_supported_p (ifn2, type))
+		  ifn = ifn2;
+		else
+		  ops[2] = build1 (NEGATE_EXPR, type, ops[2]);
+	      }
+	    /* Avoid gimplify_arg: it emits all side effects into *PRE_P.  */
+	    for (auto &&op : ops)
+	      if (gimplify_expr (&op, pre_p, post_p, is_gimple_val, fb_rvalue)
+		  == GS_ERROR)
+		return GS_ERROR;
+
+	    gcall *call = gimple_build_call_internal_vec (ifn, ops);
+	    gimple_seq_add_stmt_without_update (pre_p, call);
+	    *expr_p = create_tmp_var (type);
+	    gimple_call_set_lhs (call, *expr_p);
+	    return GS_ALL_DONE;
+	  }
+	break;
+      }
+
     default:;
     }
 
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 1d3700d..708c1c2 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,9 @@
+2023-06-16  David Malcolm  <dmalcolm@redhat.com>
+
+	PR c/107583
+	* c-parser.cc (c_parser_declspecs): Add hints to "unknown type
+	name" error.
+
 2023-06-12  Tobias Burnus  <tobias@codesourcery.com>
 
 	* c-parser.cc (c_parser_omp_clause_map): Reword error message for
diff --git a/gcc/calls.cc b/gcc/calls.cc
index 1c9abcc..1f3a6d5 100644
--- a/gcc/calls.cc
+++ b/gcc/calls.cc
@@ -94,11 +94,11 @@ struct arg_data
   /* Number of bytes to put in registers.  0 means put the whole arg
      in registers.  Also 0 if not passed in registers.  */
   int partial;
-  /* Nonzero if argument must be passed on stack.
+  /* True if argument must be passed on stack.
      Note that some arguments may be passed on the stack
-     even though pass_on_stack is zero, just because FUNCTION_ARG says so.
+     even though pass_on_stack is false, just because FUNCTION_ARG says so.
      pass_on_stack identifies arguments that *cannot* go in registers.  */
-  int pass_on_stack;
+  bool pass_on_stack;
   /* Some fields packaged up for locate_and_pad_parm.  */
   struct locate_and_pad_arg_data locate;
   /* Location on the stack at which parameter should be stored.  The store
@@ -150,19 +150,19 @@ static unsigned HOST_WIDE_INT stored_args_watermark;
 static int stack_arg_under_construction;
 
 static void precompute_register_parameters (int, struct arg_data *, int *);
-static int store_one_arg (struct arg_data *, rtx, int, int, int);
+static bool store_one_arg (struct arg_data *, rtx, int, int, int);
 static void store_unaligned_arguments_into_pseudos (struct arg_data *, int);
-static int finalize_must_preallocate (int, int, struct arg_data *,
-				      struct args_size *);
+static bool finalize_must_preallocate (bool, int, struct arg_data *,
+				       struct args_size *);
 static void precompute_arguments (int, struct arg_data *);
 static void compute_argument_addresses (struct arg_data *, rtx, int);
 static rtx rtx_for_function_call (tree, tree);
 static void load_register_parameters (struct arg_data *, int, rtx *, int,
-				      int, int *);
+				      int, bool *);
 static int special_function_p (const_tree, int);
-static int check_sibcall_argument_overlap_1 (rtx);
-static int check_sibcall_argument_overlap (rtx_insn *, struct arg_data *, int);
-
+static bool check_sibcall_argument_overlap_1 (rtx);
+static bool check_sibcall_argument_overlap (rtx_insn *, struct arg_data *,
+					    bool);
 static tree split_complex_types (tree);
 
 #ifdef REG_PARM_STACK_SPACE
@@ -383,7 +383,7 @@ emit_call_1 (rtx funexp, tree fntree ATTRIBUTE_UNUSED, tree fndecl ATTRIBUTE_UNU
 {
   rtx rounded_stack_size_rtx = gen_int_mode (rounded_stack_size, Pmode);
   rtx call, funmem, pat;
-  int already_popped = 0;
+  bool already_popped = false;
   poly_int64 n_popped = 0;
 
   /* Sibling call patterns never pop arguments (no sibcall(_value)_pop
@@ -461,7 +461,7 @@ emit_call_1 (rtx funexp, tree fntree ATTRIBUTE_UNUSED, tree fndecl ATTRIBUTE_UNU
 	pat = targetm.gen_call_pop (funmem, rounded_stack_size_rtx,
 				    next_arg_reg, n_pop);
 
-      already_popped = 1;
+      already_popped = true;
     }
   else
     {
@@ -666,14 +666,17 @@ decl_return_flags (tree fndecl)
   return 0;
 }
 
-/* Return nonzero when FNDECL represents a call to setjmp.  */
+/* Return true when FNDECL represents a call to setjmp.  */
 
-int
+bool
 setjmp_call_p (const_tree fndecl)
 {
   if (DECL_IS_RETURNS_TWICE (fndecl))
-    return ECF_RETURNS_TWICE;
-  return special_function_p (fndecl, 0) & ECF_RETURNS_TWICE;
+    return true;
+  if (special_function_p (fndecl, 0) & ECF_RETURNS_TWICE)
+    return true;
+
+  return false;
 }
 
 
@@ -1266,8 +1269,11 @@ maybe_complain_about_tail_call (tree call_expr, const char *reason)
    OLD_STACK_LEVEL is a pointer to an rtx which olds the old stack level
    and may be modified by this routine.
 
-   OLD_PENDING_ADJ, MUST_PREALLOCATE and FLAGS are pointers to integer
-   flags which may be modified by this routine.
+   OLD_PENDING_ADJ and FLAGS are pointers to integer flags which
+   may be modified by this routine.
+
+   MUST_PREALLOCATE is a pointer to bool which may be
+   modified by this routine.
 
    MAY_TAILCALL is cleared if we encounter an invisible pass-by-reference
    that requires allocation of stack space.
@@ -1286,7 +1292,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED,
 				 int reg_parm_stack_space,
 				 rtx *old_stack_level,
 				 poly_int64_pod *old_pending_adj,
-				 int *must_preallocate, int *ecf_flags,
+				 bool *must_preallocate, int *ecf_flags,
 				 bool *may_tailcall, bool call_from_thunk_p)
 {
   CUMULATIVE_ARGS *args_so_far_pnt = get_cumulative_args (args_so_far);
@@ -1359,7 +1365,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED,
 	 args[i].partial is nonzero if part but not all is passed in registers,
 	 and the exact value says how many bytes are passed in registers.
 
-	 args[i].pass_on_stack is nonzero if the argument must at least be
+	 args[i].pass_on_stack is true if the argument must at least be
 	 computed on the stack.  It may then be loaded back into registers
 	 if args[i].reg is nonzero.
 
@@ -1517,7 +1523,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED,
 	 by the PARALLEL, but also to pass it in the stack.  */
       if (args[i].reg && GET_CODE (args[i].reg) == PARALLEL
 	  && XEXP (XVECEXP (args[i].reg, 0, 0), 0) == 0)
-	args[i].pass_on_stack = 1;
+	args[i].pass_on_stack = true;
 
       /* If this is an addressable type, we must preallocate the stack
 	 since we must evaluate the object into its final location.
@@ -1526,7 +1532,7 @@ initialize_argument_information (int num_actuals ATTRIBUTE_UNUSED,
 	 to preallocate.  */
       if (TREE_ADDRESSABLE (type)
 	  || (args[i].pass_on_stack && args[i].reg != 0))
-	*must_preallocate = 1;
+	*must_preallocate = true;
 
       /* Compute the stack-size of this argument.  */
       if (args[i].reg == 0 || args[i].partial != 0
@@ -1713,8 +1719,8 @@ precompute_arguments (int num_actuals, struct arg_data *args)
    arguments to a function call in NUM_ACTUALS, ARGS and ARGS_SIZE,
    compute and return the final value for MUST_PREALLOCATE.  */
 
-static int
-finalize_must_preallocate (int must_preallocate, int num_actuals,
+static bool
+finalize_must_preallocate (bool must_preallocate, int num_actuals,
 			   struct arg_data *args, struct args_size *args_size)
 {
   /* See if we have or want to preallocate stack space.
@@ -1738,16 +1744,16 @@ finalize_must_preallocate (int must_preallocate, int num_actuals,
 
   if (! must_preallocate)
     {
-      int partial_seen = 0;
+      bool partial_seen = false;
       poly_int64 copy_to_evaluate_size = 0;
       int i;
 
       for (i = 0; i < num_actuals && ! must_preallocate; i++)
 	{
 	  if (args[i].partial > 0 && ! args[i].pass_on_stack)
-	    partial_seen = 1;
+	    partial_seen = true;
 	  else if (partial_seen && args[i].reg == 0)
-	    must_preallocate = 1;
+	    must_preallocate = true;
 
 	  if (TYPE_MODE (TREE_TYPE (args[i].tree_value)) == BLKmode
 	      && (TREE_CODE (args[i].tree_value) == CALL_EXPR
@@ -1760,7 +1766,7 @@ finalize_must_preallocate (int must_preallocate, int num_actuals,
 
       if (maybe_ne (args_size->constant, 0)
 	  && maybe_ge (copy_to_evaluate_size * 2, args_size->constant))
-	must_preallocate = 1;
+	must_preallocate = true;
     }
   return must_preallocate;
 }
@@ -2091,7 +2097,7 @@ mem_might_overlap_already_clobbered_arg_p (rtx addr, poly_uint64 size)
 static void
 load_register_parameters (struct arg_data *args, int num_actuals,
 			  rtx *call_fusage, int flags, int is_sibcall,
-			  int *sibcall_failure)
+			  bool *sibcall_failure)
 {
   int i, j;
 
@@ -2216,7 +2222,7 @@ load_register_parameters (struct arg_data *args, int num_actuals,
 		  && const_size != 0
 		  && (mem_might_overlap_already_clobbered_arg_p
 		      (XEXP (args[i].value, 0), const_size)))
-		*sibcall_failure = 1;
+		*sibcall_failure = true;
 
 	      if (const_size % UNITS_PER_WORD == 0
 		  || MEM_ALIGN (mem) % BITS_PER_WORD == 0)
@@ -2264,8 +2270,8 @@ load_register_parameters (struct arg_data *args, int num_actuals,
 	     possible that it did a load from an argument slot that was
 	     already clobbered.  */
 	  if (is_sibcall
-	      && check_sibcall_argument_overlap (before_arg, &args[i], 0))
-	    *sibcall_failure = 1;
+	      && check_sibcall_argument_overlap (before_arg, &args[i], false))
+	    *sibcall_failure = true;
 
 	  /* Handle calls that pass values in multiple non-contiguous
 	     locations.  The Irix 6 ABI has examples of this.  */
@@ -2348,10 +2354,10 @@ combine_pending_stack_adjustment_and_call (poly_int64_pod *adjustment_out,
 /* Scan X expression if it does not dereference any argument slots
    we already clobbered by tail call arguments (as noted in stored_args_map
    bitmap).
-   Return nonzero if X expression dereferences such argument slots,
-   zero otherwise.  */
+   Return true if X expression dereferences such argument slots,
+   false otherwise.  */
 
-static int
+static bool
 check_sibcall_argument_overlap_1 (rtx x)
 {
   RTX_CODE code;
@@ -2359,13 +2365,13 @@ check_sibcall_argument_overlap_1 (rtx x)
   const char *fmt;
 
   if (x == NULL_RTX)
-    return 0;
+    return false;
 
   code = GET_CODE (x);
 
   /* We need not check the operands of the CALL expression itself.  */
   if (code == CALL)
-    return 0;
+    return false;
 
   if (code == MEM)
     return (mem_might_overlap_already_clobbered_arg_p
@@ -2378,28 +2384,28 @@ check_sibcall_argument_overlap_1 (rtx x)
       if (*fmt == 'e')
 	{
 	  if (check_sibcall_argument_overlap_1 (XEXP (x, i)))
-	    return 1;
+	    return true;
 	}
       else if (*fmt == 'E')
 	{
 	  for (j = 0; j < XVECLEN (x, i); j++)
 	    if (check_sibcall_argument_overlap_1 (XVECEXP (x, i, j)))
-	      return 1;
+	      return true;
 	}
     }
-  return 0;
+  return false;
 }
 
 /* Scan sequence after INSN if it does not dereference any argument slots
    we already clobbered by tail call arguments (as noted in stored_args_map
    bitmap).  If MARK_STORED_ARGS_MAP, add stack slots for ARG to
-   stored_args_map bitmap afterwards (when ARG is a register MARK_STORED_ARGS_MAP
-   should be 0).  Return nonzero if sequence after INSN dereferences such argument
-   slots, zero otherwise.  */
+   stored_args_map bitmap afterwards (when ARG is a register
+   MARK_STORED_ARGS_MAP should be false).  Return true if sequence after
+   INSN dereferences such argument slots, false otherwise.  */
 
-static int
+static bool
 check_sibcall_argument_overlap (rtx_insn *insn, struct arg_data *arg,
-				int mark_stored_args_map)
+				bool mark_stored_args_map)
 {
   poly_uint64 low, high;
   unsigned HOST_WIDE_INT const_low, const_high;
@@ -2659,9 +2665,9 @@ expand_call (tree exp, rtx target, int ignore)
      or if we are using the non-reentrant PCC calling convention
      or expecting the value in registers.  */
   poly_int64 struct_value_size = 0;
-  /* Nonzero if called function returns an aggregate in memory PCC style,
+  /* True if called function returns an aggregate in memory PCC style,
      by returning the address of where to find it.  */
-  int pcc_struct_value = 0;
+  bool pcc_struct_value = false;
   rtx struct_value = 0;
 
   /* Number of actual parameters in this call, including struct value addr.  */
@@ -2687,15 +2693,13 @@ expand_call (tree exp, rtx target, int ignore)
   cumulative_args_t args_so_far;
   /* Nonzero if a reg parm has been scanned.  */
   int reg_parm_seen;
-  /* Nonzero if this is an indirect function call.  */
 
-  /* Nonzero if we must avoid push-insns in the args for this call.
+  /* True if we must avoid push-insns in the args for this call.
      If stack space is allocated for register parameters, but not by the
      caller, then it is preallocated in the fixed part of the stack frame.
      So the entire argument block must then be preallocated (i.e., we
      ignore PUSH_ROUNDING in that case).  */
-
-  int must_preallocate = !targetm.calls.push_argument (0);
+  bool must_preallocate = !targetm.calls.push_argument (0);
 
   /* Size of the stack reserved for parameter registers.  */
   int reg_parm_stack_space = 0;
@@ -2805,7 +2809,7 @@ expand_call (tree exp, rtx target, int ignore)
 
   if (! OUTGOING_REG_PARM_STACK_SPACE ((!fndecl ? fntype : TREE_TYPE (fndecl)))
       && reg_parm_stack_space > 0 && targetm.calls.push_argument (0))
-    must_preallocate = 1;
+    must_preallocate = true;
 
   /* Set up a place to return a structure.  */
 
@@ -2817,7 +2821,7 @@ expand_call (tree exp, rtx target, int ignore)
 
 #ifdef PCC_STATIC_STRUCT_RETURN
       {
-	pcc_struct_value = 1;
+	pcc_struct_value = true;
       }
 #else /* not PCC_STATIC_STRUCT_RETURN */
       {
@@ -2989,7 +2993,7 @@ expand_call (tree exp, rtx target, int ignore)
 				   &try_tail_call, CALL_FROM_THUNK_P (exp));
 
   if (args_size.var)
-    must_preallocate = 1;
+    must_preallocate = true;
 
   /* Now make final decision about preallocating stack space.  */
   must_preallocate = finalize_must_preallocate (must_preallocate,
@@ -3114,7 +3118,7 @@ expand_call (tree exp, rtx target, int ignore)
      initial RTL generation is complete.  */
   for (pass = try_tail_call ? 0 : 1; pass < 2; pass++)
     {
-      int sibcall_failure = 0;
+      bool sibcall_failure = false;
       bool normal_failure = false;
       /* We want to emit any pending stack adjustments before the tail
 	 recursion "call".  That way we know any adjustment after the tail
@@ -3500,7 +3504,7 @@ expand_call (tree exp, rtx target, int ignore)
 	          sorry ("passing too large argument on stack");
 		  /* Don't worry about stack clean-up.  */
 		  if (pass == 0)
-		    sibcall_failure = 1;
+		    sibcall_failure = true;
 		  else
 		    normal_failure = true;
 		  continue;
@@ -3511,8 +3515,8 @@ expand_call (tree exp, rtx target, int ignore)
 				 reg_parm_stack_space)
 		  || (pass == 0
 		      && check_sibcall_argument_overlap (before_arg,
-							 &args[i], 1)))
-		sibcall_failure = 1;
+							 &args[i], true)))
+		sibcall_failure = true;
 	      }
 
 	  if (args[i].stack)
@@ -3542,7 +3546,7 @@ expand_call (tree exp, rtx target, int ignore)
 		stack and registers work.  Play it safe and bail out.  */
 	      if (ARGS_GROW_DOWNWARD && !STACK_GROWS_DOWNWARD)
 		{
-		  sibcall_failure = 1;
+		  sibcall_failure = true;
 		  break;
 		}
 
@@ -3551,8 +3555,8 @@ expand_call (tree exp, rtx target, int ignore)
 				 reg_parm_stack_space)
 		  || (pass == 0
 		      && check_sibcall_argument_overlap (before_arg,
-							 &args[i], 1)))
-		sibcall_failure = 1;
+							 &args[i], true)))
+		sibcall_failure = true;
 	    }
 
       bool any_regs = false;
@@ -3596,7 +3600,7 @@ expand_call (tree exp, rtx target, int ignore)
 	 passed in registers.  */
       if (OUTGOING_REG_PARM_STACK_SPACE ((!fndecl ? fntype : TREE_TYPE (fndecl)))
           && !ACCUMULATE_OUTGOING_ARGS
-	  && must_preallocate == 0 && reg_parm_stack_space > 0)
+	  && !must_preallocate && reg_parm_stack_space > 0)
 	anti_adjust_stack (GEN_INT (reg_parm_stack_space));
 
       /* Pass the function the address in which to return a
@@ -3682,8 +3686,8 @@ expand_call (tree exp, rtx target, int ignore)
 	 of the argument setup we probably clobbered our call address.
 	 In that case we can't do sibcalls.  */
       if (pass == 0
-	  && check_sibcall_argument_overlap (after_args, 0, 0))
-	sibcall_failure = 1;
+	  && check_sibcall_argument_overlap (after_args, 0, false))
+	sibcall_failure = true;
 
       /* If a non-BLKmode value is returned at the most significant end
 	 of a register, shift the register right by the appropriate amount
@@ -3697,7 +3701,7 @@ expand_call (tree exp, rtx target, int ignore)
 	  && targetm.calls.return_in_msb (rettype))
 	{
 	  if (shift_return_value (TYPE_MODE (rettype), false, valreg))
-	    sibcall_failure = 1;
+	    sibcall_failure = true;
 	  valreg = gen_rtx_REG (TYPE_MODE (rettype), REGNO (valreg));
 	}
 
@@ -3839,7 +3843,7 @@ expand_call (tree exp, rtx target, int ignore)
 		 Since it is emitted after the call insn, sibcall
 		 optimization cannot be performed in that case.  */
 	      if (MEM_P (target))
-		sibcall_failure = 1;
+		sibcall_failure = true;
 	    }
 	}
       else
@@ -3891,7 +3895,7 @@ expand_call (tree exp, rtx target, int ignore)
 	  highest_outgoing_arg_in_use = initial_highest_arg_in_use;
 	  stack_usage_map = initial_stack_usage_map;
 	  stack_usage_watermark = initial_stack_usage_watermark;
-	  sibcall_failure = 1;
+	  sibcall_failure = true;
 	}
       else if (ACCUMULATE_OUTGOING_ARGS && pass)
 	{
@@ -4129,7 +4133,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value,
   rtx call_fusage = 0;
   rtx mem_value = 0;
   rtx valreg;
-  int pcc_struct_value = 0;
+  bool pcc_struct_value = false;
   poly_int64 struct_value_size = 0;
   int flags;
   int reg_parm_stack_space = 0;
@@ -4198,7 +4202,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value,
 	  rtx pointer_reg
 	    = hard_function_value (build_pointer_type (tfom), 0, 0, 0);
 	  mem_value = gen_rtx_MEM (outmode, pointer_reg);
-	  pcc_struct_value = 1;
+	  pcc_struct_value = true;
 	  if (value == 0)
 	    value = gen_reg_rtx (outmode);
 #else /* not PCC_STATIC_STRUCT_RETURN */
@@ -4883,10 +4887,10 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value,
 
    FNDECL is the declaration of the function we are calling.
 
-   Return nonzero if this arg should cause sibcall failure,
-   zero otherwise.  */
+   Return true if this arg should cause sibcall failure,
+   false otherwise.  */
 
-static int
+static bool
 store_one_arg (struct arg_data *arg, rtx argblock, int flags,
 	       int variable_size ATTRIBUTE_UNUSED, int reg_parm_stack_space)
 {
@@ -4895,10 +4899,10 @@ store_one_arg (struct arg_data *arg, rtx argblock, int flags,
   int partial = 0;
   poly_int64 used = 0;
   poly_int64 lower_bound = 0, upper_bound = 0;
-  int sibcall_failure = 0;
+  bool sibcall_failure = false;
 
   if (TREE_CODE (pval) == ERROR_MARK)
-    return 1;
+    return true;
 
   /* Push a new temporary level for any temporaries we make for
      this argument.  */
@@ -4998,13 +5002,13 @@ store_one_arg (struct arg_data *arg, rtx argblock, int flags,
 
 	 For scalar function arguments stack_usage_map is sufficient to
 	 determine which stack slots must be saved and restored.  Scalar
-	 arguments in general have pass_on_stack == 0.
+	 arguments in general have pass_on_stack == false.
 
 	 If this argument is initialized by a function which takes the
 	 address of the argument (a C++ constructor or a C function
 	 returning a BLKmode structure), then stack_usage_map is
 	 insufficient and expand_call must push the stack around the
-	 function call.  Such arguments have pass_on_stack == 1.
+	 function call.  Such arguments have pass_on_stack == true.
 
 	 Note that it is always safe to set stack_arg_under_construction,
 	 but this generates suboptimal code if set when not needed.  */
@@ -5034,7 +5038,7 @@ store_one_arg (struct arg_data *arg, rtx argblock, int flags,
       && MEM_P (arg->value)
       && mem_might_overlap_already_clobbered_arg_p (XEXP (arg->value, 0),
 						    arg->locate.size.constant))
-    sibcall_failure = 1;
+    sibcall_failure = true;
 
   /* Don't allow anything left on stack from computation
      of argument to alloca.  */
@@ -5097,7 +5101,7 @@ store_one_arg (struct arg_data *arg, rtx argblock, int flags,
 			      argblock, ARGS_SIZE_RTX (arg->locate.offset),
 			      reg_parm_stack_space,
 			      ARGS_SIZE_RTX (arg->locate.alignment_pad), true))
-	sibcall_failure = 1;
+	sibcall_failure = true;
 
       /* Unless this is a partially-in-register argument, the argument is now
 	 in the stack.  */
@@ -5184,17 +5188,17 @@ store_one_arg (struct arg_data *arg, rtx argblock, int flags,
 		     this by making sure that the incoming size is the
 		     same as the outgoing size.  */
 		  if (maybe_ne (arg->locate.size.constant, size_val))
-		    sibcall_failure = 1;
+		    sibcall_failure = true;
 		}
 	      else if (maybe_in_range_p (arg->locate.offset.constant,
 					 i, size_val))
-		sibcall_failure = 1;
+		sibcall_failure = true;
 	      /* Use arg->locate.size.constant instead of size_rtx
 		 because we only care about the part of the argument
 		 on the stack.  */
 	      else if (maybe_in_range_p (i, arg->locate.offset.constant,
 					 arg->locate.size.constant))
-		sibcall_failure = 1;
+		sibcall_failure = true;
 	    }
 	}
 
diff --git a/gcc/calls.h b/gcc/calls.h
index c7f8c5e..46090b4 100644
--- a/gcc/calls.h
+++ b/gcc/calls.h
@@ -112,7 +112,7 @@ public:
 
 extern int flags_from_decl_or_type (const_tree);
 extern int call_expr_flags (const_tree);
-extern int setjmp_call_p (const_tree);
+extern bool setjmp_call_p (const_tree);
 extern bool gimple_maybe_alloca_call_p (const gimple *);
 extern bool gimple_alloca_call_p (const gimple *);
 extern bool alloca_call_p (const_tree);
diff --git a/gcc/common.opt b/gcc/common.opt
index a28ca13..3daec85 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -1662,9 +1662,8 @@ Name(fp_contract_mode) Type(enum fp_contract_mode) UnknownError(unknown floating
 EnumValue
 Enum(fp_contract_mode) String(off) Value(FP_CONTRACT_OFF)
 
-; Not implemented, fall back to conservative FP_CONTRACT_OFF.
 EnumValue
-Enum(fp_contract_mode) String(on) Value(FP_CONTRACT_OFF)
+Enum(fp_contract_mode) String(on) Value(FP_CONTRACT_ON)
 
 EnumValue
 Enum(fp_contract_mode) String(fast) Value(FP_CONTRACT_FAST)
diff --git a/gcc/common/config/avr/avr-common.cc b/gcc/common/config/avr/avr-common.cc
index 2ad0244..2f874c5 100644
--- a/gcc/common/config/avr/avr-common.cc
+++ b/gcc/common/config/avr/avr-common.cc
@@ -29,12 +29,6 @@
 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
 static const struct default_options avr_option_optimization_table[] =
   {
-    // With -fdelete-null-pointer-checks option, the compiler assumes
-    // that dereferencing of a null pointer would halt the program.
-    // For AVR this assumption is not true and a program can safely
-    // dereference null pointers.  Changes made by this option may not
-    // work properly for AVR.  So disable this option.
-    { OPT_LEVELS_ALL, OPT_fdelete_null_pointer_checks, NULL, 0 },
     // The only effect of -fcaller-saves might be that it triggers
     // a frame without need when it tries to be smart around calls.
     { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 },
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index cd04cbd..90118c6 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -7327,6 +7327,36 @@
   [(set_attr "type" "neon_reduc_add<q>")]
 )
 
+;; A common usecase of 64-bit ADDP is to have both operands come from the same
+;; 128-bit vector and produce the pairwise addition results in the lower half.
+;; Split into the 128-bit ADDP form and extract the low half.
+(define_insn_and_split "*aarch64_addp_same_reg<mode>"
+  [(set (match_operand:<VHALF> 0 "register_operand" "=w")
+	(plus:<VHALF>
+	  (vec_select:<VHALF>
+	    (match_operand:VQ_I 1 "register_operand" "w")
+	    (match_operand:VQ_I 2 "vect_par_cnst_even_or_odd_half"))
+	  (vec_select:<VHALF>
+	    (match_dup 1)
+	    (match_operand:VQ_I 3 "vect_par_cnst_even_or_odd_half"))))]
+  "TARGET_SIMD && !rtx_equal_p (operands[2], operands[3])"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    rtx scratch;
+    if (can_create_pseudo_p ())
+      scratch = gen_reg_rtx (<MODE>mode);
+    else
+      scratch = lowpart_subreg (<MODE>mode, operands[0], <VHALF>mode);
+
+    emit_insn (gen_aarch64_addp<mode>_insn (scratch, operands[1], operands[1],
+					    operands[2], operands[3]));
+    emit_move_insn (operands[0], gen_lowpart (<VHALF>mode, scratch));
+    DONE;
+  }
+)
+
 (define_expand "aarch64_addp<mode>"
   [(match_operand:VDQ_I 0 "register_operand")
    (match_operand:VDQ_I 1 "register_operand")
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 2de651a..da5534c 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -1418,64 +1418,79 @@
 ;; Predicated gather loads for 32-bit elements.  Operand 3 is true for
 ;; unsigned extension and false for signed extension.
 (define_insn "mask_gather_load<mode><v_int_container>"
-  [(set (match_operand:SVE_4 0 "register_operand" "=w, w, w, w, w, w")
+  [(set (match_operand:SVE_4 0 "register_operand")
 	(unspec:SVE_4
-	  [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
-	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vgw, rk, rk, rk, rk")
-	   (match_operand:VNx4SI 2 "register_operand" "w, w, w, w, w, w")
-	   (match_operand:DI 3 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
+	  [(match_operand:VNx4BI 5 "register_operand")
+	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>")
+	   (match_operand:VNx4SI 2 "register_operand")
+	   (match_operand:DI 3 "const_int_operand")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>")
 	   (mem:BLK (scratch))]
 	  UNSPEC_LD1_GATHER))]
   "TARGET_SVE"
-  "@
-   ld1<Vesize>\t%0.s, %5/z, [%2.s]
-   ld1<Vesize>\t%0.s, %5/z, [%2.s, #%1]
-   ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
-   ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
-   ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
-   ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5  ]
+     [&w, Z,   w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%2.s]
+     [?w, Z,   0, Ui1, Ui1, Upl] ^
+     [&w, vgw, w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%2.s, #%1]
+     [?w, vgw, 0, Ui1, Ui1, Upl] ^
+     [&w, rk,  w, Z,   Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
+     [?w, rk,  0, Z,   Ui1, Upl] ^
+     [&w, rk,  w, Ui1, Ui1, Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
+     [?w, rk,  0, Ui1, Ui1, Upl] ^
+     [&w, rk,  w, Z,   i,   Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
+     [?w, rk,  0, Z,   i,   Upl] ^
+     [&w, rk,  w, Ui1, i,   Upl] ld1<Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]
+     [?w, rk,  0, Ui1, i,   Upl] ^
+  }
 )
 
 ;; Predicated gather loads for 64-bit elements.  The value of operand 3
 ;; doesn't matter in this case.
 (define_insn "mask_gather_load<mode><v_int_container>"
-  [(set (match_operand:SVE_2 0 "register_operand" "=w, w, w, w")
+  [(set (match_operand:SVE_2 0 "register_operand")
 	(unspec:SVE_2
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
-	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>" "Z, vgd, rk, rk")
-	   (match_operand:VNx2DI 2 "register_operand" "w, w, w, w")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "aarch64_sve_gather_offset_<Vesize>")
+	   (match_operand:VNx2DI 2 "register_operand")
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, Ui1, Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>")
 	   (mem:BLK (scratch))]
 	  UNSPEC_LD1_GATHER))]
   "TARGET_SVE"
-  "@
-   ld1<Vesize>\t%0.d, %5/z, [%2.d]
-   ld1<Vesize>\t%0.d, %5/z, [%2.d, #%1]
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d]
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, Z,   w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%2.d]
+     [?w, Z,   0, i, Ui1, Upl] ^
+     [&w, vgd, w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%2.d, #%1]
+     [?w, vgd, 0, i, Ui1, Upl] ^
+     [&w, rk,  w, i, Ui1, Upl] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d]
+     [?w, rk,  0, i, Ui1, Upl] ^
+     [&w, rk,  w, i, i,   Upl] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]
+     [?w, rk,  0, i, i,   Upl] ^
+  }
 )
 
 ;; Likewise, but with the offset being extended from 32 bits.
 (define_insn_and_rewrite "*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked"
-  [(set (match_operand:SVE_2 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_2 0 "register_operand")
 	(unspec:SVE_2
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-	   (match_operand:DI 1 "register_operand" "rk, rk")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "register_operand")
 	   (unspec:VNx2DI
 	     [(match_operand 6)
 	      (ANY_EXTEND:VNx2DI
-		(match_operand:VNx2SI 2 "register_operand" "w, w"))]
+		(match_operand:VNx2SI 2 "register_operand"))]
 	     UNSPEC_PRED_X)
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>")
 	   (mem:BLK (scratch))]
 	  UNSPEC_LD1_GATHER))]
   "TARGET_SVE"
-  "@
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, <su>xtw]
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, <su>xtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, <su>xtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, <su>xtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1485,24 +1500,27 @@
 ;; Likewise, but with the offset being truncated to 32 bits and then
 ;; sign-extended.
 (define_insn_and_rewrite "*mask_gather_load<mode><v_int_container>_sxtw"
-  [(set (match_operand:SVE_2 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_2 0 "register_operand")
 	(unspec:SVE_2
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-	   (match_operand:DI 1 "register_operand" "rk, rk")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "register_operand")
 	   (unspec:VNx2DI
 	     [(match_operand 6)
 	      (sign_extend:VNx2DI
 		(truncate:VNx2SI
-		  (match_operand:VNx2DI 2 "register_operand" "w, w")))]
+		  (match_operand:VNx2DI 2 "register_operand")))]
 	     UNSPEC_PRED_X)
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>")
 	   (mem:BLK (scratch))]
 	  UNSPEC_LD1_GATHER))]
   "TARGET_SVE"
-  "@
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1512,21 +1530,24 @@
 ;; Likewise, but with the offset being truncated to 32 bits and then
 ;; zero-extended.
 (define_insn "*mask_gather_load<mode><v_int_container>_uxtw"
-  [(set (match_operand:SVE_2 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_2 0 "register_operand")
 	(unspec:SVE_2
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-	   (match_operand:DI 1 "register_operand" "rk, rk")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "register_operand")
 	   (and:VNx2DI
-	     (match_operand:VNx2DI 2 "register_operand" "w, w")
+	     (match_operand:VNx2DI 2 "register_operand")
 	     (match_operand:VNx2DI 6 "aarch64_sve_uxtw_immediate"))
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>" "Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_<Vesize>")
 	   (mem:BLK (scratch))]
 	  UNSPEC_LD1_GATHER))]
   "TARGET_SVE"
-  "@
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
-   ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ld1<Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
 )
 
 ;; -------------------------------------------------------------------------
@@ -1544,27 +1565,34 @@
 ;; Predicated extending gather loads for 32-bit elements.  Operand 3 is
 ;; true for unsigned extension and false for signed extension.
 (define_insn_and_rewrite "@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>"
-  [(set (match_operand:SVE_4HSI 0 "register_operand" "=w, w, w, w, w, w")
+  [(set (match_operand:SVE_4HSI 0 "register_operand")
 	(unspec:SVE_4HSI
-	  [(match_operand:VNx4BI 6 "general_operand" "UplDnm, UplDnm, UplDnm, UplDnm, UplDnm, UplDnm")
+	  [(match_operand:VNx4BI 6 "general_operand")
 	   (ANY_EXTEND:SVE_4HSI
 	     (unspec:SVE_4BHI
-	       [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
-		(match_operand:DI 1 "aarch64_sve_gather_offset_<SVE_4BHI:Vesize>" "Z, vg<SVE_4BHI:Vesize>, rk, rk, rk, rk")
-		(match_operand:VNx4SI 2 "register_operand" "w, w, w, w, w, w")
-		(match_operand:DI 3 "const_int_operand" "Ui1, Ui1, Z, Ui1, Z, Ui1")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_4BHI:Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
+	       [(match_operand:VNx4BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_sve_gather_offset_<SVE_4BHI:Vesize>")
+		(match_operand:VNx4SI 2 "register_operand")
+		(match_operand:DI 3 "const_int_operand")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_4BHI:Vesize>")
 		(mem:BLK (scratch))]
 	       UNSPEC_LD1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE && (~<SVE_4HSI:narrower_mask> & <SVE_4BHI:self_mask>) == 0"
-  "@
-   ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%2.s]
-   ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%2.s, #%1]
-   ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
-   ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
-   ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
-   ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5, 6]
+     [&w, Z,                   w, Ui1, Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%2.s]
+     [?w, Z,                   0, Ui1, Ui1, Upl, UplDnm] ^
+     [&w, vg<SVE_4BHI:Vesize>, w, Ui1, Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%2.s, #%1]
+     [?w, vg<SVE_4BHI:Vesize>, 0, Ui1, Ui1, Upl, UplDnm] ^
+     [&w, rk,                  w, Z,   Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
+     [?w, rk,                  0, Z,   Ui1, Upl, UplDnm] ^
+     [&w, rk,                  w, Ui1, Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
+     [?w, rk,                  0, Ui1, Ui1, Upl, UplDnm] ^
+     [&w, rk,                  w, Z,   i,   Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
+     [?w, rk,                  0, Z,   i,   Upl, UplDnm] ^
+     [&w, rk,                  w, Ui1, i,   Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_4BHI:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]
+     [?w, rk,                  0, Ui1, i,   Upl, UplDnm] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx4BImode);
@@ -1574,25 +1602,30 @@
 ;; Predicated extending gather loads for 64-bit elements.  The value of
 ;; operand 3 doesn't matter in this case.
 (define_insn_and_rewrite "@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>"
-  [(set (match_operand:SVE_2HSDI 0 "register_operand" "=w, w, w, w")
+  [(set (match_operand:SVE_2HSDI 0 "register_operand")
 	(unspec:SVE_2HSDI
-	  [(match_operand:VNx2BI 6 "general_operand" "UplDnm, UplDnm, UplDnm, UplDnm")
+	  [(match_operand:VNx2BI 6 "general_operand")
 	   (ANY_EXTEND:SVE_2HSDI
 	     (unspec:SVE_2BHSI
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
-		(match_operand:DI 1 "aarch64_sve_gather_offset_<SVE_2BHSI:Vesize>" "Z, vg<SVE_2BHSI:Vesize>, rk, rk")
-		(match_operand:VNx2DI 2 "register_operand" "w, w, w, w")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_sve_gather_offset_<SVE_2BHSI:Vesize>")
+		(match_operand:VNx2DI 2 "register_operand")
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>" "Ui1, Ui1, Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>")
 		(mem:BLK (scratch))]
 	       UNSPEC_LD1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE && (~<SVE_2HSDI:narrower_mask> & <SVE_2BHSI:self_mask>) == 0"
-  "@
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%2.d]
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%2.d, #%1]
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d]
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5, 6]
+     [&w, Z,                    w, i, Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%2.d]
+     [?w, Z,                    0, i, Ui1, Upl, UplDnm] ^
+     [&w, vg<SVE_2BHSI:Vesize>, w, i, Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%2.d, #%1]
+     [?w, vg<SVE_2BHSI:Vesize>, 0, i, Ui1, Upl, UplDnm] ^
+     [&w, rk,                   w, i, Ui1, Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d]
+     [?w, rk,                   0, i, Ui1, Upl, UplDnm] ^
+     [&w, rk,                   w, i, i,   Upl, UplDnm] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]
+     [?w, rk,                   0, i, i,   Upl, UplDnm] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1601,27 +1634,30 @@
 
 ;; Likewise, but with the offset being extended from 32 bits.
 (define_insn_and_rewrite "*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked"
-  [(set (match_operand:SVE_2HSDI 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_2HSDI 0 "register_operand")
 	(unspec:SVE_2HSDI
 	  [(match_operand 6)
 	   (ANY_EXTEND:SVE_2HSDI
 	     (unspec:SVE_2BHSI
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-		(match_operand:DI 1 "aarch64_reg_or_zero" "rk, rk")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_reg_or_zero")
 		(unspec:VNx2DI
 		  [(match_operand 7)
 		   (ANY_EXTEND2:VNx2DI
-		     (match_operand:VNx2SI 2 "register_operand" "w, w"))]
+		     (match_operand:VNx2SI 2 "register_operand"))]
 		  UNSPEC_PRED_X)
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>" "Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>")
 		(mem:BLK (scratch))]
 	       UNSPEC_LD1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE && (~<SVE_2HSDI:narrower_mask> & <SVE_2BHSI:self_mask>) == 0"
-  "@
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, <ANY_EXTEND2:su>xtw]
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, <ANY_EXTEND2:su>xtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, <ANY_EXTEND2:su>xtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, <ANY_EXTEND2:su>xtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& (!CONSTANT_P (operands[6]) || !CONSTANT_P (operands[7]))"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1632,28 +1668,31 @@
 ;; Likewise, but with the offset being truncated to 32 bits and then
 ;; sign-extended.
 (define_insn_and_rewrite "*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>_sxtw"
-  [(set (match_operand:SVE_2HSDI 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_2HSDI 0 "register_operand")
 	(unspec:SVE_2HSDI
 	  [(match_operand 6)
 	   (ANY_EXTEND:SVE_2HSDI
 	     (unspec:SVE_2BHSI
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-		(match_operand:DI 1 "aarch64_reg_or_zero" "rk, rk")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_reg_or_zero")
 		(unspec:VNx2DI
 		  [(match_operand 7)
 		   (sign_extend:VNx2DI
 		     (truncate:VNx2SI
-		       (match_operand:VNx2DI 2 "register_operand" "w, w")))]
+		       (match_operand:VNx2DI 2 "register_operand")))]
 		  UNSPEC_PRED_X)
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>" "Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>")
 		(mem:BLK (scratch))]
 	       UNSPEC_LD1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE && (~<SVE_2HSDI:narrower_mask> & <SVE_2BHSI:self_mask>) == 0"
-  "@
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& (!CONSTANT_P (operands[6]) || !CONSTANT_P (operands[7]))"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1664,25 +1703,28 @@
 ;; Likewise, but with the offset being truncated to 32 bits and then
 ;; zero-extended.
 (define_insn_and_rewrite "*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>_uxtw"
-  [(set (match_operand:SVE_2HSDI 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_2HSDI 0 "register_operand")
 	(unspec:SVE_2HSDI
 	  [(match_operand 7)
 	   (ANY_EXTEND:SVE_2HSDI
 	     (unspec:SVE_2BHSI
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-		(match_operand:DI 1 "aarch64_reg_or_zero" "rk, rk")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_reg_or_zero")
 		(and:VNx2DI
-		  (match_operand:VNx2DI 2 "register_operand" "w, w")
+		  (match_operand:VNx2DI 2 "register_operand")
 		  (match_operand:VNx2DI 6 "aarch64_sve_uxtw_immediate"))
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>" "Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<SVE_2BHSI:Vesize>")
 		(mem:BLK (scratch))]
 	       UNSPEC_LD1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE && (~<SVE_2HSDI:narrower_mask> & <SVE_2BHSI:self_mask>) == 0"
-  "@
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
-   ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ld1<ANY_EXTEND:s><SVE_2BHSI:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& !CONSTANT_P (operands[7])"
   {
     operands[7] = CONSTM1_RTX (VNx2BImode);
@@ -1700,68 +1742,83 @@
 ;; Predicated first-faulting gather loads for 32-bit elements.  Operand
 ;; 3 is true for unsigned extension and false for signed extension.
 (define_insn "@aarch64_ldff1_gather<mode>"
-  [(set (match_operand:SVE_FULL_S 0 "register_operand" "=w, w, w, w, w, w")
+  [(set (match_operand:SVE_FULL_S 0 "register_operand")
 	(unspec:SVE_FULL_S
-	  [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
-	   (match_operand:DI 1 "aarch64_sve_gather_offset_w" "Z, vgw, rk, rk, rk, rk")
-	   (match_operand:VNx4SI 2 "register_operand" "w, w, w, w, w, w")
-	   (match_operand:DI 3 "const_int_operand" "i, i, Z, Ui1, Z, Ui1")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_w" "Ui1, Ui1, Ui1, Ui1, i, i")
+	  [(match_operand:VNx4BI 5 "register_operand")
+	   (match_operand:DI 1 "aarch64_sve_gather_offset_w")
+	   (match_operand:VNx4SI 2 "register_operand")
+	   (match_operand:DI 3 "const_int_operand")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_w")
 	   (mem:BLK (scratch))
 	   (reg:VNx16BI FFRT_REGNUM)]
 	  UNSPEC_LDFF1_GATHER))]
   "TARGET_SVE"
-  "@
-   ldff1w\t%0.s, %5/z, [%2.s]
-   ldff1w\t%0.s, %5/z, [%2.s, #%1]
-   ldff1w\t%0.s, %5/z, [%1, %2.s, sxtw]
-   ldff1w\t%0.s, %5/z, [%1, %2.s, uxtw]
-   ldff1w\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
-   ldff1w\t%0.s, %5/z, [%1, %2.s, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5  ]
+     [&w, Z,   w, i,   Ui1, Upl] ldff1w\t%0.s, %5/z, [%2.s]
+     [?w, Z,   0, i,   Ui1, Upl] ^
+     [&w, vgw, w, i,   Ui1, Upl] ldff1w\t%0.s, %5/z, [%2.s, #%1]
+     [?w, vgw, 0, i,   Ui1, Upl] ^
+     [&w, rk,  w, Z,   Ui1, Upl] ldff1w\t%0.s, %5/z, [%1, %2.s, sxtw]
+     [?w, rk,  0, Z,   Ui1, Upl] ^
+     [&w, rk,  w, Ui1, Ui1, Upl] ldff1w\t%0.s, %5/z, [%1, %2.s, uxtw]
+     [?w, rk,  0, Ui1, Ui1, Upl] ^
+     [&w, rk,  w, Z,   i,   Upl] ldff1w\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
+     [?w, rk,  0, Z,   i,   Upl] ^
+     [&w, rk,  w, Ui1, i,   Upl] ldff1w\t%0.s, %5/z, [%1, %2.s, uxtw %p4]
+     [?w, rk,  0, Ui1, i,   Upl] ^
+  }
 )
 
 ;; Predicated first-faulting gather loads for 64-bit elements.  The value
 ;; of operand 3 doesn't matter in this case.
 (define_insn "@aarch64_ldff1_gather<mode>"
-  [(set (match_operand:SVE_FULL_D 0 "register_operand" "=w, w, w, w")
+  [(set (match_operand:SVE_FULL_D 0 "register_operand")
 	(unspec:SVE_FULL_D
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
-	   (match_operand:DI 1 "aarch64_sve_gather_offset_d" "Z, vgd, rk, rk")
-	   (match_operand:VNx2DI 2 "register_operand" "w, w, w, w")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "aarch64_sve_gather_offset_d")
+	   (match_operand:VNx2DI 2 "register_operand")
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_d" "Ui1, Ui1, Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_d")
 	   (mem:BLK (scratch))
 	   (reg:VNx16BI FFRT_REGNUM)]
 	  UNSPEC_LDFF1_GATHER))]
   "TARGET_SVE"
-  "@
-   ldff1d\t%0.d, %5/z, [%2.d]
-   ldff1d\t%0.d, %5/z, [%2.d, #%1]
-   ldff1d\t%0.d, %5/z, [%1, %2.d]
-   ldff1d\t%0.d, %5/z, [%1, %2.d, lsl %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5 ]
+     [&w, Z,   w, i, Ui1, Upl ] ldff1d\t%0.d, %5/z, [%2.d]
+     [?w, Z,   0, i, Ui1, Upl ] ^
+     [&w, vgd, w, i, Ui1, Upl ] ldff1d\t%0.d, %5/z, [%2.d, #%1]
+     [?w, vgd, 0, i, Ui1, Upl ] ^
+     [&w, rk,  w, i, Ui1, Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d]
+     [?w, rk,  0, i, Ui1, Upl ] ^
+     [&w, rk,  w, i, i,   Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, lsl %p4]
+     [?w, rk,  0, i, i,   Upl ] ^
+  }
 )
 
 ;; Likewise, but with the offset being sign-extended from 32 bits.
 (define_insn_and_rewrite "*aarch64_ldff1_gather<mode>_sxtw"
-  [(set (match_operand:SVE_FULL_D 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_FULL_D 0 "register_operand")
 	(unspec:SVE_FULL_D
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-	   (match_operand:DI 1 "register_operand" "rk, rk")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "register_operand")
 	   (unspec:VNx2DI
 	     [(match_operand 6)
 	      (sign_extend:VNx2DI
 		(truncate:VNx2SI
-		  (match_operand:VNx2DI 2 "register_operand" "w, w")))]
+		  (match_operand:VNx2DI 2 "register_operand")))]
 	     UNSPEC_PRED_X)
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_d" "Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_d")
 	   (mem:BLK (scratch))
 	   (reg:VNx16BI FFRT_REGNUM)]
 	  UNSPEC_LDFF1_GATHER))]
   "TARGET_SVE"
-  "@
-   ldff1d\t%0.d, %5/z, [%1, %2.d, sxtw]
-   ldff1d\t%0.d, %5/z, [%1, %2.d, sxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, sxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, sxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1770,22 +1827,25 @@
 
 ;; Likewise, but with the offset being zero-extended from 32 bits.
 (define_insn "*aarch64_ldff1_gather<mode>_uxtw"
-  [(set (match_operand:SVE_FULL_D 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_FULL_D 0 "register_operand")
 	(unspec:SVE_FULL_D
-	  [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-	   (match_operand:DI 1 "register_operand" "rk, rk")
+	  [(match_operand:VNx2BI 5 "register_operand")
+	   (match_operand:DI 1 "register_operand")
 	   (and:VNx2DI
-	     (match_operand:VNx2DI 2 "register_operand" "w, w")
+	     (match_operand:VNx2DI 2 "register_operand")
 	     (match_operand:VNx2DI 6 "aarch64_sve_uxtw_immediate"))
 	   (match_operand:DI 3 "const_int_operand")
-	   (match_operand:DI 4 "aarch64_gather_scale_operand_d" "Ui1, i")
+	   (match_operand:DI 4 "aarch64_gather_scale_operand_d")
 	   (mem:BLK (scratch))
 	   (reg:VNx16BI FFRT_REGNUM)]
 	  UNSPEC_LDFF1_GATHER))]
   "TARGET_SVE"
-  "@
-   ldff1d\t%0.d, %5/z, [%1, %2.d, uxtw]
-   ldff1d\t%0.d, %5/z, [%1, %2.d, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, uxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, uxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
 )
 
 ;; -------------------------------------------------------------------------
@@ -1803,28 +1863,35 @@
 ;; Predicated extending first-faulting gather loads for 32-bit elements.
 ;; Operand 3 is true for unsigned extension and false for signed extension.
 (define_insn_and_rewrite "@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode><VNx4_NARROW:mode>"
-  [(set (match_operand:VNx4_WIDE 0 "register_operand" "=w, w, w, w, w, w")
+  [(set (match_operand:VNx4_WIDE 0 "register_operand")
 	(unspec:VNx4_WIDE
-	  [(match_operand:VNx4BI 6 "general_operand" "UplDnm, UplDnm, UplDnm, UplDnm, UplDnm, UplDnm")
+	  [(match_operand:VNx4BI 6 "general_operand")
 	   (ANY_EXTEND:VNx4_WIDE
 	     (unspec:VNx4_NARROW
-	       [(match_operand:VNx4BI 5 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
-		(match_operand:DI 1 "aarch64_sve_gather_offset_<VNx4_NARROW:Vesize>" "Z, vg<VNx4_NARROW:Vesize>, rk, rk, rk, rk")
-		(match_operand:VNx4_WIDE 2 "register_operand" "w, w, w, w, w, w")
-		(match_operand:DI 3 "const_int_operand" "i, i, Z, Ui1, Z, Ui1")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx4_NARROW:Vesize>" "Ui1, Ui1, Ui1, Ui1, i, i")
+	       [(match_operand:VNx4BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_sve_gather_offset_<VNx4_NARROW:Vesize>")
+		(match_operand:VNx4_WIDE 2 "register_operand")
+		(match_operand:DI 3 "const_int_operand")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx4_NARROW:Vesize>")
 		(mem:BLK (scratch))
 		(reg:VNx16BI FFRT_REGNUM)]
 	       UNSPEC_LDFF1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE"
-  "@
-   ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%2.s]
-   ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%2.s, #%1]
-   ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
-   ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
-   ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
-   ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5, 6]
+     [&w, Z,                      w, i,   Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%2.s]
+     [?w, Z,                      0, i,   Ui1, Upl, UplDnm] ^
+     [&w, vg<VNx4_NARROW:Vesize>, w, i,   Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%2.s, #%1]
+     [?w, vg<VNx4_NARROW:Vesize>, 0, i,   Ui1, Upl, UplDnm] ^
+     [&w, rk,                     w, Z,   Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw]
+     [?w, rk,                     0, Z,   Ui1, Upl, UplDnm] ^
+     [&w, rk,                     w, Ui1, Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw]
+     [?w, rk,                     0, Ui1, Ui1, Upl, UplDnm] ^
+     [&w, rk,                     w, Z,   i,   Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, sxtw %p4]
+     [?w, rk,                     0, Z,   i,   Upl, UplDnm] ^
+     [&w, rk,                     w, Ui1, i,   Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx4_NARROW:Vesize>\t%0.s, %5/z, [%1, %2.s, uxtw %p4]
+     [?w, rk,                     0, Ui1, i,   Upl, UplDnm] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx4BImode);
@@ -1834,26 +1901,31 @@
 ;; Predicated extending first-faulting gather loads for 64-bit elements.
 ;; The value of operand 3 doesn't matter in this case.
 (define_insn_and_rewrite "@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>"
-  [(set (match_operand:VNx2_WIDE 0 "register_operand" "=w, w, w, w")
+  [(set (match_operand:VNx2_WIDE 0 "register_operand")
 	(unspec:VNx2_WIDE
-	  [(match_operand:VNx2BI 6 "general_operand" "UplDnm, UplDnm, UplDnm, UplDnm")
+	  [(match_operand:VNx2BI 6 "general_operand")
 	   (ANY_EXTEND:VNx2_WIDE
 	     (unspec:VNx2_NARROW
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl, Upl, Upl")
-		(match_operand:DI 1 "aarch64_sve_gather_offset_<VNx2_NARROW:Vesize>" "Z, vg<VNx2_NARROW:Vesize>, rk, rk")
-		(match_operand:VNx2_WIDE 2 "register_operand" "w, w, w, w")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_sve_gather_offset_<VNx2_NARROW:Vesize>")
+		(match_operand:VNx2_WIDE 2 "register_operand")
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx2_NARROW:Vesize>" "Ui1, Ui1, Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx2_NARROW:Vesize>")
 		(mem:BLK (scratch))
 		(reg:VNx16BI FFRT_REGNUM)]
 	       UNSPEC_LDFF1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE"
-  "@
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%2.d]
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%2.d, #%1]
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d]
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5, 6]
+     [&w, Z,                      w, i, Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%2.d]
+     [?w, Z,                      0, i, Ui1, Upl, UplDnm] ^
+     [&w, vg<VNx2_NARROW:Vesize>, w, i, Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%2.d, #%1]
+     [?w, vg<VNx2_NARROW:Vesize>, 0, i, Ui1, Upl, UplDnm] ^
+     [&w, rk,                     w, i, Ui1, Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d]
+     [?w, rk,                     0, i, Ui1, Upl, UplDnm] ^
+     [&w, rk,                     w, i, i,   Upl, UplDnm] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, lsl %p4]
+     [?w, rk,                     w, i, i,   Upl, UplDnm] ^
+  }
   "&& !CONSTANT_P (operands[6])"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1862,29 +1934,32 @@
 
 ;; Likewise, but with the offset being sign-extended from 32 bits.
 (define_insn_and_rewrite "*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>_sxtw"
-  [(set (match_operand:VNx2_WIDE 0 "register_operand" "=w, w")
+  [(set (match_operand:VNx2_WIDE 0 "register_operand")
 	(unspec:VNx2_WIDE
 	  [(match_operand 6)
 	   (ANY_EXTEND:VNx2_WIDE
 	     (unspec:VNx2_NARROW
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-		(match_operand:DI 1 "aarch64_reg_or_zero" "rk, rk")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_reg_or_zero")
 		(unspec:VNx2DI
 		  [(match_operand 7)
 		   (sign_extend:VNx2DI
 		     (truncate:VNx2SI
-		       (match_operand:VNx2DI 2 "register_operand" "w, w")))]
+		       (match_operand:VNx2DI 2 "register_operand")))]
 		  UNSPEC_PRED_X)
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx2_NARROW:Vesize>" "Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx2_NARROW:Vesize>")
 		(mem:BLK (scratch))
 		(reg:VNx16BI FFRT_REGNUM)]
 	       UNSPEC_LDFF1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE"
-  "@
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, sxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& (!CONSTANT_P (operands[6]) || !CONSTANT_P (operands[7]))"
   {
     operands[6] = CONSTM1_RTX (VNx2BImode);
@@ -1894,26 +1969,29 @@
 
 ;; Likewise, but with the offset being zero-extended from 32 bits.
 (define_insn_and_rewrite "*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode><VNx2_NARROW:mode>_uxtw"
-  [(set (match_operand:VNx2_WIDE 0 "register_operand" "=w, w")
+  [(set (match_operand:VNx2_WIDE 0 "register_operand")
 	(unspec:VNx2_WIDE
 	  [(match_operand 7)
 	   (ANY_EXTEND:VNx2_WIDE
 	     (unspec:VNx2_NARROW
-	       [(match_operand:VNx2BI 5 "register_operand" "Upl, Upl")
-		(match_operand:DI 1 "aarch64_reg_or_zero" "rk, rk")
+	       [(match_operand:VNx2BI 5 "register_operand")
+		(match_operand:DI 1 "aarch64_reg_or_zero")
 		(and:VNx2DI
-		  (match_operand:VNx2DI 2 "register_operand" "w, w")
+		  (match_operand:VNx2DI 2 "register_operand")
 		  (match_operand:VNx2DI 6 "aarch64_sve_uxtw_immediate"))
 		(match_operand:DI 3 "const_int_operand")
-		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx2_NARROW:Vesize>" "Ui1, i")
+		(match_operand:DI 4 "aarch64_gather_scale_operand_<VNx2_NARROW:Vesize>")
 		(mem:BLK (scratch))
 		(reg:VNx16BI FFRT_REGNUM)]
 	       UNSPEC_LDFF1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE"
-  "@
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
-   ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]"
+  {@ [cons: =0, 1, 2, 3, 4, 5]
+     [&w, rk, w, i, Ui1, Upl ] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw]
+     [?w, rk, 0, i, Ui1, Upl ] ^
+     [&w, rk, w, i, i,   Upl ] ldff1<ANY_EXTEND:s><VNx2_NARROW:Vesize>\t%0.d, %5/z, [%1, %2.d, uxtw %p4]
+     [?w, rk, 0, i, i,   Upl ] ^
+  }
   "&& !CONSTANT_P (operands[7])"
   {
     operands[7] = CONSTM1_RTX (VNx2BImode);
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index da8a424..7a77e9b 100644
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -102,37 +102,43 @@
 
 ;; Non-extending loads.
 (define_insn "@aarch64_gather_ldnt<mode>"
-  [(set (match_operand:SVE_FULL_SD 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_FULL_SD 0 "register_operand")
 	(unspec:SVE_FULL_SD
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-	   (match_operand:DI 2 "aarch64_reg_or_zero" "Z, r")
-	   (match_operand:<V_INT_EQUIV> 3 "register_operand" "w, w")
+	  [(match_operand:<VPRED> 1 "register_operand")
+	   (match_operand:DI 2 "aarch64_reg_or_zero")
+	   (match_operand:<V_INT_EQUIV> 3 "register_operand")
 	   (mem:BLK (scratch))]
 	  UNSPEC_LDNT1_GATHER))]
   "TARGET_SVE2"
-  "@
-   ldnt1<Vesize>\t%0.<Vetype>, %1/z, [%3.<Vetype>]
-   ldnt1<Vesize>\t%0.<Vetype>, %1/z, [%3.<Vetype>, %2]"
+  {@ [cons: =0, 1, 2, 3]
+     [&w, Upl, Z, w    ] ldnt1<Vesize>\t%0.<Vetype>, %1/z, [%3.<Vetype>]
+     [?w, Upl, Z, 0    ] ^
+     [&w, Upl, r, w    ] ldnt1<Vesize>\t%0.<Vetype>, %1/z, [%3.<Vetype>, %2]
+     [?w, Upl, r, 0    ] ^
+  }
 )
 
 ;; Extending loads.
 (define_insn_and_rewrite "@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode><SVE_PARTIAL_I:mode>"
-  [(set (match_operand:SVE_FULL_SDI 0 "register_operand" "=w, w")
+  [(set (match_operand:SVE_FULL_SDI 0 "register_operand")
 	(unspec:SVE_FULL_SDI
-	  [(match_operand:<SVE_FULL_SDI:VPRED> 4 "general_operand" "UplDnm, UplDnm")
+	  [(match_operand:<SVE_FULL_SDI:VPRED> 4 "general_operand")
 	   (ANY_EXTEND:SVE_FULL_SDI
 	     (unspec:SVE_PARTIAL_I
-	       [(match_operand:<SVE_FULL_SDI:VPRED> 1 "register_operand" "Upl, Upl")
-		(match_operand:DI 2 "aarch64_reg_or_zero" "Z, r")
-		(match_operand:<SVE_FULL_SDI:V_INT_EQUIV> 3 "register_operand" "w, w")
+	       [(match_operand:<SVE_FULL_SDI:VPRED> 1 "register_operand")
+		(match_operand:DI 2 "aarch64_reg_or_zero")
+		(match_operand:<SVE_FULL_SDI:V_INT_EQUIV> 3 "register_operand")
 		(mem:BLK (scratch))]
 	       UNSPEC_LDNT1_GATHER))]
 	  UNSPEC_PRED_X))]
   "TARGET_SVE2
    && (~<SVE_FULL_SDI:narrower_mask> & <SVE_PARTIAL_I:self_mask>) == 0"
-  "@
-   ldnt1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_SDI:Vetype>, %1/z, [%3.<SVE_FULL_SDI:Vetype>]
-   ldnt1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_SDI:Vetype>, %1/z, [%3.<SVE_FULL_SDI:Vetype>, %2]"
+  {@ [cons: =0, 1, 2, 3, 4]
+     [&w, Upl, Z, w, UplDnm] ldnt1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_SDI:Vetype>, %1/z, [%3.<SVE_FULL_SDI:Vetype>]
+     [?w, Upl, Z, 0, UplDnm] ^
+     [&w, Upl, r, w, UplDnm] ldnt1<ANY_EXTEND:s><SVE_PARTIAL_I:Vesize>\t%0.<SVE_FULL_SDI:Vetype>, %1/z, [%3.<SVE_FULL_SDI:Vetype>, %2]
+     [?w, Upl, r, 0, UplDnm] ^
+  }
   "&& !CONSTANT_P (operands[4])"
   {
     operands[4] = CONSTM1_RTX (<SVE_FULL_SDI:VPRED>mode);
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index df37bde..b99f12c 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -9664,6 +9664,16 @@ aarch64_stack_clash_protection_alloca_probe_range (void)
   return STACK_CLASH_CALLER_GUARD;
 }
 
+/* Emit a stack tie that acts as a scheduling barrier for all previous and
+   subsequent memory accesses and that requires the stack pointer and REG
+   to have their current values.  REG can be stack_pointer_rtx if no
+   other register's value needs to be fixed.  */
+
+static void
+aarch64_emit_stack_tie (rtx reg)
+{
+  emit_insn (gen_stack_tie (reg, gen_int_mode (REGNO (reg), DImode)));
+}
 
 /* Allocate POLY_SIZE bytes of stack space using TEMP1 and TEMP2 as scratch
    registers.  If POLY_SIZE is not large enough to require a probe this function
@@ -9776,7 +9786,7 @@ aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2,
 	     the instruction.  */
 	  rtx stack_ptr_copy = gen_rtx_REG (Pmode, STACK_CLASH_SVE_CFA_REGNUM);
 	  emit_move_insn (stack_ptr_copy, stack_pointer_rtx);
-	  emit_insn (gen_stack_tie (stack_ptr_copy, stack_pointer_rtx));
+	  aarch64_emit_stack_tie (stack_ptr_copy);
 
 	  /* We want the CFA independent of the stack pointer for the
 	     duration of the loop.  */
@@ -10145,7 +10155,7 @@ aarch64_expand_prologue (void)
 	  aarch64_add_cfa_expression (insn, regno_reg_rtx[reg1],
 				      hard_frame_pointer_rtx, 0);
 	}
-      emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
+      aarch64_emit_stack_tie (hard_frame_pointer_rtx);
     }
 
   aarch64_save_callee_saves (saved_regs_offset, R0_REGNUM, R30_REGNUM,
@@ -10248,7 +10258,7 @@ aarch64_expand_epilogue (bool for_sibcall)
       || cfun->calls_alloca
       || crtl->calls_eh_return)
     {
-      emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+      aarch64_emit_stack_tie (stack_pointer_rtx);
       need_barrier_p = false;
     }
 
@@ -10287,7 +10297,7 @@ aarch64_expand_epilogue (bool for_sibcall)
 				callee_adjust != 0, &cfi_ops);
 
   if (need_barrier_p)
-    emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+    aarch64_emit_stack_tie (stack_pointer_rtx);
 
   if (callee_adjust != 0)
     aarch64_pop_regs (reg1, reg2, callee_adjust, &cfi_ops);
@@ -16256,7 +16266,8 @@ aarch64_vector_costs::analyze_loop_vinfo (loop_vec_info loop_vinfo)
       unsigned int num_masks = 0;
       rgroup_controls *rgm;
       unsigned int num_vectors_m1;
-      FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo), num_vectors_m1, rgm)
+      FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo).rgc_vec,
+			num_vectors_m1, rgm)
 	if (rgm->type)
 	  num_masks += num_vectors_m1 + 1;
       for (auto &ops : m_ops)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index ac39a4d..01cf989 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -366,7 +366,7 @@
 ;; As a convenience, "fp_q" means "fp" + the ability to move between
 ;; Q registers and is equivalent to "simd".
 
-(define_enum "arches" [ any rcpc8_4 fp fp_q simd sve fp16])
+(define_enum "arches" [ any rcpc8_4 fp fp_q simd nosimd sve fp16])
 
 (define_enum_attr "arch" "arches" (const_string "any"))
 
@@ -397,6 +397,9 @@
 	(and (eq_attr "arch" "fp_q, simd")
 	     (match_test "TARGET_SIMD"))
 
+	(and (eq_attr "arch" "nosimd")
+	     (match_test "!TARGET_SIMD"))
+
 	(and (eq_attr "arch" "fp16")
 	     (match_test "TARGET_FP_F16INST"))
 
@@ -1206,26 +1209,27 @@
 )
 
 (define_insn "*mov<mode>_aarch64"
-  [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r,    w,r  ,r,w, m,m,r,w,w")
-	(match_operand:SHORT 1 "aarch64_mov_operand"  " r,M,D<hq>,Usv,m,m,rZ,w,w,rZ,w"))]
+  [(set (match_operand:SHORT 0 "nonimmediate_operand")
+	(match_operand:SHORT 1 "aarch64_mov_operand"))]
   "(register_operand (operands[0], <MODE>mode)
     || aarch64_reg_or_zero (operands[1], <MODE>mode))"
-  "@
-   mov\t%w0, %w1
-   mov\t%w0, %1
-   * return aarch64_output_scalar_simd_mov_immediate (operands[1], <MODE>mode);
-   * return aarch64_output_sve_cnt_immediate (\"cnt\", \"%x0\", operands[1]);
-   ldr<size>\t%w0, %1
-   ldr\t%<size>0, %1
-   str<size>\t%w1, %0
-   str\t%<size>1, %0
-   * return TARGET_SIMD ? \"umov\t%w0, %1.<v>[0]\" : \"fmov\t%w0, %s1\";
-   * return TARGET_SIMD ? \"dup\t%0.<Vallxd>, %w1\" : \"fmov\t%s0, %w1\";
-   * return TARGET_SIMD ? \"dup\t%<Vetype>0, %1.<v>[0]\" : \"fmov\t%s0, %s1\";"
-  ;; The "mov_imm" type for CNT is just a placeholder.
-  [(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4,
-		     store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup")
-   (set_attr "arch" "*,*,simd,sve,*,*,*,*,*,*,*")]
+  {@ [cons: =0, 1; attrs: type, arch]
+     [r, r    ; mov_reg        , *     ] mov\t%w0, %w1
+     [r, M    ; mov_imm        , *     ] mov\t%w0, %1
+     [w, D<hq>; neon_move      , simd  ] << aarch64_output_scalar_simd_mov_immediate (operands[1], <MODE>mode);
+     /* The "mov_imm" type for CNT is just a placeholder.  */
+     [r, Usv  ; mov_imm        , sve   ] << aarch64_output_sve_cnt_immediate ("cnt", "%x0", operands[1]);
+     [r, m    ; load_4         , *     ] ldr<size>\t%w0, %1
+     [w, m    ; load_4         , *     ] ldr\t%<size>0, %1
+     [m, r Z  ; store_4        , *     ] str<size>\\t%w1, %0
+     [m, w    ; store_4        , *     ] str\t%<size>1, %0
+     [r, w    ; neon_to_gp<q>  , simd  ] umov\t%w0, %1.<v>[0]
+     [r, w    ; neon_to_gp<q>  , nosimd] fmov\t%w0, %s1
+     [w, r Z  ; neon_from_gp<q>, simd  ] dup\t%0.<Vallxd>, %w1
+     [w, r Z  ; neon_from_gp<q>, nosimd] fmov\t%s0, %w1
+     [w, w    ; neon_dup       , simd  ] dup\t%<Vetype>0, %1.<v>[0]
+     [w, w    ; neon_dup       , nosimd] fmov\t%s0, %s1
+  }
 )
 
 (define_expand "mov<mode>"
@@ -1262,79 +1266,70 @@
 )
 
 (define_insn_and_split "*movsi_aarch64"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r, r,w, m, m,  r,  r,  r, w,r,w, w")
-	(match_operand:SI 1 "aarch64_mov_operand"  " r,r,k,M,n,Usv,m,m,rZ,w,Usw,Usa,Ush,rZ,w,w,Ds"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand")
+	(match_operand:SI 1 "aarch64_mov_operand"))]
   "(register_operand (operands[0], SImode)
     || aarch64_reg_or_zero (operands[1], SImode))"
-  "@
-   mov\\t%w0, %w1
-   mov\\t%w0, %w1
-   mov\\t%w0, %w1
-   mov\\t%w0, %1
-   #
-   * return aarch64_output_sve_cnt_immediate (\"cnt\", \"%x0\", operands[1]);
-   ldr\\t%w0, %1
-   ldr\\t%s0, %1
-   str\\t%w1, %0
-   str\\t%s1, %0
-   adrp\\t%x0, %A1\;ldr\\t%w0, [%x0, %L1]
-   adr\\t%x0, %c1
-   adrp\\t%x0, %A1
-   fmov\\t%s0, %w1
-   fmov\\t%w0, %s1
-   fmov\\t%s0, %s1
-   * return aarch64_output_scalar_simd_mov_immediate (operands[1], SImode);"
+  {@ [cons: =0, 1; attrs: type, arch, length]
+     [r k, r  ; mov_reg  , *   , 4] mov\t%w0, %w1
+     [r  , k  ; mov_reg  , *   , 4] ^
+     [r  , M  ; mov_imm  , *   , 4] mov\t%w0, %1
+     [r  , n  ; mov_imm  , *   ,16] #
+     /* The "mov_imm" type for CNT is just a placeholder.  */
+     [r  , Usv; mov_imm  , sve , 4] << aarch64_output_sve_cnt_immediate ("cnt", "%x0", operands[1]);
+     [r  , m  ; load_4   , *   , 4] ldr\t%w0, %1
+     [w  , m  ; load_4   , fp  , 4] ldr\t%s0, %1
+     [m  , r Z; store_4  , *   , 4] str\t%w1, %0
+     [m  , w  ; store_4  , fp  , 4] str\t%s1, %0
+     [r  , Usw; load_4   , *   , 8] adrp\t%x0, %A1;ldr\t%w0, [%x0, %L1]
+     [r  , Usa; adr      , *   , 4] adr\t%x0, %c1
+     [r  , Ush; adr      , *   , 4] adrp\t%x0, %A1
+     [w  , r Z; f_mcr    , fp  , 4] fmov\t%s0, %w1
+     [r  , w  ; f_mrc    , fp  , 4] fmov\t%w0, %s1
+     [w  , w  ; fmov     , fp  , 4] fmov\t%s0, %s1
+     [w  , Ds ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], SImode);
+  }
   "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)
     && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
-   [(const_int 0)]
-   "{
-       aarch64_expand_mov_immediate (operands[0], operands[1]);
-       DONE;
-    }"
-  ;; The "mov_imm" type for CNT is just a placeholder.
-  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,load_4,
-		    load_4,store_4,store_4,load_4,adr,adr,f_mcr,f_mrc,fmov,neon_move")
-   (set_attr "arch"   "*,*,*,*,*,sve,*,fp,*,fp,*,*,*,fp,fp,fp,simd")
-   (set_attr "length" "4,4,4,4,*,  4,4, 4,4, 4,8,4,4, 4, 4, 4,   4")
-]
+  [(const_int 0)]
+  {
+    aarch64_expand_mov_immediate (operands[0], operands[1]);
+    DONE;
+  }
 )
 
 (define_insn_and_split "*movdi_aarch64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r, r,w, m,m,   r,  r,  r, w,r,w, w")
-	(match_operand:DI 1 "aarch64_mov_operand"  " r,r,k,O,n,Usv,m,m,rZ,w,Usw,Usa,Ush,rZ,w,w,Dd"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand")
+	(match_operand:DI 1 "aarch64_mov_operand"))]
   "(register_operand (operands[0], DImode)
     || aarch64_reg_or_zero (operands[1], DImode))"
-  "@
-   mov\\t%x0, %x1
-   mov\\t%0, %x1
-   mov\\t%x0, %1
-   * return aarch64_is_mov_xn_imm (INTVAL (operands[1])) ? \"mov\\t%x0, %1\" : \"mov\\t%w0, %1\";
-   #
-   * return aarch64_output_sve_cnt_immediate (\"cnt\", \"%x0\", operands[1]);
-   ldr\\t%x0, %1
-   ldr\\t%d0, %1
-   str\\t%x1, %0
-   str\\t%d1, %0
-   * return TARGET_ILP32 ? \"adrp\\t%0, %A1\;ldr\\t%w0, [%0, %L1]\" : \"adrp\\t%0, %A1\;ldr\\t%0, [%0, %L1]\";
-   adr\\t%x0, %c1
-   adrp\\t%x0, %A1
-   fmov\\t%d0, %x1
-   fmov\\t%x0, %d1
-   fmov\\t%d0, %d1
-   * return aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);"
-   "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)
-    && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
-   [(const_int 0)]
-   "{
-       aarch64_expand_mov_immediate (operands[0], operands[1]);
-       DONE;
-    }"
-  ;; The "mov_imm" type for CNTD is just a placeholder.
-  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm,
-		     load_8,load_8,store_8,store_8,load_8,adr,adr,f_mcr,f_mrc,
-		     fmov,neon_move")
-   (set_attr "arch"   "*,*,*,*,*,sve,*,fp,*,fp,*,*,*,fp,fp,fp,simd")
-   (set_attr "length" "4,4,4,4,*,  4,4, 4,4, 4,8,4,4, 4, 4, 4,   4")]
+  {@ [cons: =0, 1; attrs: type, arch, length]
+     [r, r  ; mov_reg  , *   , 4] mov\t%x0, %x1
+     [k, r  ; mov_reg  , *   , 4] mov\t%0, %x1
+     [r, k  ; mov_reg  , *   , 4] mov\t%x0, %1
+     [r, O  ; mov_imm  , *   , 4] << aarch64_is_mov_xn_imm (INTVAL (operands[1])) ? "mov\t%x0, %1" : "mov\t%w0, %1";
+     [r, n  ; mov_imm  , *   ,16] #
+     /* The "mov_imm" type for CNT is just a placeholder.  */
+     [r, Usv; mov_imm  , sve , 4] << aarch64_output_sve_cnt_immediate ("cnt", "%x0", operands[1]);
+     [r, m  ; load_8   , *   , 4] ldr\t%x0, %1
+     [w, m  ; load_8   , fp  , 4] ldr\t%d0, %1
+     [m, r Z; store_8  , *   , 4] str\t%x1, %0
+     [m, w  ; store_8  , fp  , 4] str\t%d1, %0
+     [r, Usw; load_8   , *   , 8] << TARGET_ILP32 ? "adrp\t%0, %A1;ldr\t%w0, [%0, %L1]" : "adrp\t%0, %A1;ldr\t%0, [%0, %L1]";
+     [r, Usa; adr      , *   , 4] adr\t%x0, %c1
+     [r, Ush; adr      , *   , 4] adrp\t%x0, %A1
+     [w, r Z; f_mcr    , fp  , 4] fmov\t%d0, %x1
+     [r, w  ; f_mrc    , fp  , 4] fmov\t%x0, %d1
+     [w, w  ; fmov     , fp  , 4] fmov\t%d0, %d1
+     [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);
+  }
+  "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)
+   && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
+  [(const_int 0)]
+  {
+      aarch64_expand_mov_immediate (operands[0], operands[1]);
+      DONE;
+  }
 )
 
 (define_insn "insv_imm<mode>"
@@ -7330,10 +7325,11 @@
 
 (define_insn "stack_tie"
   [(set (mem:BLK (scratch))
-	(unspec:BLK [(match_operand:DI 0 "register_operand" "rk")
-		     (match_operand:DI 1 "register_operand" "rk")]
+	(unspec:BLK [(reg:DI SP_REGNUM)
+		     (match_operand:DI 0 "register_operand" "rk")
+		     (match_operand:DI 1 "const_int_operand")]
 		    UNSPEC_PRLG_STK))]
-  ""
+  "REGNO (operands[0]) == INTVAL (operands[1])"
   ""
   [(set_attr "length" "0")]
 )
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index c51ce17..1f122d9 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -705,6 +705,9 @@ archs4x, archs4xd"
 	(match_operand:QI 1 "move_src_operand"  "rL,rP,q,P,hCm1,cL, I,?Rac,i,?i,T,q,Usd,Ucm,m,?Rac,c,?Rac,Cm3,i"))]
   "register_operand (operands[0], QImode)
    || register_operand (operands[1], QImode)
+   || (CONSTANT_P (operands[1])
+       && (!satisfies_constraint_I (operands[1]) || !optimize_size)
+       && satisfies_constraint_Usc (operands[0]))
    || (satisfies_constraint_Cm3 (operands[1])
        && memory_operand (operands[0], QImode))"
   "@
@@ -1363,7 +1366,10 @@ archs4x, archs4xd"
   [(set (match_operand:SF 0 "move_dest_operand"   "=h,h,   r,r,  q,S,Usc,r,m")
 	(match_operand:SF 1 "move_src_operand"  "hCfZ,E,rCfZ,E,Uts,q,  E,m,r"))]
   "register_operand (operands[0], SFmode)
-   || register_operand (operands[1], SFmode)"
+   || register_operand (operands[1], SFmode)
+   || (CONSTANT_P (operands[1])
+       && (!satisfies_constraint_I (operands[1]) || !optimize_size)
+       && satisfies_constraint_Usc (operands[0]))"
   "@
    mov%?\\t%0,%1
    mov%?\\t%0,%1 ; %A1
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index ef6872a..0447641 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -1095,6 +1095,10 @@ avr_option_override (void)
       flag_omit_frame_pointer = 0;
     }
 
+  /* Disable flag_delete_null_pointer_checks if zero is a valid address. */
+  if (targetm.addr_space.zero_address_valid (ADDR_SPACE_GENERIC))
+    flag_delete_null_pointer_checks = 0;
+
   if (flag_pic == 1)
     warning (OPT_fpic, "%<-fpic%> is not supported");
   if (flag_pic == 2)
@@ -10501,6 +10505,16 @@ avr_addr_space_diagnose_usage (addr_space_t as, location_t loc)
   (void) avr_addr_space_supported_p (as, loc);
 }
 
+/* Implement `TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID. Zero is a valid
+   address in all address spaces. Even in ADDR_SPACE_FLASH1 etc..,
+   a zero address is valid and means 0x<RAMPZ val>0000, where RAMPZ is
+   set to the appropriate segment value. */
+
+static bool
+avr_addr_space_zero_address_valid (addr_space_t)
+{
+  return true;
+}
 
 /* Look if DECL shall be placed in program memory space by
    means of attribute `progmem' or some address-space qualifier.
@@ -15255,6 +15269,9 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
 #undef  TARGET_ADDR_SPACE_DIAGNOSE_USAGE
 #define TARGET_ADDR_SPACE_DIAGNOSE_USAGE avr_addr_space_diagnose_usage
 
+#undef  TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID
+#define TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID avr_addr_space_zero_address_valid
+
 #undef  TARGET_MODE_DEPENDENT_ADDRESS_P
 #define TARGET_MODE_DEPENDENT_ADDRESS_P avr_mode_dependent_address_p
 
diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt
index f62d746..5a0b465 100644
--- a/gcc/config/avr/avr.opt
+++ b/gcc/config/avr/avr.opt
@@ -27,7 +27,7 @@ Target RejectNegative Joined Var(avr_mmcu) MissingArgError(missing device or arc
 -mmcu=MCU	Select the target MCU.
 
 mgas-isr-prologues
-Target Var(avr_gasisr_prologues) UInteger Init(0)
+Target Var(avr_gasisr_prologues) UInteger Init(0) Optimization 
 Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues.
 
 mn-flash=
@@ -65,7 +65,7 @@ Target Joined RejectNegative UInteger Var(avr_branch_cost) Init(0)
 Set the branch costs for conditional branch instructions.  Reasonable values are small, non-negative integers.  The default branch cost is 0.
 
 mmain-is-OS_task
-Target Mask(MAIN_IS_OS_TASK)
+Target Mask(MAIN_IS_OS_TASK) Optimization
 Treat main as if it had attribute OS_task.
 
 morder1
diff --git a/gcc/config/gcn/gcn-protos.h b/gcc/config/gcn/gcn-protos.h
index 287ce17..3befb2b 100644
--- a/gcc/config/gcn/gcn-protos.h
+++ b/gcc/config/gcn/gcn-protos.h
@@ -136,6 +136,17 @@ vgpr_2reg_mode_p (machine_mode mode)
   return (mode == DImode || mode == DFmode);
 }
 
+/* Return true if MODE is valid for four VGPR registers.  */
+
+inline bool
+vgpr_4reg_mode_p (machine_mode mode)
+{
+  if (VECTOR_MODE_P (mode))
+    mode = GET_MODE_INNER (mode);
+
+  return (mode == TImode);
+}
+
 /* Return true if MODE can be handled directly by VGPR operations.  */
 
 inline bool
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 7290cdc..284dda7 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -96,6 +96,10 @@
 		       V32DI V32DF
 		       V64DI V64DF])
 
+; Vector modes for four vector registers
+(define_mode_iterator V_4REG [V2TI V4TI V8TI V16TI V32TI V64TI])
+(define_mode_iterator V_4REG_ALT [V2TI V4TI V8TI V16TI V32TI V64TI])
+
 ; Vector modes with native support
 (define_mode_iterator V_noQI
 		      [V2HI V2HF V2SI V2SF V2DI V2DF
@@ -136,7 +140,7 @@
 		       V32SF V32DF
 		       V64SF V64DF])
 
-; All of above
+; All modes in which we want to do more than just moves.
 (define_mode_iterator V_ALL
 		      [V2QI V2HI V2HF V2SI V2SF V2DI V2DF
 		       V4QI V4HI V4HF V4SI V4SF V4DI V4DF
@@ -175,97 +179,113 @@
 		       V32HF V32SF V32DF
 		       V64HF V64SF V64DF])
 
+; All modes that need moves, including those without many insns.
+(define_mode_iterator V_MOV
+		      [V2QI V2HI V2HF V2SI V2SF V2DI V2DF V2TI
+		       V4QI V4HI V4HF V4SI V4SF V4DI V4DF V4TI
+		       V8QI V8HI V8HF V8SI V8SF V8DI V8DF V8TI
+		       V16QI V16HI V16HF V16SI V16SF V16DI V16DF V16TI
+		       V32QI V32HI V32HF V32SI V32SF V32DI V32DF V32TI
+		       V64QI V64HI V64HF V64SI V64SF V64DI V64DF V64TI])
+(define_mode_iterator V_MOV_ALT
+		      [V2QI V2HI V2HF V2SI V2SF V2DI V2DF V2TI
+		       V4QI V4HI V4HF V4SI V4SF V4DI V4DF V4TI
+		       V8QI V8HI V8HF V8SI V8SF V8DI V8DF V8TI
+		       V16QI V16HI V16HF V16SI V16SF V16DI V16DF V16TI
+		       V32QI V32HI V32HF V32SI V32SF V32DI V32DF V32TI
+		       V64QI V64HI V64HF V64SI V64SF V64DI V64DF V64TI])
+
 (define_mode_attr scalar_mode
-  [(QI "qi") (HI "hi") (SI "si")
+  [(QI "qi") (HI "hi") (SI "si") (TI "ti")
    (HF "hf") (SF "sf") (DI "di") (DF "df")
-   (V2QI "qi") (V2HI "hi") (V2SI "si")
+   (V2QI "qi") (V2HI "hi") (V2SI "si") (V2TI "ti")
    (V2HF "hf") (V2SF "sf") (V2DI "di") (V2DF "df")
-   (V4QI "qi") (V4HI "hi") (V4SI "si")
+   (V4QI "qi") (V4HI "hi") (V4SI "si") (V4TI "ti")
    (V4HF "hf") (V4SF "sf") (V4DI "di") (V4DF "df")
-   (V8QI "qi") (V8HI "hi") (V8SI "si")
+   (V8QI "qi") (V8HI "hi") (V8SI "si") (V8TI "ti")
    (V8HF "hf") (V8SF "sf") (V8DI "di") (V8DF "df")
-   (V16QI "qi") (V16HI "hi") (V16SI "si")
+   (V16QI "qi") (V16HI "hi") (V16SI "si") (V16TI "ti")
    (V16HF "hf") (V16SF "sf") (V16DI "di") (V16DF "df")
-   (V32QI "qi") (V32HI "hi") (V32SI "si")
+   (V32QI "qi") (V32HI "hi") (V32SI "si") (V32TI "ti")
    (V32HF "hf") (V32SF "sf") (V32DI "di") (V32DF "df")
-   (V64QI "qi") (V64HI "hi") (V64SI "si")
+   (V64QI "qi") (V64HI "hi") (V64SI "si") (V64TI "ti")
    (V64HF "hf") (V64SF "sf") (V64DI "di") (V64DF "df")])
 
 (define_mode_attr SCALAR_MODE
-  [(QI "QI") (HI "HI") (SI "SI")
+  [(QI "QI") (HI "HI") (SI "SI") (TI "TI")
    (HF "HF") (SF "SF") (DI "DI") (DF "DF")
-   (V2QI "QI") (V2HI "HI") (V2SI "SI")
+   (V2QI "QI") (V2HI "HI") (V2SI "SI") (V2TI "TI")
    (V2HF "HF") (V2SF "SF") (V2DI "DI") (V2DF "DF")
-   (V4QI "QI") (V4HI "HI") (V4SI "SI")
+   (V4QI "QI") (V4HI "HI") (V4SI "SI") (V4TI "TI")
    (V4HF "HF") (V4SF "SF") (V4DI "DI") (V4DF "DF")
-   (V8QI "QI") (V8HI "HI") (V8SI "SI")
+   (V8QI "QI") (V8HI "HI") (V8SI "SI") (V8TI "TI")
    (V8HF "HF") (V8SF "SF") (V8DI "DI") (V8DF "DF")
-   (V16QI "QI") (V16HI "HI") (V16SI "SI")
+   (V16QI "QI") (V16HI "HI") (V16SI "SI") (V16TI "TI")
    (V16HF "HF") (V16SF "SF") (V16DI "DI") (V16DF "DF")
-   (V32QI "QI") (V32HI "HI") (V32SI "SI")
+   (V32QI "QI") (V32HI "HI") (V32SI "SI") (V32TI "TI")
    (V32HF "HF") (V32SF "SF") (V32DI "DI") (V32DF "DF")
-   (V64QI "QI") (V64HI "HI") (V64SI "SI")
+   (V64QI "QI") (V64HI "HI") (V64SI "SI") (V64TI "TI")
    (V64HF "HF") (V64SF "SF") (V64DI "DI") (V64DF "DF")])
 
 (define_mode_attr vnsi
-  [(QI "si") (HI "si") (SI "si")
+  [(QI "si") (HI "si") (SI "si") (TI "si")
    (HF "si") (SF "si") (DI "si") (DF "si")
    (V2QI "v2si") (V2HI "v2si") (V2HF "v2si") (V2SI "v2si")
-   (V2SF "v2si") (V2DI "v2si") (V2DF "v2si")
+   (V2SF "v2si") (V2DI "v2si") (V2DF "v2si") (V2TI "v2si")
    (V4QI "v4si") (V4HI "v4si") (V4HF "v4si") (V4SI "v4si")
-   (V4SF "v4si") (V4DI "v4si") (V4DF "v4si")
+   (V4SF "v4si") (V4DI "v4si") (V4DF "v4si") (V4TI "v4si")
    (V8QI "v8si") (V8HI "v8si") (V8HF "v8si") (V8SI "v8si")
-   (V8SF "v8si") (V8DI "v8si") (V8DF "v8si")
+   (V8SF "v8si") (V8DI "v8si") (V8DF "v8si") (V8TI "v8si")
    (V16QI "v16si") (V16HI "v16si") (V16HF "v16si") (V16SI "v16si")
-   (V16SF "v16si") (V16DI "v16si") (V16DF "v16si")
+   (V16SF "v16si") (V16DI "v16si") (V16DF "v16si") (V16TI "v16si")
    (V32QI "v32si") (V32HI "v32si") (V32HF "v32si") (V32SI "v32si")
-   (V32SF "v32si") (V32DI "v32si") (V32DF "v32si")
+   (V32SF "v32si") (V32DI "v32si") (V32DF "v32si") (V32TI "v32si")
    (V64QI "v64si") (V64HI "v64si") (V64HF "v64si") (V64SI "v64si")
-   (V64SF "v64si") (V64DI "v64si") (V64DF "v64si")])
+   (V64SF "v64si") (V64DI "v64si") (V64DF "v64si") (V64TI "v64si")])
 
 (define_mode_attr VnSI
-  [(QI "SI") (HI "SI") (SI "SI")
+  [(QI "SI") (HI "SI") (SI "SI") (TI "SI")
    (HF "SI") (SF "SI") (DI "SI") (DF "SI")
    (V2QI "V2SI") (V2HI "V2SI") (V2HF "V2SI") (V2SI "V2SI")
-   (V2SF "V2SI") (V2DI "V2SI") (V2DF "V2SI")
+   (V2SF "V2SI") (V2DI "V2SI") (V2DF "V2SI") (V2TI "V2SI")
    (V4QI "V4SI") (V4HI "V4SI") (V4HF "V4SI") (V4SI "V4SI")
-   (V4SF "V4SI") (V4DI "V4SI") (V4DF "V4SI")
+   (V4SF "V4SI") (V4DI "V4SI") (V4DF "V4SI") (V4TI "V4SI")
    (V8QI "V8SI") (V8HI "V8SI") (V8HF "V8SI") (V8SI "V8SI")
-   (V8SF "V8SI") (V8DI "V8SI") (V8DF "V8SI")
+   (V8SF "V8SI") (V8DI "V8SI") (V8DF "V8SI") (V8TI "V8SI")
    (V16QI "V16SI") (V16HI "V16SI") (V16HF "V16SI") (V16SI "V16SI")
-   (V16SF "V16SI") (V16DI "V16SI") (V16DF "V16SI")
+   (V16SF "V16SI") (V16DI "V16SI") (V16DF "V16SI") (V16TI "V16SI")
    (V32QI "V32SI") (V32HI "V32SI") (V32HF "V32SI") (V32SI "V32SI")
-   (V32SF "V32SI") (V32DI "V32SI") (V32DF "V32SI")
+   (V32SF "V32SI") (V32DI "V32SI") (V32DF "V32SI") (V32TI "V32SI")
    (V64QI "V64SI") (V64HI "V64SI") (V64HF "V64SI") (V64SI "V64SI")
-   (V64SF "V64SI") (V64DI "V64SI") (V64DF "V64SI")])
+   (V64SF "V64SI") (V64DI "V64SI") (V64DF "V64SI") (V64TI "V64SI")])
 
 (define_mode_attr vndi
   [(V2QI "v2di") (V2HI "v2di") (V2HF "v2di") (V2SI "v2di")
-   (V2SF "v2di") (V2DI "v2di") (V2DF "v2di")
+   (V2SF "v2di") (V2DI "v2di") (V2DF "v2di") (V2TI "v2di")
    (V4QI "v4di") (V4HI "v4di") (V4HF "v4di") (V4SI "v4di")
-   (V4SF "v4di") (V4DI "v4di") (V4DF "v4di")
+   (V4SF "v4di") (V4DI "v4di") (V4DF "v4di") (V4TI "v4di")
    (V8QI "v8di") (V8HI "v8di") (V8HF "v8di") (V8SI "v8di")
-   (V8SF "v8di") (V8DI "v8di") (V8DF "v8di")
+   (V8SF "v8di") (V8DI "v8di") (V8DF "v8di") (V8TI "v8di")
    (V16QI "v16di") (V16HI "v16di") (V16HF "v16di") (V16SI "v16di")
-   (V16SF "v16di") (V16DI "v16di") (V16DF "v16di")
+   (V16SF "v16di") (V16DI "v16di") (V16DF "v16di") (V16TI "v16di")
    (V32QI "v32di") (V32HI "v32di") (V32HF "v32di") (V32SI "v32di")
-   (V32SF "v32di") (V32DI "v32di") (V32DF "v32di")
+   (V32SF "v32di") (V32DI "v32di") (V32DF "v32di") (V32TI "v32di")
    (V64QI "v64di") (V64HI "v64di") (V64HF "v64di") (V64SI "v64di")
-   (V64SF "v64di") (V64DI "v64di") (V64DF "v64di")])
+   (V64SF "v64di") (V64DI "v64di") (V64DF "v64di") (V64TI "v64di")])
 
 (define_mode_attr VnDI
   [(V2QI "V2DI") (V2HI "V2DI") (V2HF "V2DI") (V2SI "V2DI")
-   (V2SF "V2DI") (V2DI "V2DI") (V2DF "V2DI")
+   (V2SF "V2DI") (V2DI "V2DI") (V2DF "V2DI") (V2TI "V2DI")
    (V4QI "V4DI") (V4HI "V4DI") (V4HF "V4DI") (V4SI "V4DI")
-   (V4SF "V4DI") (V4DI "V4DI") (V4DF "V4DI")
+   (V4SF "V4DI") (V4DI "V4DI") (V4DF "V4DI") (V4TI "V4DI")
    (V8QI "V8DI") (V8HI "V8DI") (V8HF "V8DI") (V8SI "V8DI")
-   (V8SF "V8DI") (V8DI "V8DI") (V8DF "V8DI")
+   (V8SF "V8DI") (V8DI "V8DI") (V8DF "V8DI") (V8TI "V8DI")
    (V16QI "V16DI") (V16HI "V16DI") (V16HF "V16DI") (V16SI "V16DI")
-   (V16SF "V16DI") (V16DI "V16DI") (V16DF "V16DI")
+   (V16SF "V16DI") (V16DI "V16DI") (V16DF "V16DI") (V16TI "V16DI")
    (V32QI "V32DI") (V32HI "V32DI") (V32HF "V32DI") (V32SI "V32DI")
-   (V32SF "V32DI") (V32DI "V32DI") (V32DF "V32DI")
+   (V32SF "V32DI") (V32DI "V32DI") (V32DF "V32DI") (V32TI "V32DI")
    (V64QI "V64DI") (V64HI "V64DI") (V64HF "V64DI") (V64SI "V64DI")
-   (V64SF "V64DI") (V64DI "V64DI") (V64DF "V64DI")])
+   (V64SF "V64DI") (V64DI "V64DI") (V64DF "V64DI") (V64TI "V64DI")])
 
 (define_mode_attr sdwa
   [(V2QI "BYTE_0") (V2HI "WORD_0") (V2SI "DWORD")
@@ -288,38 +308,38 @@
 		   "" "_exec")
 
 (define_subst "vec_merge"
-  [(set (match_operand:V_ALL 0)
-	(match_operand:V_ALL 1))]
+  [(set (match_operand:V_MOV 0)
+	(match_operand:V_MOV 1))]
   ""
   [(set (match_dup 0)
-	(vec_merge:V_ALL
+	(vec_merge:V_MOV
 	  (match_dup 1)
-	  (match_operand:V_ALL 3 "gcn_register_or_unspec_operand" "U0")
+	  (match_operand:V_MOV 3 "gcn_register_or_unspec_operand" "U0")
 	  (match_operand:DI 4 "gcn_exec_reg_operand" "e")))])
 
 (define_subst "vec_merge_with_clobber"
-  [(set (match_operand:V_ALL 0)
-	(match_operand:V_ALL 1))
+  [(set (match_operand:V_MOV 0)
+	(match_operand:V_MOV 1))
    (clobber (match_operand 2))]
   ""
   [(set (match_dup 0)
-	(vec_merge:V_ALL
+	(vec_merge:V_MOV
 	  (match_dup 1)
-	  (match_operand:V_ALL 3 "gcn_register_or_unspec_operand" "U0")
+	  (match_operand:V_MOV 3 "gcn_register_or_unspec_operand" "U0")
 	  (match_operand:DI 4 "gcn_exec_reg_operand" "e")))
    (clobber (match_dup 2))])
 
 (define_subst "vec_merge_with_vcc"
-  [(set (match_operand:V_ALL 0)
-	(match_operand:V_ALL 1))
+  [(set (match_operand:V_MOV 0)
+	(match_operand:V_MOV 1))
    (set (match_operand:DI 2)
 	(match_operand:DI 3))]
   ""
   [(parallel
      [(set (match_dup 0)
-	   (vec_merge:V_ALL
+	   (vec_merge:V_MOV
 	     (match_dup 1)
-	     (match_operand:V_ALL 4 "gcn_register_or_unspec_operand" "U0")
+	     (match_operand:V_MOV 4 "gcn_register_or_unspec_operand" "U0")
 	     (match_operand:DI 5 "gcn_exec_reg_operand" "e")))
       (set (match_dup 2)
 	   (and:DI (match_dup 3)
@@ -351,8 +371,8 @@
 ; gather/scatter, maskload/store, etc.
 
 (define_expand "mov<mode>"
-  [(set (match_operand:V_ALL 0 "nonimmediate_operand")
-	(match_operand:V_ALL 1 "general_operand"))]
+  [(set (match_operand:V_MOV 0 "nonimmediate_operand")
+	(match_operand:V_MOV 1 "general_operand"))]
   ""
   {
     /* Bitwise reinterpret casts via SUBREG don't work with GCN vector
@@ -421,8 +441,8 @@
 ; A pseudo instruction that helps LRA use the "U0" constraint.
 
 (define_insn "mov<mode>_unspec"
-  [(set (match_operand:V_ALL 0 "nonimmediate_operand" "=v")
-	(match_operand:V_ALL 1 "gcn_unspec_operand"   " U"))]
+  [(set (match_operand:V_MOV 0 "nonimmediate_operand" "=v")
+	(match_operand:V_MOV 1 "gcn_unspec_operand"   " U"))]
   ""
   ""
   [(set_attr "type" "unknown")
@@ -527,6 +547,69 @@
   [(set_attr "type" "vmult,vmult,vmult,*,*")
    (set_attr "length" "16,16,16,16,16")])
 
+(define_insn "*mov<mode>_4reg"
+  [(set (match_operand:V_4REG 0 "nonimmediate_operand" "=v")
+	(match_operand:V_4REG 1 "general_operand"      "vDB"))]
+  ""
+  {
+    return "v_mov_b32\t%L0, %L1\;"
+           "v_mov_b32\t%H0, %H1\;"
+           "v_mov_b32\t%J0, %J1\;"
+           "v_mov_b32\t%K0, %K1\;";
+  }
+  [(set_attr "type" "vmult")
+   (set_attr "length" "16")])
+
+(define_insn "mov<mode>_exec"
+  [(set (match_operand:V_4REG 0 "nonimmediate_operand" "= v,   v,   v, v, m")
+	(vec_merge:V_4REG
+	  (match_operand:V_4REG 1 "general_operand"    "vDB,  v0,  v0, m, v")
+	  (match_operand:V_4REG 2 "gcn_alu_or_unspec_operand"
+						       " U0,vDA0,vDA0,U0,U0")
+	  (match_operand:DI 3 "register_operand"       "  e,  cV,  Sv, e, e")))
+   (clobber (match_scratch:<VnDI> 4		       "= X,   X,   X,&v,&v"))]
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
+  {
+    if (!REG_P (operands[1]) || REGNO (operands[0]) <= REGNO (operands[1]))
+      switch (which_alternative)
+	{
+	case 0:
+	  return "v_mov_b32\t%L0, %L1\;v_mov_b32\t%H0, %H1\;"
+                 "v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1";
+	case 1:
+	  return "v_cndmask_b32\t%L0, %L2, %L1, vcc\;"
+		 "v_cndmask_b32\t%H0, %H2, %H1, vcc\;"
+		 "v_cndmask_b32\t%J0, %J2, %J1, vcc\;"
+		 "v_cndmask_b32\t%K0, %K2, %K1, vcc";
+	case 2:
+	  return "v_cndmask_b32\t%L0, %L2, %L1, %3\;"
+		 "v_cndmask_b32\t%H0, %H2, %H1, %3\;"
+		 "v_cndmask_b32\t%J0, %J2, %J1, %3\;"
+		 "v_cndmask_b32\t%K0, %K2, %K1, %3";
+	}
+    else
+      switch (which_alternative)
+	{
+	case 0:
+	  return "v_mov_b32\t%H0, %H1\;v_mov_b32\t%L0, %L1\;"
+                 "v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1";
+	case 1:
+	  return "v_cndmask_b32\t%H0, %H2, %H1, vcc\;"
+		 "v_cndmask_b32\t%L0, %L2, %L1, vcc\;"
+		 "v_cndmask_b32\t%J0, %J2, %J1, vcc\;"
+		 "v_cndmask_b32\t%K0, %K2, %K1, vcc";
+	case 2:
+	  return "v_cndmask_b32\t%H0, %H2, %H1, %3\;"
+		 "v_cndmask_b32\t%L0, %L2, %L1, %3\;"
+		 "v_cndmask_b32\t%J0, %J2, %J1, %3\;"
+		 "v_cndmask_b32\t%K0, %K2, %K1, %3";
+	}
+
+    return "#";
+  }
+  [(set_attr "type" "vmult,vmult,vmult,*,*")
+   (set_attr "length" "32")])
+
 ; This variant does not accept an unspec, but does permit MEM
 ; read/modify/write which is necessary for maskstore.
 
@@ -592,12 +675,25 @@
   [(set_attr "type" "vmult,*,*")
    (set_attr "length" "8,12,12")])
 
+(define_insn "mov<mode>_sgprbase"
+  [(set (match_operand:V_4REG 0 "nonimmediate_operand" "= v, v, m")
+	(unspec:V_4REG
+	  [(match_operand:V_4REG 1 "general_operand"   "vDB, m, v")]
+	  UNSPEC_SGPRBASE))
+   (clobber (match_operand:<VnDI> 2 "register_operand"  "=&v,&v,&v"))]
+  "lra_in_progress || reload_completed"
+  "v_mov_b32\t%L0, %L1\;v_mov_b32\t%H0, %H1\;v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1
+   #
+   #"
+  [(set_attr "type" "vmult,*,*")
+   (set_attr "length" "8,12,12")])
+
 ; reload_in was once a standard name, but here it's only referenced by
 ; gcn_secondary_reload.  It allows a reload with a scratch register.
 
 (define_expand "reload_in<mode>"
-  [(set (match_operand:V_ALL 0 "register_operand"     "= v")
-	(match_operand:V_ALL 1 "memory_operand"	      "  m"))
+  [(set (match_operand:V_MOV 0 "register_operand"     "= v")
+	(match_operand:V_MOV 1 "memory_operand"	      "  m"))
    (clobber (match_operand:<VnDI> 2 "register_operand" "=&v"))]
   ""
   {
@@ -608,8 +704,8 @@
 ; reload_out is similar to reload_in, above.
 
 (define_expand "reload_out<mode>"
-  [(set (match_operand:V_ALL 0 "memory_operand"	      "= m")
-	(match_operand:V_ALL 1 "register_operand"     "  v"))
+  [(set (match_operand:V_MOV 0 "memory_operand"	      "= m")
+	(match_operand:V_MOV 1 "register_operand"     "  v"))
    (clobber (match_operand:<VnDI> 2 "register_operand" "=&v"))]
   ""
   {
@@ -620,9 +716,9 @@
 ; Expand scalar addresses into gather/scatter patterns
 
 (define_split
-  [(set (match_operand:V_ALL 0 "memory_operand")
-	(unspec:V_ALL
-	  [(match_operand:V_ALL 1 "general_operand")]
+  [(set (match_operand:V_MOV 0 "memory_operand")
+	(unspec:V_MOV
+	  [(match_operand:V_MOV 1 "general_operand")]
 	  UNSPEC_SGPRBASE))
    (clobber (match_scratch:<VnDI> 2))]
   ""
@@ -638,10 +734,10 @@
   })
 
 (define_split
-  [(set (match_operand:V_ALL 0 "memory_operand")
-	(vec_merge:V_ALL
-	  (match_operand:V_ALL 1 "general_operand")
-	  (match_operand:V_ALL 2 "")
+  [(set (match_operand:V_MOV 0 "memory_operand")
+	(vec_merge:V_MOV
+	  (match_operand:V_MOV 1 "general_operand")
+	  (match_operand:V_MOV 2 "")
 	  (match_operand:DI 3 "gcn_exec_reg_operand")))
    (clobber (match_scratch:<VnDI> 4))]
   ""
@@ -659,14 +755,14 @@
   })
 
 (define_split
-  [(set (match_operand:V_ALL 0 "nonimmediate_operand")
-	(unspec:V_ALL
-	  [(match_operand:V_ALL 1 "memory_operand")]
+  [(set (match_operand:V_MOV 0 "nonimmediate_operand")
+	(unspec:V_MOV
+	  [(match_operand:V_MOV 1 "memory_operand")]
 	  UNSPEC_SGPRBASE))
    (clobber (match_scratch:<VnDI> 2))]
   ""
   [(set (match_dup 0)
-	(unspec:V_ALL [(match_dup 5) (match_dup 6) (match_dup 7)
+	(unspec:V_MOV [(match_dup 5) (match_dup 6) (match_dup 7)
 		       (mem:BLK (scratch))]
 		      UNSPEC_GATHER))]
   {
@@ -678,16 +774,16 @@
   })
 
 (define_split
-  [(set (match_operand:V_ALL 0 "nonimmediate_operand")
-	(vec_merge:V_ALL
-	  (match_operand:V_ALL 1 "memory_operand")
-	  (match_operand:V_ALL 2 "")
+  [(set (match_operand:V_MOV 0 "nonimmediate_operand")
+	(vec_merge:V_MOV
+	  (match_operand:V_MOV 1 "memory_operand")
+	  (match_operand:V_MOV 2 "")
 	  (match_operand:DI 3 "gcn_exec_reg_operand")))
    (clobber (match_scratch:<VnDI> 4))]
   ""
   [(set (match_dup 0)
-	(vec_merge:V_ALL
-	  (unspec:V_ALL [(match_dup 5) (match_dup 6) (match_dup 7)
+	(vec_merge:V_MOV
+	  (unspec:V_MOV [(match_dup 5) (match_dup 6) (match_dup 7)
 			 (mem:BLK (scratch))]
 			 UNSPEC_GATHER)
 	  (match_dup 2)
@@ -744,9 +840,9 @@
    (set_attr "laneselect" "yes")])
 
 (define_expand "vec_set<mode>"
-  [(set (match_operand:V_ALL 0 "register_operand")
-	(vec_merge:V_ALL
-	  (vec_duplicate:V_ALL
+  [(set (match_operand:V_MOV 0 "register_operand")
+	(vec_merge:V_MOV
+	  (vec_duplicate:V_MOV
 	    (match_operand:<SCALAR_MODE> 1 "register_operand"))
 	  (match_dup 0)
 	  (ashift (const_int 1) (match_operand:SI 2 "gcn_alu_operand"))))]
@@ -804,6 +900,15 @@
   [(set_attr "type" "vop3a")
    (set_attr "length" "16")])
 
+(define_insn "vec_duplicate<mode><exec>"
+  [(set (match_operand:V_4REG 0 "register_operand"	   "=  v")
+	(vec_duplicate:V_4REG
+	  (match_operand:<SCALAR_MODE> 1 "gcn_alu_operand" "SvDB")))]
+  ""
+  "v_mov_b32\t%L0, %L1\;v_mov_b32\t%H0, %H1\;v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1"
+  [(set_attr "type" "mult")
+   (set_attr "length" "32")])
+
 (define_insn "vec_extract<mode><scalar_mode>"
   [(set (match_operand:<SCALAR_MODE> 0 "register_operand"  "=Sg")
 	(vec_select:<SCALAR_MODE>
@@ -828,6 +933,18 @@
    (set_attr "exec" "none")
    (set_attr "laneselect" "yes")])
 
+(define_insn "vec_extract<mode><scalar_mode>"
+  [(set (match_operand:<SCALAR_MODE> 0 "register_operand"  "=&Sg")
+	(vec_select:<SCALAR_MODE>
+	  (match_operand:V_4REG 1 "register_operand"	   "   v")
+	  (parallel [(match_operand:SI 2 "gcn_alu_operand" " SvB")])))]
+  ""
+  "v_readlane_b32 %L0, %L1, %2\;v_readlane_b32 %H0, %H1, %2\;v_readlane_b32 %J0, %J1, %2\;v_readlane_b32 %K0, %K1, %2"
+  [(set_attr "type" "vmult")
+   (set_attr "length" "32")
+   (set_attr "exec" "none")
+   (set_attr "laneselect" "yes")])
+
 (define_insn "vec_extract<V_1REG:mode><V_1REG_ALT:mode>_nop"
   [(set (match_operand:V_1REG_ALT 0 "register_operand" "=v,v")
 	(vec_select:V_1REG_ALT
@@ -854,39 +971,52 @@
   [(set_attr "type" "vmult")
    (set_attr "length" "0,8")])
   
-(define_expand "vec_extract<V_ALL:mode><V_ALL_ALT:mode>"
-  [(match_operand:V_ALL_ALT 0 "register_operand")
-   (match_operand:V_ALL 1 "register_operand")
+(define_insn "vec_extract<V_4REG:mode><V_4REG_ALT:mode>_nop"
+  [(set (match_operand:V_4REG_ALT 0 "register_operand" "=v,v")
+	(vec_select:V_4REG_ALT
+	  (match_operand:V_4REG 1 "register_operand"   " 0,v")
+	  (match_operand 2 "ascending_zero_int_parallel" "")))]
+  "MODE_VF (<V_4REG_ALT:MODE>mode) < MODE_VF (<V_4REG:MODE>mode)
+   && <V_4REG_ALT:SCALAR_MODE>mode == <V_4REG:SCALAR_MODE>mode"
+  "@
+  ; in-place extract %0
+  v_mov_b32\t%L0, %L1\;v_mov_b32\t%H0, %H1\;v_mov_b32\t%J0, %J1\;v_mov_b32\t%K0, %K1"
+  [(set_attr "type" "vmult")
+   (set_attr "length" "0,16")])
+  
+(define_expand "vec_extract<V_MOV:mode><V_MOV_ALT:mode>"
+  [(match_operand:V_MOV_ALT 0 "register_operand")
+   (match_operand:V_MOV 1 "register_operand")
    (match_operand 2 "immediate_operand")]
-  "MODE_VF (<V_ALL_ALT:MODE>mode) < MODE_VF (<V_ALL:MODE>mode)
-   && <V_ALL_ALT:SCALAR_MODE>mode == <V_ALL:SCALAR_MODE>mode"
+  "MODE_VF (<V_MOV_ALT:MODE>mode) < MODE_VF (<V_MOV:MODE>mode)
+   && <V_MOV_ALT:SCALAR_MODE>mode == <V_MOV:SCALAR_MODE>mode"
   {
-    int numlanes = GET_MODE_NUNITS (<V_ALL_ALT:MODE>mode);
+    int numlanes = GET_MODE_NUNITS (<V_MOV_ALT:MODE>mode);
     int firstlane = INTVAL (operands[2]) * numlanes;
     rtx tmp;
 
     if (firstlane == 0)
       {
-	rtx parallel = gen_rtx_PARALLEL (<V_ALL:MODE>mode,
+	rtx parallel = gen_rtx_PARALLEL (<V_MOV:MODE>mode,
 					  rtvec_alloc (numlanes));
 	for (int i = 0; i < numlanes; i++)
 	  XVECEXP (parallel, 0, i) = GEN_INT (i);
-	emit_insn (gen_vec_extract<V_ALL:mode><V_ALL_ALT:mode>_nop
+	emit_insn (gen_vec_extract<V_MOV:mode><V_MOV_ALT:mode>_nop
 		   (operands[0], operands[1], parallel));
       } else {
         /* FIXME: optimize this by using DPP where available.  */
 
-        rtx permutation = gen_reg_rtx (<V_ALL:VnSI>mode);
-	emit_insn (gen_vec_series<V_ALL:vnsi> (permutation,
+        rtx permutation = gen_reg_rtx (<V_MOV:VnSI>mode);
+	emit_insn (gen_vec_series<V_MOV:vnsi> (permutation,
 					       GEN_INT (firstlane*4),
 					       GEN_INT (4)));
 
-	tmp = gen_reg_rtx (<V_ALL:MODE>mode);
-	emit_insn (gen_ds_bpermute<V_ALL:mode> (tmp, permutation, operands[1],
-						get_exec (<V_ALL:MODE>mode)));
+	tmp = gen_reg_rtx (<V_MOV:MODE>mode);
+	emit_insn (gen_ds_bpermute<V_MOV:mode> (tmp, permutation, operands[1],
+						get_exec (<V_MOV:MODE>mode)));
 
 	emit_move_insn (operands[0],
-			gen_rtx_SUBREG (<V_ALL_ALT:MODE>mode, tmp, 0));
+			gen_rtx_SUBREG (<V_MOV_ALT:MODE>mode, tmp, 0));
       }
     DONE;
   })
@@ -894,7 +1024,7 @@
 (define_expand "extract_last_<mode>"
   [(match_operand:<SCALAR_MODE> 0 "register_operand")
    (match_operand:DI 1 "gcn_alu_operand")
-   (match_operand:V_ALL 2 "register_operand")]
+   (match_operand:V_MOV 2 "register_operand")]
   "can_create_pseudo_p ()"
   {
     rtx dst = operands[0];
@@ -912,7 +1042,7 @@
   [(match_operand:<SCALAR_MODE> 0 "register_operand")
    (match_operand:<SCALAR_MODE> 1 "gcn_alu_operand")
    (match_operand:DI 2 "gcn_alu_operand")
-   (match_operand:V_ALL 3 "register_operand")]
+   (match_operand:V_MOV 3 "register_operand")]
   "can_create_pseudo_p ()"
   {
     rtx dst = operands[0];
@@ -934,7 +1064,7 @@
   })
 
 (define_expand "vec_init<mode><scalar_mode>"
-  [(match_operand:V_ALL 0 "register_operand")
+  [(match_operand:V_MOV 0 "register_operand")
    (match_operand 1)]
   ""
   {
@@ -942,11 +1072,11 @@
     DONE;
   })
 
-(define_expand "vec_init<V_ALL:mode><V_ALL_ALT:mode>"
-  [(match_operand:V_ALL 0 "register_operand")
-   (match_operand:V_ALL_ALT 1)]
-  "<V_ALL:SCALAR_MODE>mode == <V_ALL_ALT:SCALAR_MODE>mode
-   && MODE_VF (<V_ALL_ALT:MODE>mode) < MODE_VF (<V_ALL:MODE>mode)"
+(define_expand "vec_init<V_MOV:mode><V_MOV_ALT:mode>"
+  [(match_operand:V_MOV 0 "register_operand")
+   (match_operand:V_MOV_ALT 1)]
+  "<V_MOV:SCALAR_MODE>mode == <V_MOV_ALT:SCALAR_MODE>mode
+   && MODE_VF (<V_MOV_ALT:MODE>mode) < MODE_VF (<V_MOV:MODE>mode)"
   {
     gcn_expand_vector_init (operands[0], operands[1]);
     DONE;
@@ -988,7 +1118,7 @@
 ;; TODO: implement combined gather and zero_extend, but only for -msram-ecc=on
 
 (define_expand "gather_load<mode><vnsi>"
-  [(match_operand:V_ALL 0 "register_operand")
+  [(match_operand:V_MOV 0 "register_operand")
    (match_operand:DI 1 "register_operand")
    (match_operand:<VnSI> 2 "register_operand")
    (match_operand 3 "immediate_operand")
@@ -1011,8 +1141,8 @@
 
 ; Allow any address expression
 (define_expand "gather<mode>_expr<exec>"
-  [(set (match_operand:V_ALL 0 "register_operand")
-	(unspec:V_ALL
+  [(set (match_operand:V_MOV 0 "register_operand")
+	(unspec:V_MOV
 	  [(match_operand 1 "")
 	   (match_operand 2 "immediate_operand")
 	   (match_operand 3 "immediate_operand")
@@ -1022,8 +1152,8 @@
     {})
 
 (define_insn "gather<mode>_insn_1offset<exec>"
-  [(set (match_operand:V_ALL 0 "register_operand"		   "=v")
-	(unspec:V_ALL
+  [(set (match_operand:V_MOV 0 "register_operand"		   "=v")
+	(unspec:V_MOV
 	  [(plus:<VnDI> (match_operand:<VnDI> 1 "register_operand" " v")
 			(vec_duplicate:<VnDI>
 			  (match_operand 2 "immediate_operand"	   " n")))
@@ -1061,8 +1191,8 @@
    (set_attr "length" "12")])
 
 (define_insn "gather<mode>_insn_1offset_ds<exec>"
-  [(set (match_operand:V_ALL 0 "register_operand"		   "=v")
-	(unspec:V_ALL
+  [(set (match_operand:V_MOV 0 "register_operand"		   "=v")
+	(unspec:V_MOV
 	  [(plus:<VnSI> (match_operand:<VnSI> 1 "register_operand" " v")
 			(vec_duplicate:<VnSI>
 			  (match_operand 2 "immediate_operand"	   " n")))
@@ -1083,8 +1213,8 @@
    (set_attr "length" "12")])
 
 (define_insn "gather<mode>_insn_2offsets<exec>"
-  [(set (match_operand:V_ALL 0 "register_operand"			"=v")
-	(unspec:V_ALL
+  [(set (match_operand:V_MOV 0 "register_operand"			"=v")
+	(unspec:V_MOV
 	  [(plus:<VnDI>
 	     (plus:<VnDI>
 	       (vec_duplicate:<VnDI>
@@ -1119,7 +1249,7 @@
    (match_operand:<VnSI> 1 "register_operand")
    (match_operand 2 "immediate_operand")
    (match_operand:SI 3 "gcn_alu_operand")
-   (match_operand:V_ALL 4 "register_operand")]
+   (match_operand:V_MOV 4 "register_operand")]
   ""
   {
     rtx addr = gcn_expand_scaled_offsets (DEFAULT_ADDR_SPACE, operands[0],
@@ -1141,7 +1271,7 @@
   [(set (mem:BLK (scratch))
 	(unspec:BLK
 	  [(match_operand:<VnDI> 0 "")
-	   (match_operand:V_ALL 1 "register_operand")
+	   (match_operand:V_MOV 1 "register_operand")
 	   (match_operand 2 "immediate_operand")
 	   (match_operand 3 "immediate_operand")]
 	  UNSPEC_SCATTER))]
@@ -1154,7 +1284,7 @@
 	  [(plus:<VnDI> (match_operand:<VnDI> 0 "register_operand" "v")
 			(vec_duplicate:<VnDI>
 			  (match_operand 1 "immediate_operand"	   "n")))
-	   (match_operand:V_ALL 2 "register_operand"		   "v")
+	   (match_operand:V_MOV 2 "register_operand"		   "v")
 	   (match_operand 3 "immediate_operand"			   "n")
 	   (match_operand 4 "immediate_operand"			   "n")]
 	  UNSPEC_SCATTER))]
@@ -1192,7 +1322,7 @@
 	  [(plus:<VnSI> (match_operand:<VnSI> 0 "register_operand" "v")
 			(vec_duplicate:<VnSI>
 			  (match_operand 1 "immediate_operand"	   "n")))
-	   (match_operand:V_ALL 2 "register_operand"		   "v")
+	   (match_operand:V_MOV 2 "register_operand"		   "v")
 	   (match_operand 3 "immediate_operand"			   "n")
 	   (match_operand 4 "immediate_operand"			   "n")]
 	  UNSPEC_SCATTER))]
@@ -1218,7 +1348,7 @@
 	       (sign_extend:<VnDI>
 		 (match_operand:<VnSI> 1 "register_operand"		" v")))
 	     (vec_duplicate:<VnDI> (match_operand 2 "immediate_operand" " n")))
-	   (match_operand:V_ALL 3 "register_operand"			" v")
+	   (match_operand:V_MOV 3 "register_operand"			" v")
 	   (match_operand 4 "immediate_operand"				" n")
 	   (match_operand 5 "immediate_operand"				" n")]
 	  UNSPEC_SCATTER))]
@@ -3804,8 +3934,8 @@
   })
 
 (define_expand "maskload<mode>di"
-  [(match_operand:V_ALL 0 "register_operand")
-   (match_operand:V_ALL 1 "memory_operand")
+  [(match_operand:V_MOV 0 "register_operand")
+   (match_operand:V_MOV 1 "memory_operand")
    (match_operand 2 "")]
   ""
   {
@@ -3824,8 +3954,8 @@
   })
 
 (define_expand "maskstore<mode>di"
-  [(match_operand:V_ALL 0 "memory_operand")
-   (match_operand:V_ALL 1 "register_operand")
+  [(match_operand:V_MOV 0 "memory_operand")
+   (match_operand:V_MOV 1 "register_operand")
    (match_operand 2 "")]
   ""
   {
@@ -3839,7 +3969,7 @@
   })
 
 (define_expand "mask_gather_load<mode><vnsi>"
-  [(match_operand:V_ALL 0 "register_operand")
+  [(match_operand:V_MOV 0 "register_operand")
    (match_operand:DI 1 "register_operand")
    (match_operand:<VnSI> 2 "register_operand")
    (match_operand 3 "immediate_operand")
@@ -3874,7 +4004,7 @@
    (match_operand:<VnSI> 1 "register_operand")
    (match_operand 2 "immediate_operand")
    (match_operand:SI 3 "gcn_alu_operand")
-   (match_operand:V_ALL 4 "register_operand")
+   (match_operand:V_MOV 4 "register_operand")
    (match_operand:DI 5 "")]
   ""
   {
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index efb7211..02f4ded 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -489,7 +489,7 @@ gcn_class_max_nregs (reg_class_t rclass, machine_mode mode)
       if (vgpr_2reg_mode_p (mode))
 	return 2;
       /* TImode is used by DImode compare_and_swap.  */
-      if (mode == TImode)
+      if (vgpr_4reg_mode_p (mode))
 	return 4;
     }
   else if (rclass == VCC_CONDITIONAL_REG && mode == BImode)
@@ -592,9 +592,9 @@ gcn_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
        Therefore, we restrict ourselved to aligned registers.  */
     return (vgpr_1reg_mode_p (mode)
 	    || (!((regno - FIRST_VGPR_REG) & 1) && vgpr_2reg_mode_p (mode))
-	    /* TImode is used by DImode compare_and_swap.  */
-	    || (mode == TImode
-		&& !((regno - FIRST_VGPR_REG) & 3)));
+	    /* TImode is used by DImode compare_and_swap,
+	       and by DIVMOD V64DImode libfuncs.  */
+	    || (!((regno - FIRST_VGPR_REG) & 3) && vgpr_4reg_mode_p (mode)));
   return false;
 }
 
@@ -1326,6 +1326,7 @@ GEN_VN (PREFIX, si##SUFFIX, A(PARAMS), A(ARGS)) \
 GEN_VN (PREFIX, sf##SUFFIX, A(PARAMS), A(ARGS)) \
 GEN_VN (PREFIX, di##SUFFIX, A(PARAMS), A(ARGS)) \
 GEN_VN (PREFIX, df##SUFFIX, A(PARAMS), A(ARGS)) \
+USE_TI (GEN_VN (PREFIX, ti##SUFFIX, A(PARAMS), A(ARGS))) \
 static rtx \
 gen_##PREFIX##vNm##SUFFIX (PARAMS, rtx merge_src=NULL, rtx exec=NULL) \
 { \
@@ -1340,6 +1341,8 @@ gen_##PREFIX##vNm##SUFFIX (PARAMS, rtx merge_src=NULL, rtx exec=NULL) \
     case E_SFmode: return gen_##PREFIX##vNsf##SUFFIX (ARGS, merge_src, exec); \
     case E_DImode: return gen_##PREFIX##vNdi##SUFFIX (ARGS, merge_src, exec); \
     case E_DFmode: return gen_##PREFIX##vNdf##SUFFIX (ARGS, merge_src, exec); \
+    case E_TImode: \
+	USE_TI (return gen_##PREFIX##vNti##SUFFIX (ARGS, merge_src, exec);) \
     default: \
       break; \
     } \
@@ -1348,6 +1351,14 @@ gen_##PREFIX##vNm##SUFFIX (PARAMS, rtx merge_src=NULL, rtx exec=NULL) \
   return NULL_RTX; \
 }
 
+/* These have TImode support.  */
+#define USE_TI(ARGS) ARGS
+GEN_VNM (mov,, A(rtx dest, rtx src), A(dest, src))
+GEN_VNM (vec_duplicate,, A(rtx dest, rtx src), A(dest, src))
+
+/* These do not have TImode support.  */
+#undef USE_TI
+#define USE_TI(ARGS)
 GEN_VNM (add,3, A(rtx dest, rtx src1, rtx src2), A(dest, src1, src2))
 GEN_VN (add,si3_dup, A(rtx dest, rtx src1, rtx src2), A(dest, src1, src2))
 GEN_VN (add,si3_vcc_dup, A(rtx dest, rtx src1, rtx src2, rtx vcc),
@@ -1366,12 +1377,11 @@ GEN_VNM_NOEXEC (ds_bpermute,, A(rtx dest, rtx addr, rtx src, rtx exec),
 		A(dest, addr, src, exec))
 GEN_VNM (gather,_expr, A(rtx dest, rtx addr, rtx as, rtx vol),
 	 A(dest, addr, as, vol))
-GEN_VNM (mov,, A(rtx dest, rtx src), A(dest, src))
 GEN_VN (mul,si3_dup, A(rtx dest, rtx src1, rtx src2), A(dest, src1, src2))
 GEN_VN (sub,si3, A(rtx dest, rtx src1, rtx src2), A(dest, src1, src2))
-GEN_VNM (vec_duplicate,, A(rtx dest, rtx src), A(dest, src))
 GEN_VN_NOEXEC (vec_series,si, A(rtx dest, rtx x, rtx c), A(dest, x, c))
 
+#undef USE_TI
 #undef GEN_VNM
 #undef GEN_VN
 #undef GET_VN_FN
@@ -1405,6 +1415,7 @@ get_code_for_##PREFIX##vN##SUFFIX (int nunits) \
 	CODE_FOR (PREFIX, sf) \
 	CODE_FOR (PREFIX, di) \
 	CODE_FOR (PREFIX, df) \
+	CODE_FOR (PREFIX, ti) \
 static int \
 get_code_for_##PREFIX (machine_mode mode) \
 { \
@@ -1420,6 +1431,7 @@ get_code_for_##PREFIX (machine_mode mode) \
     case E_SFmode: return get_code_for_##PREFIX##vNsf (vf); \
     case E_DImode: return get_code_for_##PREFIX##vNdi (vf); \
     case E_DFmode: return get_code_for_##PREFIX##vNdf (vf); \
+    case E_TImode: return get_code_for_##PREFIX##vNti (vf); \
     default: break; \
     } \
   \
@@ -3774,6 +3786,47 @@ gcn_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
 					      TRAMPOLINE_SIZE)));
 }
 
+/* Implement TARGET_EXPAND_DIVMOD_LIBFUNC.
+
+   There are divmod libfuncs for all modes except TImode.  They return the
+   two values packed into a larger integer/vector.  */
+
+void
+gcn_expand_divmod_libfunc (rtx libfunc, machine_mode mode, rtx op0, rtx op1,
+			   rtx *quot, rtx *rem)
+{
+  machine_mode innermode = (VECTOR_MODE_P (mode)
+			    ? GET_MODE_INNER (mode) : mode);
+  machine_mode wideinnermode = VOIDmode;
+  machine_mode widemode = VOIDmode;
+
+  switch (innermode)
+    {
+    case E_QImode:
+    case E_HImode:
+    case E_SImode:
+      wideinnermode = DImode;
+      break;
+    case E_DImode:
+      wideinnermode = TImode;
+      break;
+    default:
+      gcc_unreachable ();
+    }
+
+  if (VECTOR_MODE_P (mode))
+    widemode = VnMODE (GET_MODE_NUNITS (mode), wideinnermode);
+  else
+    widemode = wideinnermode;
+
+  emit_library_call_value (libfunc, gen_rtx_REG (widemode, RETURN_VALUE_REG),
+			   LCT_NORMAL, widemode, op0, mode, op1, mode);
+
+  *quot = gen_rtx_REG (mode, RETURN_VALUE_REG);
+  *rem = gen_rtx_REG (mode,
+		      RETURN_VALUE_REG + (wideinnermode == TImode ? 2 : 1));
+}
+
 /* }}}  */
 /* {{{ Miscellaneous.  */
 
@@ -4212,6 +4265,207 @@ gcn_init_libfuncs (void)
   set_optab_libfunc (popcount_optab, TImode, "__popcountti2");
   set_optab_libfunc (parity_optab, TImode, "__parityti2");
   set_optab_libfunc (bswap_optab, TImode, "__bswapti2");
+
+  set_optab_libfunc (sdivmod_optab, SImode, "__divmodsi4");
+  set_optab_libfunc (udivmod_optab, SImode, "__udivmodsi4");
+  set_optab_libfunc (sdivmod_optab, DImode, "__divmoddi4");
+  set_optab_libfunc (udivmod_optab, DImode, "__udivmoddi4");
+
+  set_optab_libfunc (sdiv_optab, V2QImode, "__divv2qi3");
+  set_optab_libfunc (udiv_optab, V2QImode, "__udivv2qi3");
+  set_optab_libfunc (smod_optab, V2QImode, "__modv2qi3");
+  set_optab_libfunc (umod_optab, V2QImode, "__umodv2qi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V2QImode, "__divmodv2qi4");
+  set_optab_libfunc (udivmod_optab, V2QImode, "__udivmodv2qi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V4QImode, "__divv4qi3");
+  set_optab_libfunc (udiv_optab, V4QImode, "__udivv4qi3");
+  set_optab_libfunc (smod_optab, V4QImode, "__modv4qi3");
+  set_optab_libfunc (umod_optab, V4QImode, "__umodv4qi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V4QImode, "__divmodv4qi4");
+  set_optab_libfunc (udivmod_optab, V4QImode, "__udivmodv4qi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V8QImode, "__divv8qi3");
+  set_optab_libfunc (udiv_optab, V8QImode, "__udivv8qi3");
+  set_optab_libfunc (smod_optab, V8QImode, "__modv8qi3");
+  set_optab_libfunc (umod_optab, V8QImode, "__umodv8qi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V8QImode, "__divmodv8qi4");
+  set_optab_libfunc (udivmod_optab, V8QImode, "__udivmodv8qi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V16QImode, "__divv16qi3");
+  set_optab_libfunc (udiv_optab, V16QImode, "__udivv16qi3");
+  set_optab_libfunc (smod_optab, V16QImode, "__modv16qi3");
+  set_optab_libfunc (umod_optab, V16QImode, "__umodv16qi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V16QImode, "__divmodv16qi4");
+  set_optab_libfunc (udivmod_optab, V16QImode, "__udivmodv16qi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V32QImode, "__divv32qi3");
+  set_optab_libfunc (udiv_optab, V32QImode, "__udivv32qi3");
+  set_optab_libfunc (smod_optab, V32QImode, "__modv32qi3");
+  set_optab_libfunc (umod_optab, V32QImode, "__umodv32qi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V32QImode, "__divmodv32qi4");
+  set_optab_libfunc (udivmod_optab, V32QImode, "__udivmodv32qi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V64QImode, "__divv64qi3");
+  set_optab_libfunc (udiv_optab, V64QImode, "__udivv64qi3");
+  set_optab_libfunc (smod_optab, V64QImode, "__modv64qi3");
+  set_optab_libfunc (umod_optab, V64QImode, "__umodv64qi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V64QImode, "__divmodv64qi4");
+  set_optab_libfunc (udivmod_optab, V64QImode, "__udivmodv64qi4");
+#endif
+
+  set_optab_libfunc (sdiv_optab, V2HImode, "__divv2hi3");
+  set_optab_libfunc (udiv_optab, V2HImode, "__udivv2hi3");
+  set_optab_libfunc (smod_optab, V2HImode, "__modv2hi3");
+  set_optab_libfunc (umod_optab, V2HImode, "__umodv2hi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V2HImode, "__divmodv2hi4");
+  set_optab_libfunc (udivmod_optab, V2HImode, "__udivmodv2hi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V4HImode, "__divv4hi3");
+  set_optab_libfunc (udiv_optab, V4HImode, "__udivv4hi3");
+  set_optab_libfunc (smod_optab, V4HImode, "__modv4hi3");
+  set_optab_libfunc (umod_optab, V4HImode, "__umodv4hi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V4HImode, "__divmodv4hi4");
+  set_optab_libfunc (udivmod_optab, V4HImode, "__udivmodv4hi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V8HImode, "__divv8hi3");
+  set_optab_libfunc (udiv_optab, V8HImode, "__udivv8hi3");
+  set_optab_libfunc (smod_optab, V8HImode, "__modv8hi3");
+  set_optab_libfunc (umod_optab, V8HImode, "__umodv8hi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V8HImode, "__divmodv8hi4");
+  set_optab_libfunc (udivmod_optab, V8HImode, "__udivmodv8hi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V16HImode, "__divv16hi3");
+  set_optab_libfunc (udiv_optab, V16HImode, "__udivv16hi3");
+  set_optab_libfunc (smod_optab, V16HImode, "__modv16hi3");
+  set_optab_libfunc (umod_optab, V16HImode, "__umodv16hi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V16HImode, "__divmodv16hi4");
+  set_optab_libfunc (udivmod_optab, V16HImode, "__udivmodv16hi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V32HImode, "__divv32hi3");
+  set_optab_libfunc (udiv_optab, V32HImode, "__udivv32hi3");
+  set_optab_libfunc (smod_optab, V32HImode, "__modv32hi3");
+  set_optab_libfunc (umod_optab, V32HImode, "__umodv32hi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V32HImode, "__divmodv32hi4");
+  set_optab_libfunc (udivmod_optab, V32HImode, "__udivmodv32hi4");
+#endif
+  set_optab_libfunc (sdiv_optab, V64HImode, "__divv64hi3");
+  set_optab_libfunc (udiv_optab, V64HImode, "__udivv64hi3");
+  set_optab_libfunc (smod_optab, V64HImode, "__modv64hi3");
+  set_optab_libfunc (umod_optab, V64HImode, "__umodv64hi3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V64HImode, "__divmodv64hi4");
+  set_optab_libfunc (udivmod_optab, V64HImode, "__udivmodv64hi4");
+#endif
+
+  set_optab_libfunc (sdiv_optab, V2SImode, "__divv2si3");
+  set_optab_libfunc (udiv_optab, V2SImode, "__udivv2si3");
+  set_optab_libfunc (smod_optab, V2SImode, "__modv2si3");
+  set_optab_libfunc (umod_optab, V2SImode, "__umodv2si3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V2SImode, "__divmodv2si4");
+  set_optab_libfunc (udivmod_optab, V2SImode, "__udivmodv2si4");
+#endif
+  set_optab_libfunc (sdiv_optab, V4SImode, "__divv4si3");
+  set_optab_libfunc (udiv_optab, V4SImode, "__udivv4si3");
+  set_optab_libfunc (smod_optab, V4SImode, "__modv4si3");
+  set_optab_libfunc (umod_optab, V4SImode, "__umodv4si3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V4SImode, "__divmodv4si4");
+  set_optab_libfunc (udivmod_optab, V4SImode, "__udivmodv4si4");
+#endif
+  set_optab_libfunc (sdiv_optab, V8SImode, "__divv8si3");
+  set_optab_libfunc (udiv_optab, V8SImode, "__udivv8si3");
+  set_optab_libfunc (smod_optab, V8SImode, "__modv8si3");
+  set_optab_libfunc (umod_optab, V8SImode, "__umodv8si3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V8SImode, "__divmodv8si4");
+  set_optab_libfunc (udivmod_optab, V8SImode, "__udivmodv8si4");
+#endif
+  set_optab_libfunc (sdiv_optab, V16SImode, "__divv16si3");
+  set_optab_libfunc (udiv_optab, V16SImode, "__udivv16si3");
+  set_optab_libfunc (smod_optab, V16SImode, "__modv16si3");
+  set_optab_libfunc (umod_optab, V16SImode, "__umodv16si3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V16SImode, "__divmodv16si4");
+  set_optab_libfunc (udivmod_optab, V16SImode, "__udivmodv16si4");
+#endif
+  set_optab_libfunc (sdiv_optab, V32SImode, "__divv32si3");
+  set_optab_libfunc (udiv_optab, V32SImode, "__udivv32si3");
+  set_optab_libfunc (smod_optab, V32SImode, "__modv32si3");
+  set_optab_libfunc (umod_optab, V32SImode, "__umodv32si3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V32SImode, "__divmodv32si4");
+  set_optab_libfunc (udivmod_optab, V32SImode, "__udivmodv32si4");
+#endif
+  set_optab_libfunc (sdiv_optab, V64SImode, "__divv64si3");
+  set_optab_libfunc (udiv_optab, V64SImode, "__udivv64si3");
+  set_optab_libfunc (smod_optab, V64SImode, "__modv64si3");
+  set_optab_libfunc (umod_optab, V64SImode, "__umodv64si3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V64SImode, "__divmodv64si4");
+  set_optab_libfunc (udivmod_optab, V64SImode, "__udivmodv64si4");
+#endif
+
+  set_optab_libfunc (sdiv_optab, V2DImode, "__divv2di3");
+  set_optab_libfunc (udiv_optab, V2DImode, "__udivv2di3");
+  set_optab_libfunc (smod_optab, V2DImode, "__modv2di3");
+  set_optab_libfunc (umod_optab, V2DImode, "__umodv2di3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V2DImode, "__divmodv2di4");
+  set_optab_libfunc (udivmod_optab, V2DImode, "__udivmodv2di4");
+#endif
+  set_optab_libfunc (sdiv_optab, V4DImode, "__divv4di3");
+  set_optab_libfunc (udiv_optab, V4DImode, "__udivv4di3");
+  set_optab_libfunc (smod_optab, V4DImode, "__modv4di3");
+  set_optab_libfunc (umod_optab, V4DImode, "__umodv4di3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V4DImode, "__divmodv4di4");
+  set_optab_libfunc (udivmod_optab, V4DImode, "__udivmodv4di4");
+#endif
+  set_optab_libfunc (sdiv_optab, V8DImode, "__divv8di3");
+  set_optab_libfunc (udiv_optab, V8DImode, "__udivv8di3");
+  set_optab_libfunc (smod_optab, V8DImode, "__modv8di3");
+  set_optab_libfunc (umod_optab, V8DImode, "__umodv8di3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V8DImode, "__divmodv8di4");
+  set_optab_libfunc (udivmod_optab, V8DImode, "__udivmodv8di4");
+#endif
+  set_optab_libfunc (sdiv_optab, V16DImode, "__divv16di3");
+  set_optab_libfunc (udiv_optab, V16DImode, "__udivv16di3");
+  set_optab_libfunc (smod_optab, V16DImode, "__modv16di3");
+  set_optab_libfunc (umod_optab, V16DImode, "__umodv16di3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V16DImode, "__divmodv16di4");
+  set_optab_libfunc (udivmod_optab, V16DImode, "__udivmodv16di4");
+#endif
+  set_optab_libfunc (sdiv_optab, V32DImode, "__divv32di3");
+  set_optab_libfunc (udiv_optab, V32DImode, "__udivv32di3");
+  set_optab_libfunc (smod_optab, V32DImode, "__modv32di3");
+  set_optab_libfunc (umod_optab, V32DImode, "__umodv32di3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V32DImode, "__divmodv32di4");
+  set_optab_libfunc (udivmod_optab, V32DImode, "__udivmodv32di4");
+#endif
+  set_optab_libfunc (sdiv_optab, V64DImode, "__divv64di3");
+  set_optab_libfunc (udiv_optab, V64DImode, "__udivv64di3");
+  set_optab_libfunc (smod_optab, V64DImode, "__modv64di3");
+  set_optab_libfunc (umod_optab, V64DImode, "__umodv64di3");
+#if 0
+  set_optab_libfunc (sdivmod_optab, V64DImode, "__divmodv64di4");
+  set_optab_libfunc (udivmod_optab, V64DImode, "__udivmodv64di4");
+#endif
 }
 
 /* Expand the CMP_SWAP GCN builtins.  We have our own versions that do
@@ -4895,7 +5149,13 @@ gcn_vector_mode_supported_p (machine_mode mode)
 	  || mode == V4SFmode || mode == V4DFmode
 	  || mode == V2QImode || mode == V2HImode
 	  || mode == V2SImode || mode == V2DImode
-	  || mode == V2SFmode || mode == V2DFmode);
+	  || mode == V2SFmode || mode == V2DFmode
+	  /* TImode vectors are allowed to exist for divmod, but there
+	     are almost no instructions defined for them, and the
+	     autovectorizer does not use them.  */
+	  || mode == V64TImode || mode == V32TImode
+	  || mode == V16TImode || mode == V8TImode
+	  || mode == V4TImode || mode == V2TImode);
 }
 
 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
@@ -6722,6 +6982,10 @@ print_operand_address (FILE *file, rtx mem)
    O - print offset:n for data share operations.
    ^ - print "_co" suffix for GCN5 mnemonics
    g - print "glc", if appropriate for given MEM
+   L - print low-part of a multi-reg value
+   H - print second part of a multi-reg value (high-part of 2-reg value)
+   J - print third part of a multi-reg value
+   K - print fourth part of a multi-reg value
  */
 
 void
@@ -7261,6 +7525,12 @@ print_operand (FILE *file, rtx x, int code)
     case 'H':
       print_operand (file, gcn_operand_part (GET_MODE (x), x, 1), 0);
       return;
+    case 'J':
+      print_operand (file, gcn_operand_part (GET_MODE (x), x, 2), 0);
+      return;
+    case 'K':
+      print_operand (file, gcn_operand_part (GET_MODE (x), x, 3), 0);
+      return;
     case 'R':
       /* Print a scalar register number as an integer.  Temporary hack.  */
       gcc_assert (REG_P (x));
@@ -7467,6 +7737,8 @@ gcn_dwarf_register_span (rtx rtl)
 #define TARGET_EMUTLS_VAR_INIT gcn_emutls_var_init
 #undef  TARGET_EXPAND_BUILTIN
 #define TARGET_EXPAND_BUILTIN gcn_expand_builtin
+#undef  TARGET_EXPAND_DIVMOD_LIBFUNC
+#define TARGET_EXPAND_DIVMOD_LIBFUNC gcn_expand_divmod_libfunc
 #undef  TARGET_FRAME_POINTER_REQUIRED
 #define TARGET_FRAME_POINTER_REQUIRED gcn_frame_pointer_rqd
 #undef  TARGET_FUNCTION_ARG
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index def060a..7bb4d39 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -521,7 +521,8 @@ ix86_expand_move (machine_mode mode, rtx operands[])
 		  return;
 		}
 	    }
-	  else if (GET_MODE_SIZE (mode) >= 16)
+	  else if (CONST_WIDE_INT_P (op1)
+		   && GET_MODE_SIZE (mode) >= 16)
 	    {
 	      rtx tmp = ix86_convert_const_wide_int_to_broadcast
 		(GET_MODE (op0), op1);
@@ -696,8 +697,9 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
       return;
     }
 
-  /* Special case TImode to V1TImode conversions, via V2DI.  */
-  if (mode == V1TImode
+  /* Special case TImode to 128-bit vector conversions via V2DI.  */
+  if (VECTOR_MODE_P (mode)
+      && GET_MODE_SIZE (mode) == 16
       && SUBREG_P (op1)
       && GET_MODE (SUBREG_REG (op1)) == TImode
       && TARGET_64BIT && TARGET_SSE
@@ -709,7 +711,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[])
       emit_move_insn (lo, gen_lowpart (DImode, SUBREG_REG (op1)));
       emit_move_insn (hi, gen_highpart (DImode, SUBREG_REG (op1)));
       emit_insn (gen_vec_concatv2di (tmp, lo, hi));
-      emit_move_insn (op0, gen_lowpart (V1TImode, tmp));
+      emit_move_insn (op0, gen_lowpart (mode, tmp));
       return;
     }
 
@@ -1019,6 +1021,7 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code)
   rtx op0 = operands[0];
   rtx op1 = operands[1];
   rtx op2 = operands[2];
+  rtx src;
 
   machine_mode dmode = GET_MODE (op0);
   machine_mode smode = GET_MODE (op1);
@@ -1042,11 +1045,20 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code)
   op1 = lowpart_subreg (sse_smode, op1, GET_MODE (op1));
   op2 = lowpart_subreg (sse_smode, op2, GET_MODE (op2));
 
-  op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1);
-  op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2);
-  rtx insn = gen_rtx_SET (dest, gen_rtx_VEC_CONCAT (sse_dmode,
-						    op1, op2));
-  emit_insn (insn);
+  /* paskusdw/packuswb does unsigned saturation of a signed source
+     which is different from generic us_truncate RTX.  */
+  if (code == US_TRUNCATE)
+    src = gen_rtx_UNSPEC (sse_dmode,
+			  gen_rtvec (2, op1, op2),
+			  UNSPEC_US_TRUNCATE);
+  else
+    {
+      op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1);
+      op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2);
+      src = gen_rtx_VEC_CONCAT (sse_dmode, op1, op2);
+    }
+
+  emit_move_insn (dest, src);
 
   ix86_move_vector_high_sse_to_mmx (op0);
 }
@@ -2266,7 +2278,7 @@ ix86_expand_copysign (rtx operands[])
   else
     dest = NULL_RTX;
   op1 = lowpart_subreg (vmode, force_reg (mode, operands[2]), mode);
-  mask = ix86_build_signbit_mask (vmode, 0, 0);
+  mask = ix86_build_signbit_mask (vmode, TARGET_AVX512F && mode != HFmode, 0);
 
   if (CONST_DOUBLE_P (operands[1]))
     {
@@ -12644,6 +12656,21 @@ ix86_check_builtin_isa_match (unsigned int fcode,
   return (bisa & isa) == bisa && (bisa2 & isa2) == bisa2;
 }
 
+/* Emit instructions to set the carry flag from ARG.  */
+
+void
+ix86_expand_carry (rtx arg)
+{
+  if (!CONST_INT_P (arg) || arg == const0_rtx)
+    {
+      arg = convert_to_mode (QImode, arg, 1);
+      arg = copy_to_mode_reg (QImode, arg);
+      emit_insn (gen_addqi3_cconly_overflow (arg, constm1_rtx));
+    }
+  else
+    emit_insn (gen_x86_stc ());
+}
+
 /* Expand an expression EXP that calls a built-in function,
    with result going to TARGET if that's convenient
    (and in mode MODE if that's convenient).
@@ -13975,14 +14002,7 @@ rdseed_step:
       else
 	{
 	  /* Generate CF from input operand.  */
-	  if (!CONST_INT_P (op1))
-	    {
-	      op1 = convert_to_mode (QImode, op1, 1);
-	      op1 = copy_to_mode_reg (QImode, op1);
-	      emit_insn (gen_addqi3_cconly_overflow (op1, constm1_rtx));
-	    }
-	  else
-	    emit_insn (gen_x86_stc ());
+	  ix86_expand_carry (op1);
 
 	  /* Generate instruction that consumes CF.  */
 	  op1 = gen_rtx_REG (CCCmode, FLAGS_REG);
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index af01299..27fe73c 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -155,6 +155,7 @@ extern void ix86_expand_sse_movcc (rtx, rtx, rtx, rtx);
 extern void ix86_expand_sse_unpack (rtx, rtx, bool, bool);
 extern void ix86_expand_fp_spaceship (rtx, rtx, rtx);
 extern bool ix86_expand_int_addcc (rtx[]);
+extern void ix86_expand_carry (rtx arg);
 extern rtx_insn *ix86_expand_call (rtx, rtx, rtx, rtx, rtx, bool);
 extern bool ix86_call_use_plt_p (rtx);
 extern void ix86_split_call_vzeroupper (rtx, rtx);
diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index b20cb86..32851a5 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -23666,6 +23666,7 @@ class ix86_vector_costs : public vector_costs
 			      stmt_vec_info stmt_info, slp_tree node,
 			      tree vectype, int misalign,
 			      vect_cost_model_location where) override;
+  void finish_cost (const vector_costs *) override;
 };
 
 /* Implement targetm.vectorize.create_costs.  */
@@ -23918,6 +23919,31 @@ ix86_vector_costs::add_stmt_cost (int count, vect_cost_for_stmt kind,
   return retval;
 }
 
+void
+ix86_vector_costs::finish_cost (const vector_costs *scalar_costs)
+{
+  loop_vec_info loop_vinfo = dyn_cast<loop_vec_info> (m_vinfo);
+  if (loop_vinfo && !m_costing_for_scalar)
+    {
+      /* We are currently not asking the vectorizer to compare costs
+	 between different vector mode sizes.  When using predication
+	 that will end up always choosing the prefered mode size even
+	 if there's a smaller mode covering all lanes.  Test for this
+	 situation and artificially reject the larger mode attempt.
+	 ???  We currently lack masked ops for sub-SSE sized modes,
+	 so we could restrict this rejection to AVX and AVX512 modes
+	 but error on the safe side for now.  */
+      if (LOOP_VINFO_USING_PARTIAL_VECTORS_P (loop_vinfo)
+	  && !LOOP_VINFO_EPILOGUE_P (loop_vinfo)
+	  && LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
+	  && (exact_log2 (LOOP_VINFO_VECT_FACTOR (loop_vinfo).to_constant ())
+	      > ceil_log2 (LOOP_VINFO_INT_NITERS (loop_vinfo))))
+	m_costs[vect_body] = INT_MAX;
+    }
+
+  vector_costs::finish_cost (scalar_costs);
+}
+
 /* Validate target specific memory model bits in VAL. */
 
 static unsigned HOST_WIDE_INT
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 93794c1..95a6653c 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -129,6 +129,10 @@
   UNSPEC_RSQRT
   UNSPEC_PSADBW
 
+  ;; Different from generic us_truncate RTX
+  ;; as it does unsigned saturation of signed source.
+  UNSPEC_US_TRUNCATE
+
   ;; For AVX/AVX512F support
   UNSPEC_SCALEF
   UNSPEC_PCMP
@@ -8601,9 +8605,7 @@
     emit_insn (gen_addcarry<mode>_0 (operands[0], operands[2], operands[3]));
   else
     {
-      rtx op4 = copy_to_mode_reg (QImode,
-				  convert_to_mode (QImode, operands[4], 1));
-      emit_insn (gen_addqi3_cconly_overflow (op4, constm1_rtx));
+      ix86_expand_carry (operands[4]);
       pat = gen_rtx_LTU (<DWI>mode, cf, const0_rtx);
       pat2 = gen_rtx_LTU (<MODE>mode, cf, const0_rtx);
       emit_insn (gen_addcarry<mode> (operands[0], operands[2], operands[3],
@@ -8634,9 +8636,7 @@
   else
     {
       cf = gen_rtx_REG (CCCmode, FLAGS_REG);
-      rtx op4 = copy_to_mode_reg (QImode,
-				  convert_to_mode (QImode, operands[4], 1));
-      emit_insn (gen_addqi3_cconly_overflow (op4, constm1_rtx));
+      ix86_expand_carry (operands[4]);
       pat = gen_rtx_LTU (<DWI>mode, cf, const0_rtx);
       pat2 = gen_rtx_LTU (<MODE>mode, cf, const0_rtx);
       emit_insn (gen_subborrow<mode> (operands[0], operands[2], operands[3],
@@ -12211,7 +12211,7 @@
   [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
 	(any_or_plus:<DWI>
 	  (ashift:<DWI> (match_operand:<DWI> 1 "register_operand" "r,r")
-			(match_operand:<DWI> 2 "const_int_operand"))
+			(match_operand:QI 2 "const_int_operand"))
 	  (zero_extend:<DWI>
 	    (match_operand:DWIH 3 "nonimmediate_operand" "r,m"))))]
   "INTVAL (operands[2]) == <MODE_SIZE> * BITS_PER_UNIT"
@@ -12230,7 +12230,7 @@
 	  (zero_extend:<DWI>
 	    (match_operand:DWIH 1 "nonimmediate_operand" "r,m"))
 	  (ashift:<DWI> (match_operand:<DWI> 2 "register_operand" "r,r")
-			(match_operand:<DWI> 3 "const_int_operand"))))]
+			(match_operand:QI 3 "const_int_operand"))))]
   "INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
   "#"
   "&& reload_completed"
@@ -12247,7 +12247,7 @@
 	  (ashift:<DWI>
 	    (zero_extend:<DWI>
 	      (match_operand:DWIH 1 "nonimmediate_operand" "r,m,r,m"))
-	    (match_operand:<DWI> 2 "const_int_operand"))
+	    (match_operand:QI 2 "const_int_operand"))
 	  (zero_extend:<DWI>
 	    (match_operand:DWIH 3 "nonimmediate_operand" "r,r,m,m"))))]
   "INTVAL (operands[2]) == <MODE_SIZE> * BITS_PER_UNIT"
@@ -12267,7 +12267,7 @@
 	  (ashift:<DWI>
 	    (zero_extend:<DWI>
 	      (match_operand:DWIH 2 "nonimmediate_operand" "r,r,m,m"))
-	    (match_operand:<DWI> 3 "const_int_operand"))))]
+	    (match_operand:QI 3 "const_int_operand"))))]
   "INTVAL (operands[3]) == <MODE_SIZE> * BITS_PER_UNIT"
   "#"
   "&& reload_completed"
@@ -12281,7 +12281,7 @@
   [(set (match_operand:DWI 0 "nonimmediate_operand" "=r,o,o")
 	(any_or_plus:DWI
 	  (ashift:DWI (match_operand:DWI 1 "register_operand" "r,r,r")
-		      (match_operand:DWI 2 "const_int_operand"))
+		      (match_operand:QI 2 "const_int_operand"))
 	  (match_operand:DWI 3 "const_scalar_int_operand" "n,n,Wd")))]
   "INTVAL (operands[2]) == <MODE_SIZE> * BITS_PER_UNIT / 2
    && (<MODE>mode == DImode
@@ -12313,7 +12313,7 @@
 	  (ashift:<DWI>
 	    (zero_extend:<DWI>
 	      (match_operand:DWIH 1 "nonimmediate_operand" "r,r,r,m"))
-	    (match_operand:<DWI> 2 "const_int_operand"))
+	    (match_operand:QI 2 "const_int_operand"))
 	  (match_operand:<DWI> 3 "const_scalar_int_operand" "n,n,Wd,n")))]
   "INTVAL (operands[2]) == <MODE_SIZE> * BITS_PER_UNIT
    && (<DWI>mode == DImode
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 6fbe390..12b103a 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3337,27 +3337,43 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-;; Used in signed and unsigned truncations with saturation.
-(define_code_iterator any_s_truncate [ss_truncate us_truncate])
-;; Instruction suffix for truncations with saturation.
-(define_code_attr s_trunsuffix [(ss_truncate "s") (us_truncate "u")])
-
-(define_insn_and_split "mmx_pack<s_trunsuffix>swb"
+(define_insn_and_split "mmx_packsswb"
   [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
 	(vec_concat:V8QI
-	  (any_s_truncate:V4QI
+	  (ss_truncate:V4QI
 	    (match_operand:V4HI 1 "register_operand" "0,0,Yw"))
-	  (any_s_truncate:V4QI
+	  (ss_truncate:V4QI
 	    (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
   "TARGET_MMX || TARGET_MMX_WITH_SSE"
   "@
-   pack<s_trunsuffix>swb\t{%2, %0|%0, %2}
+   packsswb\t{%2, %0|%0, %2}
+   #
+   #"
+  "&& reload_completed
+   && SSE_REGNO_P (REGNO (operands[0]))"
+  [(const_int 0)]
+  "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
+  [(set_attr "mmx_isa" "native,sse_noavx,avx")
+   (set_attr "type" "mmxshft,sselog,sselog")
+   (set_attr "mode" "DI,TI,TI")])
+
+;; This instruction does unsigned saturation of signed source
+;; and is different from generic us_truncate RTX.
+(define_insn_and_split "mmx_packuswb"
+  [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
+	(unspec:V8QI
+	  [(match_operand:V4HI 1 "register_operand" "0,0,Yw")
+	   (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")]
+	  UNSPEC_US_TRUNCATE))]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+  "@
+   packuswb\t{%2, %0|%0, %2}
    #
    #"
   "&& reload_completed
    && SSE_REGNO_P (REGNO (operands[0]))"
   [(const_int 0)]
-  "ix86_split_mmx_pack (operands, <any_s_truncate:CODE>); DONE;"
+  "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
   [(set_attr "mmx_isa" "native,sse_noavx,avx")
    (set_attr "type" "mmxshft,sselog,sselog")
    (set_attr "mode" "DI,TI,TI")])
@@ -3384,11 +3400,10 @@
 
 (define_insn_and_split "mmx_packusdw"
   [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
-	(vec_concat:V4HI
-	  (us_truncate:V2HI
-	    (match_operand:V2SI 1 "register_operand" "0,0,Yw"))
-	  (us_truncate:V2HI
-	    (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw"))))]
+	(unspec:V4HI
+	  [(match_operand:V2SI 1 "register_operand" "0,0,Yw")
+	   (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw")]
+	   UNSPEC_US_TRUNCATE))]
   "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
   "#"
   "&& reload_completed"
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 70d7410..f793258 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -12597,22 +12597,35 @@
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "*<avx512>_vternlog<mode>_all"
-  [(set (match_operand:V 0 "register_operand" "=v")
+  [(set (match_operand:V 0 "register_operand" "=v,v")
 	(unspec:V
-	  [(match_operand:V 1 "register_operand" "0")
-	   (match_operand:V 2 "register_operand" "v")
-	   (match_operand:V 3 "bcst_vector_operand" "vmBr")
+	  [(match_operand:V 1 "register_operand" "0,0")
+	   (match_operand:V 2 "register_operand" "v,v")
+	   (match_operand:V 3 "bcst_vector_operand" "vBr,m")
 	   (match_operand:SI 4 "const_0_to_255_operand")]
 	  UNSPEC_VTERNLOG))]
-  "TARGET_AVX512F
+  "(<MODE_SIZE> == 64 || TARGET_AVX512VL
+    || (TARGET_AVX512F && !TARGET_PREFER_AVX256))
 /* Disallow embeded broadcast for vector HFmode since
    it's not real AVX512FP16 instruction.  */
   && (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) >= 4
      || GET_CODE (operands[3]) != VEC_DUPLICATE)"
-  "vpternlog<ternlogsuffix>\t{%4, %3, %2, %0|%0, %2, %3, %4}"
+{
+  if (TARGET_AVX512VL)
+    return "vpternlog<ternlogsuffix>\t{%4, %3, %2, %0|%0, %2, %3, %4}";
+  else
+    return "vpternlog<ternlogsuffix>\t{%4, %g3, %g2, %g0|%g0, %g2, %g3, %4}";
+}
   [(set_attr "type" "sselog")
    (set_attr "prefix" "evex")
-   (set_attr "mode" "<sseinsnmode>")])
+   (set (attr "mode")
+        (if_then_else (match_test "TARGET_AVX512VL")
+		      (const_string "<sseinsnmode>")
+		      (const_string "XI")))
+   (set (attr "enabled")
+	(if_then_else (eq_attr "alternative" "1")
+		      (symbol_ref "<MODE_SIZE> == 64 || TARGET_AVX512VL")
+		      (const_string "*")))])
 
 ;; There must be lots of other combinations like
 ;;
@@ -12641,7 +12654,8 @@
 	  (any_logic2:V
 	    (match_operand:V 3 "regmem_or_bitnot_regmem_operand")
 	    (match_operand:V 4 "regmem_or_bitnot_regmem_operand"))))]
-  "(<MODE_SIZE> == 64 || TARGET_AVX512VL)
+  "(<MODE_SIZE> == 64 || TARGET_AVX512VL
+    || (TARGET_AVX512F && !TARGET_PREFER_AVX256))
    && ix86_pre_reload_split ()
    && (rtx_equal_p (STRIP_UNARY (operands[1]),
 		    STRIP_UNARY (operands[4]))
@@ -12725,7 +12739,8 @@
 	      (match_operand:V 2 "regmem_or_bitnot_regmem_operand"))
 	    (match_operand:V 3 "regmem_or_bitnot_regmem_operand"))
 	  (match_operand:V 4 "regmem_or_bitnot_regmem_operand")))]
-  "(<MODE_SIZE> == 64 || TARGET_AVX512VL)
+  "(<MODE_SIZE> == 64 || TARGET_AVX512VL
+    || (TARGET_AVX512F && !TARGET_PREFER_AVX256))
    && ix86_pre_reload_split ()
    && (rtx_equal_p (STRIP_UNARY (operands[1]),
 		    STRIP_UNARY (operands[4]))
@@ -12808,7 +12823,8 @@
 	    (match_operand:V 1 "regmem_or_bitnot_regmem_operand")
 	    (match_operand:V 2 "regmem_or_bitnot_regmem_operand"))
 	  (match_operand:V 3 "regmem_or_bitnot_regmem_operand")))]
-  "(<MODE_SIZE> == 64 || TARGET_AVX512VL)
+  "(<MODE_SIZE> == 64 || TARGET_AVX512VL
+    || (TARGET_AVX512F && !TARGET_PREFER_AVX256))
    && ix86_pre_reload_split ()"
   "#"
   "&& 1"
@@ -17762,14 +17778,14 @@
   DONE;
 })
 
-(define_insn "<sse2_avx2>_packsswb<mask_name>"
-  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>")
-	(vec_concat:VI1_AVX512
-	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>"))
-	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))]
-  "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
+(define_insn "sse2_packsswb<mask_name>"
+  [(set (match_operand:V16QI 0 "register_operand" "=x,Yw")
+	(vec_concat:V16QI
+	  (ss_truncate:V8QI
+	    (match_operand:V8HI 1 "register_operand" "0,Yw"))
+	  (ss_truncate:V8QI
+	    (match_operand:V8HI 2 "vector_operand" "xBm,Ywm"))))]
+  "TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
   "@
    packsswb\t{%2, %0|%0, %2}
    vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -17777,16 +17793,93 @@
    (set_attr "type" "sselog")
    (set_attr "prefix_data16" "1,*")
    (set_attr "prefix" "orig,<mask_prefix>")
-   (set_attr "mode" "<sseinsnmode>")])
+   (set_attr "mode" "TI")])
 
-(define_insn "<sse2_avx2>_packssdw<mask_name>"
-  [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,<v_Yw>")
-	(vec_concat:VI2_AVX2
-	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>"))
-	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))]
-  "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
+(define_insn "avx2_packsswb<mask_name>"
+  [(set (match_operand:V32QI 0 "register_operand" "=Yw")
+	(vec_select:V32QI
+	  (vec_concat:V32QI
+	    (ss_truncate:V16QI
+	      (match_operand:V16HI 1 "register_operand" "Yw"))
+	    (ss_truncate:V16QI
+	      (match_operand:V16HI 2 "vector_operand" "Ywm")))
+	  (parallel [(const_int 0)  (const_int 1)
+		     (const_int 2)  (const_int 3)
+		     (const_int 4)  (const_int 5)
+		     (const_int 6)  (const_int 7)
+		     (const_int 16) (const_int 17)
+		     (const_int 18) (const_int 19)
+		     (const_int 20) (const_int 21)
+		     (const_int 22) (const_int 23)
+		     (const_int 8)  (const_int 9)
+		     (const_int 10) (const_int 11)
+		     (const_int 12) (const_int 13)
+		     (const_int 14) (const_int 15)
+		     (const_int 24) (const_int 25)
+		     (const_int 26) (const_int 27)
+		     (const_int 28) (const_int 29)
+		     (const_int 30) (const_int 31)])))]
+  "TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
+  "vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sselog")
+   (set_attr "prefix" "<mask_prefix>")
+   (set_attr "mode" "OI")])
+
+(define_insn "avx512bw_packsswb<mask_name>"
+  [(set (match_operand:V64QI 0 "register_operand" "=v")
+	(vec_select:V64QI
+	  (vec_concat:V64QI
+	    (ss_truncate:V32QI
+	      (match_operand:V32HI 1 "register_operand" "v"))
+	    (ss_truncate:V32QI
+	      (match_operand:V32HI 2 "vector_operand" "vm")))
+	  (parallel [(const_int 0)  (const_int 1)
+		     (const_int 2)  (const_int 3)
+		     (const_int 4)  (const_int 5)
+		     (const_int 6)  (const_int 7)
+		     (const_int 32) (const_int 33)
+		     (const_int 34) (const_int 35)
+		     (const_int 36) (const_int 37)
+		     (const_int 38) (const_int 39)
+		     (const_int 8)  (const_int 9)
+		     (const_int 10) (const_int 11)
+		     (const_int 12) (const_int 13)
+		     (const_int 14) (const_int 15)
+		     (const_int 40) (const_int 41)
+		     (const_int 42) (const_int 43)
+		     (const_int 44) (const_int 45)
+		     (const_int 46) (const_int 47)
+		     (const_int 16) (const_int 17)
+		     (const_int 18) (const_int 19)
+		     (const_int 20) (const_int 21)
+		     (const_int 22) (const_int 23)
+		     (const_int 48) (const_int 49)
+		     (const_int 50) (const_int 51)
+		     (const_int 52) (const_int 53)
+		     (const_int 54) (const_int 55)
+		     (const_int 24) (const_int 25)
+		     (const_int 26) (const_int 27)
+		     (const_int 28) (const_int 29)
+		     (const_int 30) (const_int 31)
+		     (const_int 56) (const_int 57)
+		     (const_int 58) (const_int 59)
+		     (const_int 60) (const_int 61)
+		     (const_int 62) (const_int 63)])))]
+
+  "TARGET_AVX512BW"
+  "vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sselog")
+   (set_attr "prefix" "<mask_prefix>")
+   (set_attr "mode" "XI")])
+
+(define_insn "sse2_packssdw<mask_name>"
+  [(set (match_operand:V8HI 0 "register_operand" "=x,Yw")
+	(vec_concat:V8HI
+	  (ss_truncate:V4HI
+	    (match_operand:V4SI 1 "register_operand" "0,Yw"))
+	  (ss_truncate:V4HI
+	    (match_operand:V4SI 2 "vector_operand" "xBm,Ywm"))))]
+  "TARGET_SSE2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
   "@
    packssdw\t{%2, %0|%0, %2}
    vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -17794,15 +17887,68 @@
    (set_attr "type" "sselog")
    (set_attr "prefix_data16" "1,*")
    (set_attr "prefix" "orig,<mask_prefix>")
-   (set_attr "mode" "<sseinsnmode>")])
+   (set_attr "mode" "TI")])
 
+(define_insn "avx2_packssdw<mask_name>"
+  [(set (match_operand:V16HI 0 "register_operand" "=Yw")
+	(vec_select:V16HI
+	  (vec_concat:V16HI
+	    (ss_truncate:V8HI
+	      (match_operand:V8SI 1 "register_operand" "Yw"))
+	    (ss_truncate:V8HI
+	      (match_operand:V8SI 2 "vector_operand" "Ywm")))
+	  (parallel [(const_int 0)  (const_int 1)
+		     (const_int 2)  (const_int 3)
+		     (const_int 8)  (const_int 9)
+		     (const_int 10) (const_int 11)
+		     (const_int 4)  (const_int 5)
+		     (const_int 6)  (const_int 7)
+		     (const_int 12) (const_int 13)
+		     (const_int 14) (const_int 15)])))]
+  "TARGET_AVX2 && <mask_avx512vl_condition> && <mask_avx512bw_condition>"
+  "vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sselog")
+   (set_attr "prefix" "<mask_prefix>")
+   (set_attr "mode" "OI")])
+
+(define_insn "avx512bw_packssdw<mask_name>"
+  [(set (match_operand:V32HI 0 "register_operand" "=v")
+	(vec_select:V32HI
+	  (vec_concat:V32HI
+	    (ss_truncate:V16HI
+	      (match_operand:V16SI 1 "register_operand" "v"))
+	    (ss_truncate:V16HI
+	      (match_operand:V16SI 2 "vector_operand" "vm")))
+	  (parallel [(const_int 0)  (const_int 1)
+		     (const_int 2)  (const_int 3)
+		     (const_int 16)  (const_int 17)
+		     (const_int 18) (const_int 19)
+		     (const_int 4)  (const_int 5)
+		     (const_int 6)  (const_int 7)
+		     (const_int 20) (const_int 21)
+		     (const_int 22) (const_int 23)
+		     (const_int 8)  (const_int 9)
+		     (const_int 10)  (const_int 11)
+		     (const_int 24)  (const_int 25)
+		     (const_int 26)  (const_int 27)
+		     (const_int 12)  (const_int 13)
+		     (const_int 14)  (const_int 15)
+		     (const_int 28)  (const_int 29)
+		     (const_int 30)  (const_int 31)])))]
+  "TARGET_AVX512BW"
+  "vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+  [(set_attr "type" "sselog")
+   (set_attr "prefix" "<mask_prefix>")
+   (set_attr "mode" "XI")])
+
+;; This instruction does unsigned saturation of signed source
+;; and is different from generic us_truncate RTX.
 (define_insn "<sse2_avx2>_packuswb<mask_name>"
   [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>")
-	(vec_concat:VI1_AVX512
-	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>"))
-	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m"))))]
+	(unspec:VI1_AVX512
+	  [(match_operand:<sseunpackmode> 1 "register_operand" "0,<v_Yw>")
+	   (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,<v_Yw>m")]
+	  UNSPEC_US_TRUNCATE))]
   "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packuswb\t{%2, %0|%0, %2}
@@ -21889,11 +22035,10 @@
 
 (define_insn "<sse4_1_avx2>_packusdw<mask_name>"
   [(set (match_operand:VI2_AVX2 0 "register_operand" "=Yr,*x,<v_Yw>")
-	(vec_concat:VI2_AVX2
-	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>"))
-	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,<v_Yw>m"))))]
+	(unspec:VI2_AVX2
+	  [(match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>")
+	   (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")]
+	   UNSPEC_US_TRUNCATE))]
   "TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packusdw\t{%2, %0|%0, %2}
@@ -26033,19 +26178,35 @@
 	   (symbol_ref "true")))])
 
 (define_insn "*vec_dupv2di"
-  [(set (match_operand:V2DI 0 "register_operand"     "=x,v,v,x")
+  [(set (match_operand:V2DI 0 "register_operand"     "=x,v,v,v,x")
 	(vec_duplicate:V2DI
-	  (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,0")))]
+	  (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,Yvm,0")))]
   "TARGET_SSE"
   "@
    punpcklqdq\t%0, %0
    vpunpcklqdq\t{%d1, %0|%0, %d1}
+   * return TARGET_AVX512VL ? \"vpbroadcastq\t{%1, %0|%0, %1}\" : \"vpbroadcastq\t{%1, %g0|%g0, %1}\";
    %vmovddup\t{%1, %0|%0, %1}
    movlhps\t%0, %0"
-  [(set_attr "isa" "sse2_noavx,avx,sse3,noavx")
-   (set_attr "type" "sselog1,sselog1,sselog1,ssemov")
-   (set_attr "prefix" "orig,maybe_evex,maybe_vex,orig")
-   (set_attr "mode" "TI,TI,DF,V4SF")])
+  [(set_attr "isa" "sse2_noavx,avx,avx512f,sse3,noavx")
+   (set_attr "type" "sselog1,sselog1,ssemov,sselog1,ssemov")
+   (set_attr "prefix" "orig,maybe_evex,evex,maybe_vex,orig")
+   (set (attr "mode")
+	(cond [(and (eq_attr "alternative" "2")
+		    (match_test "!TARGET_AVX512VL"))
+		 (const_string "XI")
+	       (eq_attr "alternative" "3")
+		 (const_string "DF")
+	       (eq_attr "alternative" "4")
+		 (const_string "V4SF")
+	      ]
+	      (const_string "TI")))
+   (set (attr "enabled")
+	(if_then_else
+	  (eq_attr "alternative" "2")
+	  (symbol_ref "TARGET_AVX512VL
+		       || (TARGET_AVX512F && !TARGET_PREFER_AVX256)")
+	  (const_string "*")))])
 
 (define_insn "avx2_vbroadcasti128_<mode>"
   [(set (match_operand:VI_256 0 "register_operand" "=x,v,v")
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index fb1b072..2804080 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -376,3 +376,32 @@
 }
  [(set_attr "type" "vnshift")
   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; -------------------------------------------------------------------------
+;; ---- Sign-extension for vmv.x.s.
+;; -------------------------------------------------------------------------
+(define_insn "*pred_extract_first_sextdi<mode>"
+  [(set (match_operand:DI 0 "register_operand"		"=r")
+	(sign_extend:DI
+          (unspec:<VEL>
+	    [(vec_select:<VEL>
+	       (match_operand:VI_QHS 1 "register_operand""vr")
+	       (parallel [(const_int 0)]))
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
+  "TARGET_VECTOR && Pmode == DImode"
+  "vmv.x.s\t%0,%1"
+  [(set_attr "type" "vimovvx")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*pred_extract_first_sextsi<mode>"
+  [(set (match_operand:SI 0 "register_operand"		  "=r")
+	(sign_extend:SI
+          (unspec:<VEL>
+	    [(vec_select:<VEL>
+	       (match_operand:VI_QH 1 "register_operand"  "vr")
+	       (parallel [(const_int 0)]))
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
+  "TARGET_VECTOR && Pmode == SImode"
+  "vmv.x.s\t%0,%1"
+  [(set_attr "type" "vimovvx")
+   (set_attr "mode" "<MODE>")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index c23a625..f1641d7 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -513,7 +513,7 @@
 })
 
 ;; -------------------------------------------------------------------------------
-;; - ABS expansion to vmslt and vneg
+;; - [INT] ABS expansion to vmslt and vneg.
 ;; -------------------------------------------------------------------------------
 
 (define_expand "abs<mode>2"
@@ -532,6 +532,40 @@
   DONE;
 })
 
+;; -------------------------------------------------------------------------------
+;; ---- [FP] Unary operations
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vfneg.v/vfabs.v
+;; -------------------------------------------------------------------------------
+(define_expand "<optab><mode>2"
+  [(set (match_operand:VF_AUTO 0 "register_operand")
+    (any_float_unop_nofrm:VF_AUTO
+     (match_operand:VF_AUTO 1 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
+  DONE;
+})
+
+;; -------------------------------------------------------------------------------
+;; - [FP] Square root
+;; -------------------------------------------------------------------------------
+;; Includes:
+;; - vfsqrt.v
+;; -------------------------------------------------------------------------------
+(define_expand "<optab><mode>2"
+  [(set (match_operand:VF_AUTO 0 "register_operand")
+    (any_float_unop:VF_AUTO
+     (match_operand:VF_AUTO 1 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+  riscv_vector::emit_vlmax_fp_insn (icode, riscv_vector::RVV_UNOP, operands);
+  DONE;
+})
+
 ;; =========================================================================
 ;; == Ternary arithmetic
 ;; =========================================================================
@@ -655,3 +689,118 @@
   riscv_vector::expand_select_vl (operands);
   DONE;
 })
+
+;; -------------------------------------------------------------------------
+;; ---- [INT,FP] Insert a vector element.
+;; -------------------------------------------------------------------------
+
+(define_expand "vec_set<mode>"
+  [(match_operand:V	0 "register_operand")
+   (match_operand:<VEL> 1 "register_operand")
+   (match_operand	2 "immediate_operand")]
+  "TARGET_VECTOR"
+{
+  /* If we set the first element, emit an v(f)mv.s.[xf].  */
+  if (operands[2] == const0_rtx)
+    {
+      rtx ops[] = {operands[0], riscv_vector::gen_scalar_move_mask (<VM>mode),
+		   RVV_VUNDEF (<MODE>mode), operands[1]};
+      riscv_vector::emit_scalar_move_insn
+	  (code_for_pred_broadcast (<MODE>mode), ops);
+    }
+  else
+    {
+      /* Move the desired value into a vector register and insert
+	 it at the proper position using vslideup with an
+	 "effective length" of 1 i.e. a VL 1 past the offset.  */
+
+      /* Slide offset = element index.  */
+      int offset = INTVAL (operands[2]);
+
+      /* Only insert one element, i.e. VL = offset + 1.  */
+      rtx length = gen_reg_rtx (Pmode);
+      emit_move_insn (length, GEN_INT (offset + 1));
+
+      /* Move operands[1] into a vector register via vmv.v.x using the same
+	 VL we need for the slide.  */
+      rtx tmp = gen_reg_rtx (<MODE>mode);
+      rtx ops1[] = {tmp, operands[1]};
+      riscv_vector::emit_nonvlmax_integer_move_insn
+	(code_for_pred_broadcast (<MODE>mode), ops1, length);
+
+      /* Slide exactly one element up leaving the tail elements
+	 unchanged.  */
+      rtx ops2[] = {operands[0], operands[0], tmp, operands[2]};
+      riscv_vector::emit_nonvlmax_slide_tu_insn
+	(code_for_pred_slide (UNSPEC_VSLIDEUP, <MODE>mode), ops2, length);
+    }
+  DONE;
+})
+
+;; -------------------------------------------------------------------------
+;; ---- [INT,FP] Extract a vector element.
+;; -------------------------------------------------------------------------
+(define_expand "vec_extract<mode><vel>"
+  [(set (match_operand:<VEL>	  0 "register_operand")
+     (vec_select:<VEL>
+       (match_operand:V		  1 "register_operand")
+       (parallel
+	 [(match_operand	  2 "nonmemory_operand")])))]
+  "TARGET_VECTOR"
+{
+  /* Element extraction can be done by sliding down the requested element
+     to index 0 and then v(f)mv.[xf].s it to a scalar register.  */
+
+  /* When extracting any other than the first element we need to slide
+     it down.  */
+  rtx tmp = NULL_RTX;
+  if (operands[2] != const0_rtx)
+    {
+      /* Emit the slide down to index 0 in a new vector.  */
+      tmp = gen_reg_rtx (<MODE>mode);
+      rtx ops[] = {tmp, RVV_VUNDEF (<MODE>mode), operands[1], operands[2]};
+      riscv_vector::emit_vlmax_slide_insn
+	(code_for_pred_slide (UNSPEC_VSLIDEDOWN, <MODE>mode), ops);
+    }
+
+  /* Emit v(f)mv.[xf].s.  */
+  emit_insn (gen_pred_extract_first (<MODE>mode, operands[0],
+				     tmp ? tmp : operands[1]));
+  DONE;
+})
+
+;; -------------------------------------------------------------------------
+;; ---- [FP] Binary operations
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfadd.vv/vfsub.vv/...
+;; - vfadd.vf/vfsub.vf/...
+;; -------------------------------------------------------------------------
+(define_expand "<optab><mode>3"
+  [(match_operand:VF_AUTO 0 "register_operand")
+   (any_float_binop:VF_AUTO
+    (match_operand:VF_AUTO 1 "register_operand")
+    (match_operand:VF_AUTO 2 "register_operand"))]
+  "TARGET_VECTOR"
+{
+  riscv_vector::emit_vlmax_fp_insn (code_for_pred (<CODE>, <MODE>mode),
+				    riscv_vector::RVV_BINOP, operands);
+  DONE;
+})
+
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vfmin.vv/vfmax.vv
+;; - vfmin.vf/vfmax.vf
+;; -------------------------------------------------------------------------
+(define_expand "<optab><mode>3"
+  [(match_operand:VF_AUTO 0 "register_operand")
+   (any_float_binop_nofrm:VF_AUTO
+    (match_operand:VF_AUTO 1 "register_operand")
+    (match_operand:VF_AUTO 2 "register_operand"))]
+  "TARGET_VECTOR"
+{
+  riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
+				 riscv_vector::RVV_BINOP, operands);
+  DONE;
+})
diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc
index 8fc93ce..a332a6a 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -73,9 +73,6 @@ valid_type (unsigned sew, int lmul_log2, unsigned nf, bool float_p)
   if (nf > 8 || nf < 1)
     return false;
 
-  if (sew == 16 && nf != 1 && float_p) // Disable FP16 tuple in temporarily.
-    return false;
-
   switch (lmul_log2)
     {
     case 1:
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 19a4f9f..1d15270 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -220,6 +220,7 @@ ADJUST_ALIGNMENT (VNx1QI, 1);
 #define RVV_TUPLE_MODES(NBYTES, NSUBPARTS, VB, VH, VS, VD)                     \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, NBYTES, 1);             \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, NBYTES / 2, 1);         \
+  VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, NBYTES / 2, 1);       \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, NBYTES / 4, 1);         \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, NBYTES / 4, 1);       \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, DI, NBYTES / 8, 1);         \
@@ -236,6 +237,9 @@ ADJUST_ALIGNMENT (VNx1QI, 1);
   ADJUST_NUNITS (VNx##NSUBPARTS##x##VD##DI,                                    \
 		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VD##DI##mode,       \
 					VD * NSUBPARTS));                      \
+  ADJUST_NUNITS (VNx##NSUBPARTS##x##VH##HF,                                    \
+		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VH##HF##mode,       \
+					VH * NSUBPARTS));                      \
   ADJUST_NUNITS (VNx##NSUBPARTS##x##VS##SF,                                    \
 		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VS##SF##mode,       \
 					VS * NSUBPARTS));                      \
@@ -247,6 +251,7 @@ ADJUST_ALIGNMENT (VNx1QI, 1);
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HI, 2);                             \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SI, 4);                             \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DI, 8);                             \
+  ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HF, 2);                             \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SF, 4);                             \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DF, 8);
 
@@ -275,10 +280,12 @@ RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8)
 #define RVV_TUPLE_PARTIAL_MODES(NSUBPARTS)                                     \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 1, 1);                  \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 1, 1);                  \
+  VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, 1, 1);                \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, 1, 1);                  \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, 1, 1);                \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 2, 1);                  \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 2, 1);                  \
+  VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, HF, 2, 1);                \
   VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 4, 1);                  \
                                                                                \
   ADJUST_NUNITS (VNx##NSUBPARTS##x1QI,                                         \
@@ -287,6 +294,9 @@ RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8)
   ADJUST_NUNITS (VNx##NSUBPARTS##x1HI,                                         \
 		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HI##mode,            \
 					NSUBPARTS));                           \
+  ADJUST_NUNITS (VNx##NSUBPARTS##x1HF,                                         \
+		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HF##mode,            \
+					NSUBPARTS));                           \
   ADJUST_NUNITS (VNx##NSUBPARTS##x1SI,                                         \
 		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x1SI##mode,            \
 					NSUBPARTS));                           \
@@ -299,15 +309,20 @@ RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8)
   ADJUST_NUNITS (VNx##NSUBPARTS##x2HI,                                         \
 		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HI##mode,            \
 					2 * NSUBPARTS));                       \
+ADJUST_NUNITS (VNx##NSUBPARTS##x2HF,                                         \
+		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HF##mode,            \
+					2 * NSUBPARTS));                       \
   ADJUST_NUNITS (VNx##NSUBPARTS##x4QI,                                         \
 		 riscv_v_adjust_nunits (VNx##NSUBPARTS##x4QI##mode,            \
 					4 * NSUBPARTS));                       \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1QI, 1);                                  \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HI, 2);                                  \
+  ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HF, 2);                                  \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SI, 4);                                  \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SF, 4);                                  \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2QI, 1);                                  \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HI, 2);                                  \
+  ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HF, 2);                                  \
   ADJUST_ALIGNMENT (VNx##NSUBPARTS##x4QI, 1);
 
 RVV_TUPLE_PARTIAL_MODES (2)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index b23a9c1..f052757 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -146,6 +146,7 @@ enum insn_type
   RVV_TERNOP = 5,
   RVV_WIDEN_TERNOP = 4,
   RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md.  */
+  RVV_SLIDE_OP = 4,      /* Dest, VUNDEF, source and offset.  */
 };
 enum vlmul_type
 {
@@ -184,12 +185,17 @@ bool legitimize_move (rtx, rtx);
 void emit_vlmax_vsetvl (machine_mode, rtx);
 void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
+void emit_vlmax_fp_insn (unsigned, int, rtx *, rtx = 0);
 void emit_vlmax_ternary_insn (unsigned, int, rtx *, rtx = 0);
 void emit_nonvlmax_insn (unsigned, int, rtx *, rtx);
+void emit_vlmax_slide_insn (unsigned, rtx *);
+void emit_nonvlmax_slide_tu_insn (unsigned, rtx *, rtx);
 void emit_vlmax_merge_insn (unsigned, int, rtx *);
 void emit_vlmax_cmp_insn (unsigned, rtx *);
 void emit_vlmax_cmp_mu_insn (unsigned, rtx *);
 void emit_vlmax_masked_mu_insn (unsigned, int, rtx *);
+void emit_scalar_move_insn (unsigned, rtx *);
+void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx);
 enum vlmul_type get_vlmul (machine_mode);
 unsigned int get_ratio (machine_mode);
 unsigned int get_nf (machine_mode);
@@ -247,19 +253,21 @@ void expand_vec_init (rtx, rtx);
 void expand_vcond (rtx *);
 void expand_vec_perm (rtx, rtx, rtx, rtx);
 void expand_select_vl (rtx *);
+
 /* Rounding mode bitfield for fixed point VXRM.  */
-enum vxrm_field_enum
+enum fixed_point_rounding_mode
 {
   VXRM_RNU,
   VXRM_RNE,
   VXRM_RDN,
   VXRM_ROD
 };
+
 /* Rounding mode bitfield for floating point FRM.  The value of enum comes
    from the below link.
    https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register
  */
-enum frm_field_enum
+enum floating_point_rounding_mode
 {
   FRM_RNE = 0, /* Aka 0b000.  */
   FRM_RTZ = 1, /* Aka 0b001.  */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6421e93..839a2c6 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -74,8 +74,10 @@ public:
     : m_opno (0), m_op_num (0), m_has_dest_p (false),
       m_fully_unmasked_p (false), m_use_real_merge_p (false),
       m_needs_avl_p (false), m_vlmax_p (false), m_has_tail_policy_p (false),
-      m_has_mask_policy_p (false), m_tail_policy (TAIL_ANY),
-      m_mask_policy (MASK_ANY), m_dest_mode (VOIDmode), m_mask_mode (VOIDmode),
+      m_has_mask_policy_p (false), m_has_fp_rounding_mode_p (false),
+      m_tail_policy (TAIL_ANY), m_mask_policy (MASK_ANY),
+      m_fp_rounding_mode (FRM_DYN),
+      m_dest_mode (VOIDmode), m_mask_mode (VOIDmode),
       m_vl_op (NULL_RTX)
   {}
 
@@ -87,8 +89,10 @@ public:
       m_fully_unmasked_p (use_all_trues_mask_p),
       m_use_real_merge_p (use_real_merge_p), m_needs_avl_p (needs_avl_p),
       m_vlmax_p (vlmax_p), m_has_tail_policy_p (false),
-      m_has_mask_policy_p (false), m_tail_policy (TAIL_ANY),
-      m_mask_policy (MASK_ANY), m_dest_mode (dest_mode),
+      m_has_mask_policy_p (false), m_has_fp_rounding_mode_p (false),
+      m_tail_policy (TAIL_ANY), m_mask_policy (MASK_ANY),
+      m_fp_rounding_mode (FRM_DYN),
+      m_dest_mode (dest_mode),
       m_mask_mode (mask_mode), m_vl_op (NULL_RTX)
   {}
 
@@ -104,6 +108,12 @@ public:
   }
   void set_vl (rtx vl) { m_vl_op = vl; }
 
+  void set_rounding_mode (enum floating_point_rounding_mode mode)
+  {
+    m_has_fp_rounding_mode_p = true;
+    m_fp_rounding_mode = mode;
+  }
+
   void add_output_operand (rtx x, machine_mode mode)
   {
     create_output_operand (&m_ops[m_opno++], x, mode);
@@ -140,6 +150,15 @@ public:
     add_input_operand (gen_int_mode (type, Pmode), Pmode);
   }
 
+  void add_rounding_mode_operand ()
+  {
+    if (m_has_fp_rounding_mode_p)
+      {
+	rtx frm_rtx = gen_int_mode (m_fp_rounding_mode, Pmode);
+	add_input_operand (frm_rtx, Pmode);
+      }
+  }
+
   void emit_insn (enum insn_code icode, rtx *ops)
   {
     int opno = 0;
@@ -200,6 +219,9 @@ public:
       add_policy_operand ();
     if (m_needs_avl_p)
       add_avl_type_operand (m_vlmax_p ? avl_type::VLMAX : avl_type::NONVLMAX);
+
+    add_rounding_mode_operand ();
+
     expand (icode, any_mem_p);
   }
 
@@ -231,8 +253,10 @@ private:
   bool m_vlmax_p;
   bool m_has_tail_policy_p;
   bool m_has_mask_policy_p;
+  bool m_has_fp_rounding_mode_p;
   enum tail_policy m_tail_policy;
   enum mask_policy m_mask_policy;
+  enum floating_point_rounding_mode m_fp_rounding_mode;
   machine_mode m_dest_mode;
   machine_mode m_mask_mode;
   rtx m_vl_op;
@@ -653,6 +677,27 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
   e.emit_insn ((enum insn_code) icode, ops);
 }
 
+void
+emit_vlmax_fp_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
+{
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (op_num,
+					  /* HAS_DEST_P */ true,
+					  /* FULLY_UNMASKED_P */ true,
+					  /* USE_REAL_MERGE_P */ false,
+					  /* HAS_AVL_P */ true,
+					  /* VLMAX_P */ true,
+					  dest_mode,
+					  mask_mode);
+
+  e.set_policy (TAIL_ANY);
+  e.set_policy (MASK_ANY);
+  e.set_rounding_mode (FRM_DYN);
+  e.set_vl (vl);
+  e.emit_insn ((enum insn_code) icode, ops);
+}
+
 /* This function emits a {VLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the
  * ternary operation which always has a real merge operand.  */
 void
@@ -695,6 +740,52 @@ emit_nonvlmax_insn (unsigned icode, int op_num, rtx *ops, rtx avl)
   e.emit_insn ((enum insn_code) icode, ops);
 }
 
+/* This function emits a {NONVLMAX, TAIL_UNDISTURBED, MASK_ANY} vsetvli
+   followed by a vslide insn (with real merge operand).  */
+void
+emit_vlmax_slide_insn (unsigned icode, rtx *ops)
+{
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (RVV_SLIDE_OP,
+					  /* HAS_DEST_P */ true,
+					  /* FULLY_UNMASKED_P */ true,
+					  /* USE_REAL_MERGE_P */ true,
+					  /* HAS_AVL_P */ true,
+					  /* VLMAX_P */ true,
+					  dest_mode,
+					  mask_mode);
+
+  e.set_policy (TAIL_ANY);
+  e.set_policy (MASK_ANY);
+
+  e.emit_insn ((enum insn_code) icode, ops);
+}
+
+/* This function emits a {NONVLMAX, TAIL_UNDISTURBED, MASK_ANY} vsetvli
+   followed by a vslide insn (with real merge operand).  */
+void
+emit_nonvlmax_slide_tu_insn (unsigned icode, rtx *ops, rtx avl)
+{
+  machine_mode dest_mode = GET_MODE (ops[0]);
+  machine_mode mask_mode = get_mask_mode (dest_mode).require ();
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (RVV_SLIDE_OP,
+					  /* HAS_DEST_P */ true,
+					  /* FULLY_UNMASKED_P */ true,
+					  /* USE_REAL_MERGE_P */ true,
+					  /* HAS_AVL_P */ true,
+					  /* VLMAX_P */ false,
+					  dest_mode,
+					  mask_mode);
+
+  e.set_policy (TAIL_UNDISTURBED);
+  e.set_policy (MASK_ANY);
+  e.set_vl (avl);
+
+  e.emit_insn ((enum insn_code) icode, ops);
+}
+
+
 /* This function emits merge instruction.  */
 void
 emit_vlmax_merge_insn (unsigned icode, int op_num, rtx *ops)
@@ -768,7 +859,7 @@ emit_vlmax_masked_mu_insn (unsigned icode, int op_num, rtx *ops)
 
 /* Emit vmv.s.x instruction.  */
 
-static void
+void
 emit_scalar_move_insn (unsigned icode, rtx *ops)
 {
   machine_mode dest_mode = GET_MODE (ops[0]);
@@ -798,7 +889,7 @@ emit_vlmax_integer_move_insn (unsigned icode, rtx *ops, rtx vl)
 
 /* Emit vmv.v.x instruction with nonvlmax.  */
 
-static void
+void
 emit_nonvlmax_integer_move_insn (unsigned icode, rtx *ops, rtx avl)
 {
   emit_nonvlmax_insn (icode, riscv_vector::RVV_UNOP, ops, avl);
@@ -1037,7 +1128,7 @@ expand_const_vector (rtx target, rtx src)
 	builder.quick_push (CONST_VECTOR_ELT (src, i * npatterns + j));
     }
   builder.finalize ();
-  
+
   if (CONST_VECTOR_DUPLICATE_P (src))
     {
       /* Handle the case with repeating sequence that NELTS_PER_PATTERN = 1
@@ -1113,61 +1204,52 @@ expand_const_vector (rtx target, rtx src)
       if (builder.single_step_npatterns_p ())
 	{
 	  /* Describe the case by choosing NPATTERNS = 4 as an example.  */
-	  rtx base, step;
+	  insn_code icode;
+
+	  /* Step 1: Generate vid = { 0, 1, 2, 3, 4, 5, 6, 7, ... }.  */
+	  rtx vid = gen_reg_rtx (builder.mode ());
+	  rtx vid_ops[] = {vid};
+	  icode = code_for_pred_series (builder.mode ());
+	  emit_vlmax_insn (icode, RVV_MISC_OP, vid_ops);
+
 	  if (builder.npatterns_all_equal_p ())
 	    {
 	      /* Generate the variable-length vector following this rule:
 		 { a, a, a + step, a + step, a + step * 2, a + step * 2, ...}
 		   E.g. { 0, 0, 8, 8, 16, 16, ... } */
-	      /* Step 1: Generate base = { 0, 0, 0, 0, 0, 0, 0, ... }.  */
-	      base = expand_vector_broadcast (builder.mode (), builder.elt (0));
+	      /* We want to create a pattern where value[ix] = floor (ix /
+		 NPATTERNS). As NPATTERNS is always a power of two we can
+		 rewrite this as = ix & -NPATTERNS.  */
+	      /* Step 2: VID AND -NPATTERNS:
+		 { 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... }
+	      */
+	      rtx imm
+		= gen_int_mode (-builder.npatterns (), builder.inner_mode ());
+	      rtx and_ops[] = {target, vid, imm};
+	      icode = code_for_pred_scalar (AND, builder.mode ());
+	      emit_vlmax_insn (icode, RVV_BINOP, and_ops);
 	    }
 	  else
 	    {
 	      /* Generate the variable-length vector following this rule:
 		 { a, b, a, b, a + step, b + step, a + step*2, b + step*2, ...}
-		   E.g. { 0, 6, 0, 6, 8, 14, 8, 14, 16, 22, 16, 22, ... } */
-	      /* Step 1: Generate base = { 0, 6, 0, 6, ... }.  */
-	      rvv_builder new_builder (builder.mode (), builder.npatterns (),
-				       1);
-	      for (unsigned int i = 0; i < builder.npatterns (); ++i)
-		new_builder.quick_push (builder.elt (i));
-	      rtx new_vec = new_builder.build ();
-	      base = gen_reg_rtx (builder.mode ());
-	      emit_move_insn (base, new_vec);
+		   E.g. { 3, 2, 1, 0, 7, 6, 5, 4, ... } */
+	      /* Step 2: Generate diff = TARGET - VID:
+		 { 3-0, 2-1, 1-2, 0-3, 7-4, 6-5, 5-6, 4-7, ... }*/
+	      rvv_builder v (builder.mode (), builder.npatterns (), 1);
+	      for (unsigned int i = 0; i < v.npatterns (); ++i)
+		{
+		  /* Calculate the diff between the target sequence and
+		     vid sequence.  */
+		  HOST_WIDE_INT diff = INTVAL (builder.elt (i)) - i;
+		  v.quick_push (gen_int_mode (diff, v.inner_mode ()));
+		}
+	      /* Step 2: Generate result = VID + diff.  */
+	      rtx vec = v.build ();
+	      rtx add_ops[] = {target, vid, vec};
+	      emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), RVV_BINOP,
+			       add_ops);
 	    }
-
-	  /* Step 2: Generate step = gen_int_mode (diff, mode).  */
-	  poly_int64 value1 = rtx_to_poly_int64 (builder.elt (0));
-	  poly_int64 value2
-	    = rtx_to_poly_int64 (builder.elt (builder.npatterns ()));
-	  poly_int64 diff = value2 - value1;
-	  step = gen_int_mode (diff, builder.inner_mode ());
-
-	  /* Step 3: Generate vid = { 0, 1, 2, 3, 4, 5, 6, 7, ... }.  */
-	  rtx vid = gen_reg_rtx (builder.mode ());
-	  rtx op[] = {vid};
-	  emit_vlmax_insn (code_for_pred_series (builder.mode ()), RVV_MISC_OP,
-			   op);
-
-	  /* Step 4: Generate factor = { 0, 0, 0, 0, 1, 1, 1, 1, ... }.  */
-	  rtx factor = gen_reg_rtx (builder.mode ());
-	  rtx shift_ops[]
-	    = {factor, vid,
-	       gen_int_mode (exact_log2 (builder.npatterns ()), Pmode)};
-	  emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, builder.mode ()),
-			   RVV_BINOP, shift_ops);
-
-	  /* Step 5: Generate adjusted step = { 0, 0, 0, 0, diff, diff, ... } */
-	  rtx adjusted_step = gen_reg_rtx (builder.mode ());
-	  rtx mul_ops[] = {adjusted_step, factor, step};
-	  emit_vlmax_insn (code_for_pred_scalar (MULT, builder.mode ()),
-			   RVV_BINOP, mul_ops);
-
-	  /* Step 6: Generate the final result.  */
-	  rtx add_ops[] = {target, base, adjusted_step};
-	  emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), RVV_BINOP,
-			   add_ops);
 	}
       else
 	/* TODO: We will enable more variable-length vector in the future.  */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 87a684d..c6c53dc 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1397,7 +1397,7 @@ public:
   rtx expand (function_expander &e) const override
   {
     return e.use_exact_insn (
-      code_for_pred_reduc (CODE, e.vector_mode (), e.vector_mode ()));
+      code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));
   }
 };
 
@@ -1412,7 +1412,7 @@ public:
   {
     return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
 							     e.vector_mode (),
-							     e.vector_mode ()));
+							     e.ret_mode ()));
   }
 };
 
@@ -1426,7 +1426,7 @@ public:
   rtx expand (function_expander &e) const override
   {
     return e.use_exact_insn (
-      code_for_pred_reduc_plus (UNSPEC, e.vector_mode (), e.vector_mode ()));
+      code_for_pred_reduc_plus (UNSPEC, e.vector_mode (), e.ret_mode ()));
   }
 };
 
@@ -1441,7 +1441,7 @@ public:
   {
     return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
 							     e.vector_mode (),
-							     e.vector_mode ()));
+							     e.ret_mode ()));
   }
 };
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index 4926bd8..1c3cc0e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -1291,6 +1291,31 @@ DEF_RVV_TUPLE_OPS (vint64m2x4_t, RVV_REQUIRE_ELEN_64)
 DEF_RVV_TUPLE_OPS (vuint64m2x4_t, RVV_REQUIRE_ELEN_64)
 DEF_RVV_TUPLE_OPS (vint64m4x2_t, RVV_REQUIRE_ELEN_64)
 DEF_RVV_TUPLE_OPS (vuint64m4x2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x3_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x5_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x6_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x7_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf4x8_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x3_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x5_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x6_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x7_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16mf2x8_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x3_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x5_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x6_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x7_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m1x8_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m2x2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m2x3_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m2x4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_TUPLE_OPS (vfloat16m4x2_t, RVV_REQUIRE_ELEN_FP_16)
 DEF_RVV_TUPLE_OPS (vfloat32mf2x2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_TUPLE_OPS (vfloat32mf2x3_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_TUPLE_OPS (vfloat32mf2x4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 310edea..1e94579 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -494,18 +494,48 @@ DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID,
 /* LMUL = 1/4.  */
 DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID,
 	      _f16mf4, _f16, _e16mf4)
+/* Define tuple types for SEW = 16, LMUL = MF4. */
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x2_t, 20, __rvv_float16mf4x2_t, vfloat16mf4_t, float, 2, _f16mf4x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x3_t, 20, __rvv_float16mf4x3_t, vfloat16mf4_t, float, 3, _f16mf4x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x4_t, 20, __rvv_float16mf4x4_t, vfloat16mf4_t, float, 4, _f16mf4x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x5_t, 20, __rvv_float16mf4x5_t, vfloat16mf4_t, float, 5, _f16mf4x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x6_t, 20, __rvv_float16mf4x6_t, vfloat16mf4_t, float, 6, _f16mf4x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x7_t, 20, __rvv_float16mf4x7_t, vfloat16mf4_t, float, 7, _f16mf4x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf4x8_t, 20, __rvv_float16mf4x8_t, vfloat16mf4_t, float, 8, _f16mf4x8)
 /* LMUL = 1/2.  */
 DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, VNx4HF, VNx2HF, VNx1HF,
 	      _f16mf2, _f16, _e16mf2)
+/* Define tuple types for SEW = 16, LMUL = MF2. */
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x2_t, 20, __rvv_float16mf2x2_t, vfloat16mf2_t, float, 2, _f16mf2x2)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x3_t, 20, __rvv_float16mf2x3_t, vfloat16mf2_t, float, 3, _f16mf2x3)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x4_t, 20, __rvv_float16mf2x4_t, vfloat16mf2_t, float, 4, _f16mf2x4)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x5_t, 20, __rvv_float16mf2x5_t, vfloat16mf2_t, float, 5, _f16mf2x5)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x6_t, 20, __rvv_float16mf2x6_t, vfloat16mf2_t, float, 6, _f16mf2x6)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x7_t, 20, __rvv_float16mf2x7_t, vfloat16mf2_t, float, 7, _f16mf2x7)
+DEF_RVV_TUPLE_TYPE (vfloat16mf2x8_t, 20, __rvv_float16mf2x8_t, vfloat16mf2_t, float, 8, _f16mf2x8)
 /* LMUL = 1.  */
 DEF_RVV_TYPE (vfloat16m1_t, 17, __rvv_float16m1_t, float16, VNx8HF, VNx4HF, VNx2HF,
 	      _f16m1, _f16, _e16m1)
+/* Define tuple types for SEW = 16, LMUL = M1. */
+DEF_RVV_TUPLE_TYPE (vfloat16m1x2_t, 19, __rvv_float16m1x2_t, vfloat16m1_t, float, 2, _f16m1x2)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x3_t, 19, __rvv_float16m1x3_t, vfloat16m1_t, float, 3, _f16m1x3)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x4_t, 19, __rvv_float16m1x4_t, vfloat16m1_t, float, 4, _f16m1x4)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x5_t, 19, __rvv_float16m1x5_t, vfloat16m1_t, float, 5, _f16m1x5)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x6_t, 19, __rvv_float16m1x6_t, vfloat16m1_t, float, 6, _f16m1x6)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x7_t, 19, __rvv_float16m1x7_t, vfloat16m1_t, float, 7, _f16m1x7)
+DEF_RVV_TUPLE_TYPE (vfloat16m1x8_t, 19, __rvv_float16m1x8_t, vfloat16m1_t, float, 8, _f16m1x8)
 /* LMUL = 2.  */
 DEF_RVV_TYPE (vfloat16m2_t, 17, __rvv_float16m2_t, float16, VNx16HF, VNx8HF, VNx4HF,
 	      _f16m2, _f16, _e16m2)
+/* Define tuple types for SEW = 16, LMUL = M2. */
+DEF_RVV_TUPLE_TYPE (vfloat16m2x2_t, 19, __rvv_float16m2x2_t, vfloat16m2_t, float, 2, _f16m2x2)
+DEF_RVV_TUPLE_TYPE (vfloat16m2x3_t, 19, __rvv_float16m2x3_t, vfloat16m2_t, float, 3, _f16m2x3)
+DEF_RVV_TUPLE_TYPE (vfloat16m2x4_t, 19, __rvv_float16m2x4_t, vfloat16m2_t, float, 4, _f16m2x4)
 /* LMUL = 4.  */
 DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, VNx32HF, VNx16HF, VNx8HF,
 	      _f16m4, _f16, _e16m4)
+/* Define tuple types for SEW = 16, LMUL = M4. */
+DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float, 2, _f16m4x2)
 /* LMUL = 8.  */
 DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, VNx64HF, VNx32HF, VNx16HF,
 	      _f16m8, _f16, _e16m8)
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def
index 52f07709..7f14891 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -248,6 +248,38 @@ TUPLE_ENTRY (VNx5x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 5, LMUL_F2, 32, LMUL_F4, 6
 TUPLE_ENTRY (VNx6x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 6, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
 TUPLE_ENTRY (VNx7x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 7, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
 TUPLE_ENTRY (VNx8x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 8, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx2x32HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx32HF, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 4)
+TUPLE_ENTRY (VNx2x16HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx16HF, 2, LMUL_RESERVED, 0, LMUL_4, 4, LMUL_2, 8)
+TUPLE_ENTRY (VNx3x16HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx16HF, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 8)
+TUPLE_ENTRY (VNx4x16HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx16HF, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 8)
+TUPLE_ENTRY (VNx2x8HF, TARGET_VECTOR_ELEN_FP_16, VNx8HF, 2, LMUL_4, 4, LMUL_2, 8, LMUL_1, 16)
+TUPLE_ENTRY (VNx3x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx8HF, 3, LMUL_RESERVED, 0, LMUL_2, 8, LMUL_1, 16)
+TUPLE_ENTRY (VNx4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx8HF, 4, LMUL_RESERVED, 0, LMUL_2, 8, LMUL_1, 16)
+TUPLE_ENTRY (VNx5x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16)
+TUPLE_ENTRY (VNx6x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16)
+TUPLE_ENTRY (VNx7x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16)
+TUPLE_ENTRY (VNx8x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, VNx8HF, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16)
+TUPLE_ENTRY (VNx2x4HF, TARGET_VECTOR_ELEN_FP_16, VNx4HF, 2, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx3x4HF, TARGET_VECTOR_ELEN_FP_16, VNx4HF, 3, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx4x4HF, TARGET_VECTOR_ELEN_FP_16, VNx4HF, 4, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx5x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 5, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx6x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 6, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx7x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 7, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx8x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64, VNx4HF, 8, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32)
+TUPLE_ENTRY (VNx2x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 2, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx3x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 3, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx4x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 4, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx5x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 5, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx6x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 6, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx7x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 7, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx8x2HF, TARGET_VECTOR_ELEN_FP_16, VNx2HF, 8, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+TUPLE_ENTRY (VNx2x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 2, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx3x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 3, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx4x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 4, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx5x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 5, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx6x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 6, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx7x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 7, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+TUPLE_ENTRY (VNx8x1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, VNx1HF, 8, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
 
 /* Tuple modes for EEW = 32.  */
 TUPLE_ENTRY (VNx2x16SI, TARGET_MIN_VLEN >= 128, VNx16SI, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 8)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 7066dea..971c3f9 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -744,7 +744,10 @@ insert_vsetvl (enum emit_type emit_type, rtx_insn *rinsn,
   if (vlmax_avl_p (info.get_avl ()))
     {
       gcc_assert (has_vtype_op (rinsn) || vsetvl_insn_p (rinsn));
-      rtx vl_op = info.get_avl_reg_rtx ();
+      /* For user vsetvli a5, zero, we should use get_vl to get the VL
+	 operand "a5".  */
+      rtx vl_op
+	= vsetvl_insn_p (rinsn) ? get_vl (rinsn) : info.get_avl_reg_rtx ();
       gcc_assert (!vlmax_avl_p (vl_op));
       emit_vsetvl_insn (VSETVL_NORMAL, emit_type, info, vl_op, rinsn);
       return VSETVL_NORMAL;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e5ae4e8..280aa0b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1306,11 +1306,22 @@ riscv_const_insns (rtx x)
 		if (satisfies_constraint_vi (x))
 		  return 1;
 
-		/* A const duplicate vector can always be broadcast from
-		   a general-purpose register.  This means we need as many
-		   insns as it takes to load the constant into the GPR
-		   and one vmv.v.x.  */
-		return 1 + riscv_const_insns (elt);
+		/* Any int/FP constants can always be broadcast from a
+		   scalar register.  Loading of a floating-point
+		   constant incurs a literal-pool access.  Allow this in
+		   order to increase vectorization possibilities.  */
+		int n = riscv_const_insns (elt);
+		if (CONST_DOUBLE_P (elt))
+		    return 1 + 4; /* vfmv.v.f + memory access.  */
+		else
+		  {
+		    /* We need as many insns as it takes to load the constant
+		       into a GPR and one vmv.v.x.  */
+		    if (n != 0)
+		      return 1 + n;
+		    else
+		      return 1 + 4; /*vmv.v.x + memory access.  */
+		  }
 	      }
 	  }
 
@@ -3795,31 +3806,22 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
-/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and
-   intrinsic vector type.  Because we can't get the decl for the params.  */
-
-static bool
-riscv_scalable_vector_type_p (const_tree type)
-{
-  tree size = TYPE_SIZE (type);
-  if (size && TREE_CODE (size) == INTEGER_CST)
-    return false;
-
-  /* For the data type like vint32m1_t, the size code is POLY_INT_CST.  */
-  return true;
-}
+/* Return true if a vector type is included in the type TYPE.  */
 
 static bool
 riscv_arg_has_vector (const_tree type)
 {
-  bool is_vector = false;
+  if (riscv_v_ext_mode_p (TYPE_MODE (type)))
+    return true;
+
+  if (!COMPLETE_TYPE_P (type))
+    return false;
 
   switch (TREE_CODE (type))
     {
     case RECORD_TYPE:
-      if (!COMPLETE_TYPE_P (type))
-	break;
-
+      /* If it is a record, it is further determined whether its fields have
+	 vector type.  */
       for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
 	if (TREE_CODE (f) == FIELD_DECL)
 	  {
@@ -3827,25 +3829,17 @@ riscv_arg_has_vector (const_tree type)
 	    if (!TYPE_P (field_type))
 	      break;
 
-	    /* Ignore it if it's fixed length vector.  */
-	    if (VECTOR_TYPE_P (field_type))
-	      is_vector = riscv_scalable_vector_type_p (field_type);
-	    else
-	      is_vector = riscv_arg_has_vector (field_type);
+	    if (riscv_arg_has_vector (field_type))
+	      return true;
 	  }
-
       break;
-
-    case VECTOR_TYPE:
-      is_vector = riscv_scalable_vector_type_p (type);
-      break;
-
+    case ARRAY_TYPE:
+      return riscv_arg_has_vector (TREE_TYPE (type));
     default:
-      is_vector = false;
       break;
     }
 
-  return is_vector;
+  return false;
 }
 
 /* Pass the type to check whether it's a vector type or contains vector type.
@@ -3856,11 +3850,11 @@ riscv_pass_in_vector_p (const_tree type)
 {
   static int warned = 0;
 
-  if (type && riscv_arg_has_vector (type) && !warned)
+  if (type && riscv_v_ext_mode_p (TYPE_MODE (type)) && !warned)
     {
-      warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in "
-	       "experimental stage and may changes in the upcoming version of "
-	       "GCC.");
+      warning (OPT_Wpsabi,
+	       "ABI for the vector type is currently in experimental stage and "
+	       "may changes in the upcoming version of GCC.");
       warned = 1;
     }
 }
@@ -5102,12 +5096,15 @@ riscv_compute_frame_info (void)
 
   frame = &cfun->machine->frame;
 
-  /* In an interrupt function, if we have a large frame, then we need to
-     save/restore t0.  We check for this before clearing the frame struct.  */
+  /* In an interrupt function, there are two cases in which t0 needs to be used:
+     1, If we have a large frame, then we need to save/restore t0.  We check for
+     this before clearing the frame struct.
+     2, Need to save and restore some CSRs in the frame.  */
   if (cfun->machine->interrupt_handler_p)
     {
       HOST_WIDE_INT step1 = riscv_first_stack_step (frame, frame->total_size);
-      if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1)))
+      if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1))
+	  || (TARGET_HARD_FLOAT || TARGET_ZFINX))
 	interrupt_save_prologue_temp = true;
     }
 
@@ -5154,6 +5151,17 @@ riscv_compute_frame_info (void)
 	}
     }
 
+  /* In an interrupt function, we need extra space for the initial saves of CSRs.  */
+  if (cfun->machine->interrupt_handler_p
+      && ((TARGET_HARD_FLOAT && frame->fmask)
+	  || (TARGET_ZFINX
+	      /* Except for RISCV_PROLOGUE_TEMP_REGNUM.  */
+	      && (frame->mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM)))))
+    /* Save and restore FCSR.  */
+    /* TODO: When P or V extensions support interrupts, some of their CSRs
+       may also need to be saved and restored.  */
+    x_save_size += riscv_stack_align (1 * UNITS_PER_WORD);
+
   /* At the bottom of the frame are any outgoing stack arguments. */
   offset = riscv_stack_align (crtl->outgoing_args_size);
   /* Next are local stack variables. */
@@ -5399,6 +5407,34 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn,
 	    }
 	}
 
+      /* In an interrupt function, save and restore some necessary CSRs in the stack
+	 to avoid changes in CSRs.  */
+      if (regno == RISCV_PROLOGUE_TEMP_REGNUM
+	  && cfun->machine->interrupt_handler_p
+	  && ((TARGET_HARD_FLOAT  && cfun->machine->frame.fmask)
+	      || (TARGET_ZFINX
+		  && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM)))))
+	{
+	  unsigned int fcsr_size = GET_MODE_SIZE (SImode);
+	  if (!epilogue)
+	    {
+	      riscv_save_restore_reg (word_mode, regno, offset, fn);
+	      offset -= fcsr_size;
+	      emit_insn (gen_riscv_frcsr (RISCV_PROLOGUE_TEMP (SImode)));
+	      riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM,
+				      offset, riscv_save_reg);
+	    }
+	  else
+	    {
+	      riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM,
+				      offset - fcsr_size, riscv_restore_reg);
+	      emit_insn (gen_riscv_fscsr (RISCV_PROLOGUE_TEMP (SImode)));
+	      riscv_save_restore_reg (word_mode, regno, offset, fn);
+	      offset -= fcsr_size;
+	    }
+	  continue;
+	}
+
       riscv_save_restore_reg (word_mode, regno, offset, fn);
     }
 
@@ -7209,8 +7245,8 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode)
        precision of the _FloatN type; evaluate all other operations and
        constants to the range and precision of the semantic type;
 
-   If we have the zfh/zhinx extensions then we support _Float16 in native
-   precision, so we should set this to 16.  */
+   If we have the zfh/zhinx/zvfh extensions then we support _Float16
+   in native precision, so we should set this to 16.  */
 static enum flt_eval_method
 riscv_excess_precision (enum excess_precision_type type)
 {
@@ -7218,7 +7254,7 @@ riscv_excess_precision (enum excess_precision_type type)
     {
     case EXCESS_PRECISION_TYPE_FAST:
     case EXCESS_PRECISION_TYPE_STANDARD:
-      return ((TARGET_ZFH || TARGET_ZHINX)
+      return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZVFH)
 		? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
 		: FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
     case EXCESS_PRECISION_TYPE_IMPLICIT:
@@ -7328,6 +7364,11 @@ riscv_regmode_natural_size (machine_mode mode)
      anything smaller than that.  */
   /* ??? For now, only do this for variable-width RVV registers.
      Doing it for constant-sized registers breaks lower-subreg.c.  */
+
+  /* RVV mask modes always consume a single register.  */
+  if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+    return BYTES_PER_RISCV_VECTOR;
+
   if (!riscv_vector_chunks.is_constant () && riscv_v_ext_mode_p (mode))
     {
       if (riscv_v_ext_tuple_mode_p (mode))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d8e935c..245cace 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -78,6 +78,8 @@
   UNSPECV_GPR_RESTORE
 
   ;; Floating-point unspecs.
+  UNSPECV_FRCSR
+  UNSPECV_FSCSR
   UNSPECV_FRFLAGS
   UNSPECV_FSFLAGS
   UNSPECV_FSNVSNAN
@@ -189,6 +191,11 @@
   VNx2x4HI,VNx3x4HI,VNx4x4HI,VNx5x4HI,VNx6x4HI,VNx7x4HI,VNx8x4HI,
   VNx2x2HI,VNx3x2HI,VNx4x2HI,VNx5x2HI,VNx6x2HI,VNx7x2HI,VNx8x2HI,
   VNx2x1HI,VNx3x1HI,VNx4x1HI,VNx5x1HI,VNx6x1HI,VNx7x1HI,VNx8x1HI,
+  VNx2x32HF,VNx2x16HF,VNx3x16HF,VNx4x16HF,
+  VNx2x8HF,VNx3x8HF,VNx4x8HF,VNx5x8HF,VNx6x8HF,VNx7x8HF,VNx8x8HF,
+  VNx2x4HF,VNx3x4HF,VNx4x4HF,VNx5x4HF,VNx6x4HF,VNx7x4HF,VNx8x4HF,
+  VNx2x2HF,VNx3x2HF,VNx4x2HF,VNx5x2HF,VNx6x2HF,VNx7x2HF,VNx8x2HF,
+  VNx2x1HF,VNx3x1HF,VNx4x1HF,VNx5x1HF,VNx6x1HF,VNx7x1HF,VNx8x1HF,
   VNx2x16SI,VNx2x8SI,VNx3x8SI,VNx4x8SI,
   VNx2x4SI,VNx3x4SI,VNx4x4SI,VNx5x4SI,VNx6x4SI,VNx7x4SI,VNx8x4SI,
   VNx2x2SI,VNx3x2SI,VNx4x2SI,VNx5x2SI,VNx6x2SI,VNx7x2SI,VNx8x2SI,
@@ -3056,6 +3063,17 @@
   ""
   "")
 
+(define_insn "riscv_frcsr"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec_volatile [(const_int 0)] UNSPECV_FRCSR))]
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
+  "frcsr\t%0")
+
+(define_insn "riscv_fscsr"
+  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)]
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
+  "fscsr\t%0")
+
 (define_insn "riscv_frflags"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))]
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 8c71c9e..6ca1c54 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -265,36 +265,12 @@
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
 ])
 
-(define_mode_iterator VI_ZVE64 [
-  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI VNx64QI
-  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI VNx32HI
-  VNx1SI VNx2SI VNx4SI VNx8SI VNx16SI
-  VNx1DI VNx2DI VNx4DI VNx8DI
-])
-
-(define_mode_iterator VI_ZVE32 [
-  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI
-  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI
-  VNx1SI VNx2SI VNx4SI VNx8SI
-])
-
 (define_mode_iterator VWI [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >= 128")
   (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
 ])
 
-(define_mode_iterator VWI_ZVE64 [
-  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI VNx64QI
-  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI VNx32HI
-  VNx1SI VNx2SI VNx4SI VNx8SI VNx16SI
-])
-
-(define_mode_iterator VWI_ZVE32 [
-  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI
-  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI
-])
-
 (define_mode_iterator VF [
   (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
   (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
@@ -317,16 +293,32 @@
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
 ])
 
-(define_mode_iterator VF_ZVE64 [
-  VNx1SF VNx2SF VNx4SF VNx8SF VNx16SF
-  VNx1DF VNx2DF VNx4DF VNx8DF
-])
+;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16
+;; changed to TARGET_ZVFH.  TARGET_VECTOR_ELEN_FP_16 is also true for
+;; TARGET_ZVFHMIN while we actually disable all instructions apart from
+;; load, store and convert for it.
+;; Consequently the autovec expanders should also only be enabled with
+;; TARGET_ZVFH.
+(define_mode_iterator VF_AUTO [
+  (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_ZVFH")
+  (VNx4HF "TARGET_ZVFH")
+  (VNx8HF "TARGET_ZVFH")
+  (VNx16HF "TARGET_ZVFH")
+  (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
 
-(define_mode_iterator VF_ZVE32 [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
 ])
 
 (define_mode_iterator VWF [
@@ -340,11 +332,6 @@
   (VNx1SF "TARGET_MIN_VLEN < 128") VNx2SF VNx4SF VNx8SF (VNx16SF "TARGET_MIN_VLEN > 32") (VNx32SF "TARGET_MIN_VLEN >= 128")
 ])
 
-(define_mode_iterator VWF_ZVE64 [
-  VNx1HF VNx2HF VNx4HF VNx8HF VNx16HF VNx32HF
-  VNx1SF VNx2SF VNx4SF VNx8SF VNx16SF
-])
-
 (define_mode_iterator VFULLI [
   (VNx1QI "!TARGET_FULL_V") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_FULL_V")
   (VNx1HI "!TARGET_FULL_V") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_FULL_V")
@@ -352,6 +339,11 @@
   (VNx2DI "TARGET_FULL_V") (VNx4DI "TARGET_FULL_V") (VNx8DI "TARGET_FULL_V") (VNx16DI "TARGET_FULL_V")
 ])
 
+(define_mode_iterator VI_QH [
+  (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >= 128")
+  (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
+])
+
 (define_mode_iterator VI_QHS [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32") (VNx128QI "TARGET_MIN_VLEN >= 128")
   (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
@@ -503,12 +495,12 @@
 ])
 
 (define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
 
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -660,6 +652,38 @@
   (VNx6x1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128")
   (VNx7x1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128")
   (VNx8x1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128")
+  (VNx2x32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx2x16HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx3x16HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx4x16HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx2x8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx3x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx4x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx5x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx6x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx7x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx8x8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx2x4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx3x4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4x4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx5x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx6x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx7x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx8x4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
+  (VNx2x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx3x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx5x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx6x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx7x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8x2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx2x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx3x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx4x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx5x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx6x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx7x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx8x1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
   (VNx2x16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
   (VNx2x8SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
   (VNx3x8SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
@@ -929,6 +953,111 @@
   (VNx2x64QI "TARGET_MIN_VLEN >= 128")
 ])
 
+(define_mode_iterator VQI [
+  (VNx1QI "TARGET_MIN_VLEN < 128")
+  VNx2QI
+  VNx4QI
+  VNx8QI
+  VNx16QI
+  VNx32QI
+  (VNx64QI "TARGET_MIN_VLEN > 32")
+  (VNx128QI "TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VHI [
+  (VNx1HI "TARGET_MIN_VLEN < 128")
+  VNx2HI
+  VNx4HI
+  VNx8HI
+  VNx16HI
+  (VNx32HI "TARGET_MIN_VLEN > 32")
+  (VNx64HI "TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VSI [
+  (VNx1SI "TARGET_MIN_VLEN < 128")
+  VNx2SI
+  VNx4SI
+  VNx8SI
+  (VNx16SI "TARGET_MIN_VLEN > 32")
+  (VNx32SI "TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VDI [
+  (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128")
+  (VNx2DI "TARGET_VECTOR_ELEN_64")
+  (VNx4DI "TARGET_VECTOR_ELEN_64")
+  (VNx8DI "TARGET_VECTOR_ELEN_64")
+  (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VHF [
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VSF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VDF [
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+])
+
+(define_mode_iterator VQI_LMUL1 [
+  (VNx16QI "TARGET_MIN_VLEN >= 128")
+  (VNx8QI "TARGET_MIN_VLEN == 64")
+  (VNx4QI "TARGET_MIN_VLEN == 32")
+])
+
+(define_mode_iterator VHI_LMUL1 [
+  (VNx8HI "TARGET_MIN_VLEN >= 128")
+  (VNx4HI "TARGET_MIN_VLEN == 64")
+  (VNx2HI "TARGET_MIN_VLEN == 32")
+])
+
+(define_mode_iterator VSI_LMUL1 [
+  (VNx4SI "TARGET_MIN_VLEN >= 128")
+  (VNx2SI "TARGET_MIN_VLEN == 64")
+  (VNx1SI "TARGET_MIN_VLEN == 32")
+])
+
+(define_mode_iterator VDI_LMUL1 [
+  (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+  (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN == 64")
+])
+
+(define_mode_iterator VHF_LMUL1 [
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+])
+
+(define_mode_iterator VSF_LMUL1 [
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 64")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN == 32")
+])
+
+(define_mode_iterator VDF_LMUL1 [
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN == 64")
+])
+
 (define_mode_attr VLMULX2 [
   (VNx1QI "VNx2QI") (VNx2QI "VNx4QI") (VNx4QI "VNx8QI") (VNx8QI "VNx16QI") (VNx16QI "VNx32QI") (VNx32QI "VNx64QI") (VNx64QI "VNx128QI")
   (VNx1HI "VNx2HI") (VNx2HI "VNx4HI") (VNx4HI "VNx8HI") (VNx8HI "VNx16HI") (VNx16HI "VNx32HI") (VNx32HI "VNx64HI")
@@ -1025,6 +1154,11 @@
   (VNx2x8DI "VNx8BI") (VNx2x4DI "VNx4BI") (VNx3x4DI "VNx4BI") (VNx4x4DI "VNx4BI")
   (VNx2x2DI "VNx2BI") (VNx3x2DI "VNx2BI") (VNx4x2DI "VNx2BI") (VNx5x2DI "VNx2BI") (VNx6x2DI "VNx2BI") (VNx7x2DI "VNx2BI") (VNx8x2DI "VNx2BI")
   (VNx2x1DI "VNx1BI") (VNx3x1DI "VNx1BI") (VNx4x1DI "VNx1BI") (VNx5x1DI "VNx1BI") (VNx6x1DI "VNx1BI") (VNx7x1DI "VNx1BI") (VNx8x1DI "VNx1BI")
+  (VNx2x32HF "VNx32BI") (VNx2x16HF "VNx16BI") (VNx3x16HF "VNx16BI") (VNx4x16HF "VNx16BI")
+  (VNx2x8HF "VNx8BI") (VNx3x8HF "VNx8BI") (VNx4x8HF "VNx8BI") (VNx5x8HF "VNx8BI") (VNx6x8HF "VNx8BI") (VNx7x8HF "VNx8BI") (VNx8x8HF "VNx8BI")
+  (VNx2x4HF "VNx4BI") (VNx3x4HF "VNx4BI") (VNx4x4HF "VNx4BI") (VNx5x4HF "VNx4BI") (VNx6x4HF "VNx4BI") (VNx7x4HF "VNx4BI") (VNx8x4HF "VNx4BI")
+  (VNx2x2HF "VNx2BI") (VNx3x2HF "VNx2BI") (VNx4x2HF "VNx2BI") (VNx5x2HF "VNx2BI") (VNx6x2HF "VNx2BI") (VNx7x2HF "VNx2BI") (VNx8x2HF "VNx2BI")
+  (VNx2x1HF "VNx1BI") (VNx3x1HF "VNx1BI") (VNx4x1HF "VNx1BI") (VNx5x1HF "VNx1BI") (VNx6x1HF "VNx1BI") (VNx7x1HF "VNx1BI") (VNx8x1HF "VNx1BI")
   (VNx2x16SF "VNx16BI") (VNx2x8SF "VNx8BI") (VNx3x8SF "VNx8BI") (VNx4x8SF "VNx8BI")
   (VNx2x4SF "VNx4BI") (VNx3x4SF "VNx4BI") (VNx4x4SF "VNx4BI") (VNx5x4SF "VNx4BI") (VNx6x4SF "VNx4BI") (VNx7x4SF "VNx4BI") (VNx8x4SF "VNx4BI")
   (VNx2x2SF "VNx2BI") (VNx3x2SF "VNx2BI") (VNx4x2SF "VNx2BI") (VNx5x2SF "VNx2BI") (VNx6x2SF "VNx2BI") (VNx7x2SF "VNx2BI") (VNx8x2SF "VNx2BI")
@@ -1287,152 +1421,6 @@
   (VNx1DF "VNx1SI") (VNx2DF "VNx2SI") (VNx4DF "VNx4SI") (VNx8DF "VNx8SI") (VNx16DF "VNx16SI")
 ])
 
-(define_mode_attr VLMUL1 [
-  (VNx1QI "VNx16QI") (VNx2QI "VNx16QI") (VNx4QI "VNx16QI")
-  (VNx8QI "VNx16QI") (VNx16QI "VNx16QI") (VNx32QI "VNx16QI") (VNx64QI "VNx16QI") (VNx128QI "VNx16QI")
-  (VNx1HI "VNx8HI") (VNx2HI "VNx8HI") (VNx4HI "VNx8HI")
-  (VNx8HI "VNx8HI") (VNx16HI "VNx8HI") (VNx32HI "VNx8HI") (VNx64HI "VNx8HI")
-  (VNx1SI "VNx4SI") (VNx2SI "VNx4SI") (VNx4SI "VNx4SI")
-  (VNx8SI "VNx4SI") (VNx16SI "VNx4SI") (VNx32SI "VNx4SI")
-  (VNx1DI "VNx2DI") (VNx2DI "VNx2DI")
-  (VNx4DI "VNx2DI") (VNx8DI "VNx2DI") (VNx16DI "VNx2DI")
-  (VNx1HF "VNx8HF") (VNx2HF "VNx8HF") (VNx4HF "VNx8HF") (VNx8HF "VNx8HF") (VNx16HF "VNx8HF") (VNx32HF "VNx8HF") (VNx64HF "VNx8HF")
-  (VNx1SF "VNx4SF") (VNx2SF "VNx4SF")
-  (VNx4SF "VNx4SF") (VNx8SF "VNx4SF") (VNx16SF "VNx4SF") (VNx32SF "VNx4SF")
-  (VNx1DF "VNx2DF") (VNx2DF "VNx2DF")
-  (VNx4DF "VNx2DF") (VNx8DF "VNx2DF") (VNx16DF "VNx2DF")
-])
-
-(define_mode_attr VLMUL1_ZVE64 [
-  (VNx1QI "VNx8QI") (VNx2QI "VNx8QI") (VNx4QI "VNx8QI")
-  (VNx8QI "VNx8QI") (VNx16QI "VNx8QI") (VNx32QI "VNx8QI") (VNx64QI "VNx8QI")
-  (VNx1HI "VNx4HI") (VNx2HI "VNx4HI") (VNx4HI "VNx4HI")
-  (VNx8HI "VNx4HI") (VNx16HI "VNx4HI") (VNx32HI "VNx4HI")
-  (VNx1SI "VNx2SI") (VNx2SI "VNx2SI") (VNx4SI "VNx2SI")
-  (VNx8SI "VNx2SI") (VNx16SI "VNx2SI")
-  (VNx1DI "VNx1DI") (VNx2DI "VNx1DI")
-  (VNx4DI "VNx1DI") (VNx8DI "VNx1DI")
-  (VNx1SF "VNx2SF") (VNx2SF "VNx2SF")
-  (VNx4SF "VNx2SF") (VNx8SF "VNx2SF") (VNx16SF "VNx2SF")
-  (VNx1DF "VNx1DF") (VNx2DF "VNx1DF")
-  (VNx4DF "VNx1DF") (VNx8DF "VNx1DF")
-])
-
-(define_mode_attr VLMUL1_ZVE32 [
-  (VNx1QI "VNx4QI") (VNx2QI "VNx4QI") (VNx4QI "VNx4QI")
-  (VNx8QI "VNx4QI") (VNx16QI "VNx4QI") (VNx32QI "VNx4QI")
-  (VNx1HI "VNx2HI") (VNx2HI "VNx2HI") (VNx4HI "VNx2HI")
-  (VNx8HI "VNx2HI") (VNx16HI "VNx2HI")
-  (VNx1SI "VNx1SI") (VNx2SI "VNx1SI") (VNx4SI "VNx1SI")
-  (VNx8SI "VNx1SI")
-  (VNx1SF "VNx2SF") (VNx2SF "VNx2SF")
-  (VNx4SF "VNx2SF") (VNx8SF "VNx2SF")
-])
-
-(define_mode_attr VWLMUL1 [
-  (VNx1QI "VNx8HI") (VNx2QI "VNx8HI") (VNx4QI "VNx8HI")
-  (VNx8QI "VNx8HI") (VNx16QI "VNx8HI") (VNx32QI "VNx8HI") (VNx64QI "VNx8HI") (VNx128QI "VNx8HI")
-  (VNx1HI "VNx4SI") (VNx2HI "VNx4SI") (VNx4HI "VNx4SI")
-  (VNx8HI "VNx4SI") (VNx16HI "VNx4SI") (VNx32HI "VNx4SI") (VNx64HI "VNx4SI")
-  (VNx1SI "VNx2DI") (VNx2SI "VNx2DI") (VNx4SI "VNx2DI")
-  (VNx8SI "VNx2DI") (VNx16SI "VNx2DI") (VNx32SI "VNx2DI")
-  (VNx1HF "VNx4SF") (VNx2HF "VNx4SF") (VNx4HF "VNx4SF") (VNx8HF "VNx4SF") (VNx16HF "VNx4SF") (VNx32HF "VNx4SF") (VNx64HF "VNx4SF")
-  (VNx1SF "VNx2DF") (VNx2SF "VNx2DF")
-  (VNx4SF "VNx2DF") (VNx8SF "VNx2DF") (VNx16SF "VNx2DF") (VNx32SF "VNx2DF")
-])
-
-(define_mode_attr VWLMUL1_ZVE64 [
-  (VNx1QI "VNx4HI") (VNx2QI "VNx4HI") (VNx4QI "VNx4HI")
-  (VNx8QI "VNx4HI") (VNx16QI "VNx4HI") (VNx32QI "VNx4HI") (VNx64QI "VNx4HI")
-  (VNx1HI "VNx2SI") (VNx2HI "VNx2SI") (VNx4HI "VNx2SI")
-  (VNx8HI "VNx2SI") (VNx16HI "VNx2SI") (VNx32HI "VNx2SI")
-  (VNx1SI "VNx1DI") (VNx2SI "VNx1DI") (VNx4SI "VNx1DI")
-  (VNx8SI "VNx1DI") (VNx16SI "VNx1DI")
-  (VNx1HF "VNx2SF") (VNx2HF "VNx2SF") (VNx4HF "VNx2SF") (VNx8HF "VNx2SF") (VNx16HF "VNx2SF") (VNx32HF "VNx2SF")
-  (VNx1SF "VNx1DF") (VNx2SF "VNx1DF")
-  (VNx4SF "VNx1DF") (VNx8SF "VNx1DF") (VNx16SF "VNx1DF")
-])
-
-(define_mode_attr VWLMUL1_ZVE32 [
-  (VNx1QI "VNx2HI") (VNx2QI "VNx2HI") (VNx4QI "VNx2HI")
-  (VNx8QI "VNx2HI") (VNx16QI "VNx2HI") (VNx32QI "VNx2HI")
-  (VNx1HI "VNx1SI") (VNx2HI "VNx1SI") (VNx4HI "VNx1SI")
-  (VNx8HI "VNx1SI") (VNx16HI "VNx1SI")
-])
-
-(define_mode_attr vlmul1 [
-  (VNx1QI "vnx16qi") (VNx2QI "vnx16qi") (VNx4QI "vnx16qi")
-  (VNx8QI "vnx16qi") (VNx16QI "vnx16qi") (VNx32QI "vnx16qi") (VNx64QI "vnx16qi") (VNx128QI "vnx16qi")
-  (VNx1HI "vnx8hi") (VNx2HI "vnx8hi") (VNx4HI "vnx8hi")
-  (VNx8HI "vnx8hi") (VNx16HI "vnx8hi") (VNx32HI "vnx8hi") (VNx64HI "vnx8hi")
-  (VNx1SI "vnx4si") (VNx2SI "vnx4si") (VNx4SI "vnx4si")
-  (VNx8SI "vnx4si") (VNx16SI "vnx4si") (VNx32SI "vnx4si")
-  (VNx1DI "vnx2di") (VNx2DI "vnx2di")
-  (VNx4DI "vnx2di") (VNx8DI "vnx2di") (VNx16DI "vnx2di")
-  (VNx1HF "vnx8hf") (VNx2HF "vnx8hf") (VNx4HF "vnx8hf") (VNx8HF "vnx8hf") (VNx16HF "vnx8hf") (VNx32HF "vnx8hf") (VNx64HF "vnx8hf")
-  (VNx1SF "vnx4sf") (VNx2SF "vnx4sf")
-  (VNx4SF "vnx4sf") (VNx8SF "vnx4sf") (VNx16SF "vnx4sf") (VNx32SF "vnx4sf")
-  (VNx1DF "vnx2df") (VNx2DF "vnx2df")
-  (VNx4DF "vnx2df") (VNx8DF "vnx2df") (VNx16DF "vnx2df")
-])
-
-(define_mode_attr vlmul1_zve64 [
-  (VNx1QI "vnx8qi") (VNx2QI "vnx8qi") (VNx4QI "vnx8qi")
-  (VNx8QI "vnx8qi") (VNx16QI "vnx8qi") (VNx32QI "vnx8qi") (VNx64QI "vnx8qi")
-  (VNx1HI "vnx4hi") (VNx2HI "vnx4hi") (VNx4HI "vnx4hi")
-  (VNx8HI "vnx4hi") (VNx16HI "vnx4hi") (VNx32HI "vnx4hi")
-  (VNx1SI "vnx2si") (VNx2SI "vnx2si") (VNx4SI "vnx2si")
-  (VNx8SI "vnx2si") (VNx16SI "vnx2si")
-  (VNx1DI "vnx1di") (VNx2DI "vnx1di")
-  (VNx4DI "vnx1di") (VNx8DI "vnx1di")
-  (VNx1SF "vnx2sf") (VNx2SF "vnx2sf")
-  (VNx4SF "vnx2sf") (VNx8SF "vnx2sf") (VNx16SF "vnx2sf")
-  (VNx1DF "vnx1df") (VNx2DF "vnx1df")
-  (VNx4DF "vnx1df") (VNx8DF "vnx1df")
-])
-
-(define_mode_attr vlmul1_zve32 [
-  (VNx1QI "vnx4qi") (VNx2QI "vnx4qi") (VNx4QI "vnx4qi")
-  (VNx8QI "vnx4qi") (VNx16QI "vnx4qi") (VNx32QI "vnx4qi")
-  (VNx1HI "vnx2hi") (VNx2HI "vnx2hi") (VNx4HI "vnx2hi")
-  (VNx8HI "vnx2hi") (VNx16HI "vnx2hi")
-  (VNx1SI "vnx1si") (VNx2SI "vnx1si") (VNx4SI "vnx1si")
-  (VNx8SI "vnx1si")
-  (VNx1SF "vnx1sf") (VNx2SF "vnx1sf")
-  (VNx4SF "vnx1sf") (VNx8SF "vnx1sf")
-])
-
-(define_mode_attr vwlmul1 [
-  (VNx1QI "vnx8hi") (VNx2QI "vnx8hi") (VNx4QI "vnx8hi")
-  (VNx8QI "vnx8hi") (VNx16QI "vnx8hi") (VNx32QI "vnx8hi") (VNx64QI "vnx8hi") (VNx128QI "vnx8hi")
-  (VNx1HI "vnx4si") (VNx2HI "vnx4si") (VNx4HI "vnx4si")
-  (VNx8HI "vnx4si") (VNx16HI "vnx4si") (VNx32HI "vnx4si") (VNx64HI "vnx4si")
-  (VNx1SI "vnx2di") (VNx2SI "vnx2di") (VNx4SI "vnx2di")
-  (VNx8SI "vnx2di") (VNx16SI "vnx2di") (VNx32SI "vnx2di")
-  (VNx1HF "vnx4sf") (VNx2HF "vnx4sf") (VNx4HF "vnx4sf") (VNx8HF "vnx4sf") (VNx16HF "vnx4sf") (VNx32HF "vnx4sf") (VNx64HF "vnx4sf")
-  (VNx1SF "vnx2df") (VNx2SF "vnx2df")
-  (VNx4SF "vnx2df") (VNx8SF "vnx2df") (VNx16SF "vnx2df") (VNx32SF "vnx2df")
-])
-
-(define_mode_attr vwlmul1_zve64 [
-  (VNx1QI "vnx4hi") (VNx2QI "vnx4hi") (VNx4QI "vnx4hi")
-  (VNx8QI "vnx4hi") (VNx16QI "vnx4hi") (VNx32QI "vnx4hi") (VNx64QI "vnx4hi")
-  (VNx1HI "vnx2si") (VNx2HI "vnx2si") (VNx4HI "vnx2si")
-  (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2si")
-  (VNx1SI "vnx1di") (VNx2SI "vnx1di") (VNx4SI "vnx1di")
-  (VNx8SI "vnx1di") (VNx16SI "vnx1di")
-  (VNx1HF "vnx2sf") (VNx2HF "vnx2sf") (VNx4HF "vnx2sf") (VNx8HF "vnx2sf") (VNx16HF "vnx2sf") (VNx32HF "vnx2sf")
-  (VNx1SF "vnx1df") (VNx2SF "vnx1df")
-  (VNx4SF "vnx1df") (VNx8SF "vnx1df") (VNx16SF "vnx1df")
-])
-
-(define_mode_attr vwlmul1_zve32 [
-  (VNx1QI "vnx2hi") (VNx2QI "vnx2hi") (VNx4QI "vnx2hi")
-  (VNx8QI "vnx2hi") (VNx16QI "vnx2hi") (VNx32QI "vnx2hi")
-  (VNx1HI "vnx1si") (VNx2HI "vnx1si") (VNx4HI "vnx1si")
-  (VNx8HI "vnx1si") (VNx16HI "vnx1si")
-])
-
 (define_mode_attr VDEMOTE [
   (VNx1DI "VNx2SI") (VNx2DI "VNx4SI")
   (VNx4DI "VNx8SI") (VNx8DI "VNx16SI") (VNx16DI "VNx32SI")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847b..884e7435 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7244,320 +7244,592 @@
 ;; -------------------------------------------------------------------------------
 
 ;; For reduction operations, we should have seperate patterns for
-;; TARGET_MIN_VLEN == 32 and TARGET_MIN_VLEN > 32.
+;; different types. For each type, we will cover MIN_VLEN == 32, MIN_VLEN == 64
+;; and the MIN_VLEN >= 128 from the well defined iterators.
 ;; Since reduction need LMUL = 1 scalar operand as the input operand
 ;; and they are different.
 ;; For example, The LMUL = 1 corresponding mode of VNx16QImode is VNx4QImode
 ;; for -march=rv*zve32* wheras VNx8QImode for -march=rv*zve64*
-(define_insn "@pred_reduc_<reduc><mode><vlmul1>"
-  [(set (match_operand:<VLMUL1> 0 "register_operand"            "=vr,   vr")
-	(unspec:<VLMUL1>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"     "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"        "   rK,   rK")
-	      (match_operand 6 "const_int_operand"            "    i,    i")
-	      (match_operand 7 "const_int_operand"            "    i,    i")
+
+;; Integer Reduction for QI
+(define_insn "@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VQI_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VQI_LMUL1
+	[
+	  (unspec:<VQI:VM>
+	    [
+	      (match_operand:<VQI:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
-	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	   (any_reduc:VI
-	     (vec_duplicate:VI
-	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1> 4 "register_operand" "   vr,   vr")
-	         (parallel [(const_int 0)])))
-	     (match_operand:VI 3 "register_operand"           "   vr,   vr"))
-	   (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VQI
+	    (vec_duplicate:VQI
+	      (vec_select:<VEL>
+		(match_operand:VQI_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VQI           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VQI_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vred<reduc>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vired")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vired")
+    (set_attr "mode" "<VQI:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
-  [(set (match_operand:<VLMUL1_ZVE64> 0 "register_operand"            "=vr,   vr")
-	(unspec:<VLMUL1_ZVE64>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"     "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"        "   rK,   rK")
-	      (match_operand 6 "const_int_operand"            "    i,    i")
-	      (match_operand 7 "const_int_operand"            "    i,    i")
+;; Integer Reduction for HI
+(define_insn "@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VHI_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VHI_LMUL1
+	[
+	  (unspec:<VHI:VM>
+	    [
+	      (match_operand:<VHI:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
-	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	   (any_reduc:VI_ZVE64
-	     (vec_duplicate:VI_ZVE64
-	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1_ZVE64> 4 "register_operand" "   vr,   vr")
-	         (parallel [(const_int 0)])))
-	     (match_operand:VI_ZVE64 3 "register_operand"           "   vr,   vr"))
-	   (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VHI
+	    (vec_duplicate:VHI
+	      (vec_select:<VEL>
+		(match_operand:VHI_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VHI           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VHI_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vred<reduc>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vired")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vired")
+    (set_attr "mode" "<VHI:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
-  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"          "=vd, vd, vr, vr")
-	(unspec:<VLMUL1_ZVE32>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"           " vm, vm,Wc1,Wc1")
-	      (match_operand 5 "vector_length_operand"              " rK, rK, rK, rK")
-	      (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
-	      (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
+;; Integer Reduction for SI
+(define_insn "@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VSI_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VSI_LMUL1
+	[
+	  (unspec:<VSI:VM>
+	    [
+	      (match_operand:<VSI:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
-	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	   (any_reduc:VI_ZVE32
-	     (vec_duplicate:VI_ZVE32
-	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
-	         (parallel [(const_int 0)])))
-	     (match_operand:VI_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
-	   (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VSI
+	    (vec_duplicate:VSI
+	      (vec_select:<VEL>
+		(match_operand:VSI_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VSI           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VSI_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vred<reduc>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vired")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vired")
+    (set_attr "mode" "<VSI:MODE>")
+  ]
+)
 
-(define_insn "@pred_widen_reduc_plus<v_su><mode><vwlmul1>"
-  [(set (match_operand:<VWLMUL1> 0 "register_operand"           "=&vr,  &vr")
-	(unspec:<VWLMUL1>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"         "   rK,   rK")
-	      (match_operand 6 "const_int_operand"             "    i,    i")
-	      (match_operand 7 "const_int_operand"             "    i,    i")
+;; Integer Reduction for DI
+(define_insn "@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VDI_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VDI_LMUL1
+	[
+	  (unspec:<VDI:VM>
+	    [
+	      (match_operand:<VDI:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
-	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	   (match_operand:VWI 3 "register_operand"             "   vr,   vr")
-	   (match_operand:<VWLMUL1> 4 "register_operand"       "   vr,   vr")
-	   (match_operand:<VWLMUL1> 2 "vector_merge_operand"   "   vu,    0")] WREDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
-  "vwredsum<v_su>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "viwred")
-   (set_attr "mode" "<MODE>")])
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VDI
+	    (vec_duplicate:VDI
+	      (vec_select:<VEL>
+		(match_operand:VDI_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VDI           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VDI_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
+  "vred<reduc>.vs\t%0,%3,%4%p1"
+  [
+    (set_attr "type" "vired")
+    (set_attr "mode" "<VDI:MODE>")
+  ]
+)
 
-(define_insn "@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>"
-  [(set (match_operand:<VWLMUL1_ZVE64> 0 "register_operand"           "=&vr,  &vr")
-	(unspec:<VWLMUL1_ZVE64>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"            "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"               "   rK,   rK")
-	      (match_operand 6 "const_int_operand"                   "    i,    i")
-	      (match_operand 7 "const_int_operand"                   "    i,    i")
+;; Integer Reduction Widen for QI, HI = QI op HI
+(define_insn "@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VHI_LMUL1        0 "register_operand"      "=&vr,&vr")
+      (unspec:VHI_LMUL1
+	[
+	  (unspec:<VQI:VM>
+	    [
+	      (match_operand:<VQI:VM> 1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand          5 "vector_length_operand" "   rK,   rK")
+	      (match_operand          6 "const_int_operand"     "    i,    i")
+	      (match_operand          7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
-	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	   (match_operand:VWI_ZVE64 3 "register_operand"             "   vr,   vr")
-	   (match_operand:<VWLMUL1_ZVE64> 4 "register_operand"       "   vr,   vr")
-	   (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] WREDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (match_operand:VQI          3 "register_operand"      "   vr,   vr")
+	  (match_operand:VHI_LMUL1    4 "register_operand"      "   vr,   vr")
+	  (match_operand:VHI_LMUL1    2 "vector_merge_operand"  "   vu,    0")
+	] WREDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vwredsum<v_su>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "viwred")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "viwred")
+    (set_attr "mode" "<VQI:MODE>")
+  ]
+)
 
+;; Integer Reduction Widen for HI, SI = HI op SI
+(define_insn "@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VSI_LMUL1        0 "register_operand"      "=&vr,&vr")
+      (unspec:VSI_LMUL1
+	[
+	  (unspec:<VHI:VM>
+	    [
+	      (match_operand:<VHI:VM> 1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand          5 "vector_length_operand" "   rK,   rK")
+	      (match_operand          6 "const_int_operand"     "    i,    i")
+	      (match_operand          7 "const_int_operand"     "    i,    i")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (match_operand:VHI          3 "register_operand"      "   vr,   vr")
+	  (match_operand:VSI_LMUL1    4 "register_operand"      "   vr,   vr")
+	  (match_operand:VSI_LMUL1    2 "vector_merge_operand"  "   vu,    0")
+	] WREDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
+  "vwredsum<v_su>.vs\t%0,%3,%4%p1"
+  [
+    (set_attr "type" "viwred")
+    (set_attr "mode" "<VHI:MODE>")
+  ]
+)
 
-(define_insn "@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>"
-  [(set (match_operand:<VWLMUL1_ZVE32> 0 "register_operand"           "=&vr,  &vr")
-	(unspec:<VWLMUL1_ZVE32>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"            "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"               "   rK,   rK")
-	      (match_operand 6 "const_int_operand"                   "    i,    i")
-	      (match_operand 7 "const_int_operand"                   "    i,    i")
+;; Integer Reduction Widen for SI, DI = SI op DI
+(define_insn "@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VDI_LMUL1        0 "register_operand"      "=&vr,&vr")
+      (unspec:VDI_LMUL1
+	[
+	  (unspec:<VSI:VM>
+	    [
+	      (match_operand:<VSI:VM> 1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand          5 "vector_length_operand" "   rK,   rK")
+	      (match_operand          6 "const_int_operand"     "    i,    i")
+	      (match_operand          7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
-	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	   (match_operand:VWI_ZVE32 3 "register_operand"             "   vr,   vr")
-	   (match_operand:<VWLMUL1_ZVE32> 4 "register_operand"       "   vr,   vr")
-	   (match_operand:<VWLMUL1_ZVE32> 2 "vector_merge_operand"   "   vu,    0")] WREDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+	      (reg:SI VTYPE_REGNUM)
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (match_operand:VSI          3 "register_operand"      "   vr,   vr")
+	  (match_operand:VDI_LMUL1    4 "register_operand"      "   vr,   vr")
+	  (match_operand:VDI_LMUL1    2 "vector_merge_operand"  "   vu,    0")
+	] WREDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vwredsum<v_su>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "viwred")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "viwred")
+    (set_attr "mode" "<VSI:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_<reduc><mode><vlmul1>"
-  [(set (match_operand:<VLMUL1> 0 "register_operand"             "=vr,   vr")
-	(unspec:<VLMUL1>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"         "   rK,   rK")
-	      (match_operand 6 "const_int_operand"             "    i,    i")
-	      (match_operand 7 "const_int_operand"             "    i,    i")
-	      (match_operand 8 "const_int_operand"             "    i,    i")
+;; Float Reduction for HF
+(define_insn "@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VHF_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VHF_LMUL1
+	[
+	  (unspec:<VHF:VM>
+	    [
+	      (match_operand:<VHF:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)
-	      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	   (any_freduc:VF
-	     (vec_duplicate:VF
-	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1> 4 "register_operand" "   vr,   vr")
-	         (parallel [(const_int 0)])))
-	     (match_operand:VF 3 "register_operand"           "   vr,   vr"))
-	   (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VHF
+	    (vec_duplicate:VHF
+	      (vec_select:<VEL>
+		(match_operand:VHF_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VHF           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VHF_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfred<reduc>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfredu")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfredu")
+    (set_attr "mode" "<VHF:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve64>"
-  [(set (match_operand:<VLMUL1_ZVE64> 0 "register_operand"            "=vr,   vr")
-	(unspec:<VLMUL1_ZVE64>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
-	      (match_operand 5 "vector_length_operand"              "   rK,   rK")
-	      (match_operand 6 "const_int_operand"                  "    i,    i")
-	      (match_operand 7 "const_int_operand"                  "    i,    i")
-	      (match_operand 8 "const_int_operand"                  "    i,    i")
+;; Float Reduction for SF
+(define_insn "@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VSF_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VSF_LMUL1
+	[
+	  (unspec:<VSF:VM>
+	    [
+	      (match_operand:<VSF:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)
-	      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	   (any_freduc:VF_ZVE64
-	     (vec_duplicate:VF_ZVE64
-	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1_ZVE64> 4 "register_operand" "   vr,   vr")
-	         (parallel [(const_int 0)])))
-	     (match_operand:VF_ZVE64 3 "register_operand"           "   vr,   vr"))
-	   (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VSF
+	    (vec_duplicate:VSF
+	      (vec_select:<VEL>
+		(match_operand:VSF_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VSF           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VSF_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfred<reduc>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfredu")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfredu")
+    (set_attr "mode" "<VSF:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
-  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"          "=vd, vd, vr, vr")
-	(unspec:<VLMUL1_ZVE32>
-	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"           " vm, vm,Wc1,Wc1")
-	      (match_operand 5 "vector_length_operand"              " rK, rK, rK, rK")
-	      (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
-	      (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
-	      (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i")
+;; Float Reduction for DF
+(define_insn "@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VDF_LMUL1           0 "register_operand"      "=vr,     vr")
+      (unspec:VDF_LMUL1
+	[
+	  (unspec:<VDF:VM>
+	    [
+	      (match_operand:<VDF:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+	      (match_operand             5 "vector_length_operand" "   rK,   rK")
+	      (match_operand             6 "const_int_operand"     "    i,    i")
+	      (match_operand             7 "const_int_operand"     "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)
-	      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	   (any_freduc:VF_ZVE32
-	     (vec_duplicate:VF_ZVE32
-	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
-	         (parallel [(const_int 0)])))
-	     (match_operand:VF_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
-	   (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+	    ] UNSPEC_VPREDICATE
+	  )
+	  (any_reduc:VDF
+	    (vec_duplicate:VDF
+	      (vec_select:<VEL>
+		(match_operand:VDF_LMUL1 4 "register_operand"      "   vr,   vr")
+		(parallel [(const_int 0)])
+	      )
+	    )
+	    (match_operand:VDF           3 "register_operand"      "   vr,   vr")
+	  )
+	  (match_operand:VDF_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	] UNSPEC_REDUC
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfred<reduc>.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfredu")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfredu")
+    (set_attr "mode" "<VDF:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_plus<order><mode><vlmul1>"
-  [(set (match_operand:<VLMUL1> 0 "register_operand"               "=vr,   vr")
-	(unspec:<VLMUL1>
-	  [(unspec:<VLMUL1>
-	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-	        (match_operand 5 "vector_length_operand"         "   rK,   rK")
-	        (match_operand 6 "const_int_operand"             "    i,    i")
-	        (match_operand 7 "const_int_operand"             "    i,    i")
-	        (match_operand 8 "const_int_operand"             "    i,    i")
-	        (reg:SI VL_REGNUM)
-	        (reg:SI VTYPE_REGNUM)
-	        (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	     (plus:VF
-	       (vec_duplicate:VF
-	         (vec_select:<VEL>
-	           (match_operand:<VLMUL1> 4 "register_operand" "   vr,   vr")
-	           (parallel [(const_int 0)])))
-	       (match_operand:VF 3 "register_operand"           "   vr,   vr"))
-	     (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC)] ORDER))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+;; Float Ordered Reduction Sum for HF
+(define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VHF_LMUL1               0 "register_operand"      "=vr,vr")
+      (unspec:VHF_LMUL1
+	[
+	  (unspec:VHF_LMUL1
+	    [
+	      (unspec:<VHF:VM>
+		[
+		  (match_operand:<VHF:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+		  (match_operand             5 "vector_length_operand" "   rK,   rK")
+		  (match_operand             6 "const_int_operand"     "    i,    i")
+		  (match_operand             7 "const_int_operand"     "    i,    i")
+		  (match_operand             8 "const_int_operand"     "    i,    i")
+		  (reg:SI VL_REGNUM)
+		  (reg:SI VTYPE_REGNUM)
+		  (reg:SI FRM_REGNUM)
+		] UNSPEC_VPREDICATE
+	      )
+	      (plus:VHF
+		(vec_duplicate:VHF
+		  (vec_select:<VEL>
+		    (match_operand:VHF_LMUL1 4 "register_operand"      "   vr,   vr")
+		    (parallel [(const_int 0)])
+		  )
+		)
+		(match_operand:VHF           3 "register_operand"      "   vr,   vr")
+	      )
+	      (match_operand:VHF_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	    ] UNSPEC_REDUC
+	  )
+	] ORDER
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfred<order>sum.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfred<order>")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfred<order>")
+    (set_attr "mode" "<VHF:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_plus<order><mode><vlmul1_zve64>"
-  [(set (match_operand:<VLMUL1_ZVE64> 0 "register_operand"              "=vr,   vr")
-	(unspec:<VLMUL1_ZVE64>
-	  [(unspec:<VLMUL1_ZVE64>
-	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
-	        (match_operand 5 "vector_length_operand"              "   rK,   rK")
-	        (match_operand 6 "const_int_operand"                  "    i,    i")
-	        (match_operand 7 "const_int_operand"                  "    i,    i")
-	        (match_operand 8 "const_int_operand"                  "    i,    i")
-	        (reg:SI VL_REGNUM)
-	        (reg:SI VTYPE_REGNUM)
-	        (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	     (plus:VF_ZVE64
-	       (vec_duplicate:VF_ZVE64
-	         (vec_select:<VEL>
-	           (match_operand:<VLMUL1_ZVE64> 4 "register_operand" "   vr,   vr")
-	           (parallel [(const_int 0)])))
-	       (match_operand:VF_ZVE64 3 "register_operand"           "   vr,   vr"))
-	     (match_operand:<VLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC)] ORDER))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+;; Float Ordered Reduction Sum for SF
+(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VSF_LMUL1               0 "register_operand"      "=vr,vr")
+      (unspec:VSF_LMUL1
+	[
+	  (unspec:VSF_LMUL1
+	    [
+	      (unspec:<VSF:VM>
+		[
+		  (match_operand:<VSF:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+		  (match_operand             5 "vector_length_operand" "   rK,   rK")
+		  (match_operand             6 "const_int_operand"     "    i,    i")
+		  (match_operand             7 "const_int_operand"     "    i,    i")
+		  (match_operand             8 "const_int_operand"     "    i,    i")
+		  (reg:SI VL_REGNUM)
+		  (reg:SI VTYPE_REGNUM)
+		  (reg:SI FRM_REGNUM)
+		] UNSPEC_VPREDICATE
+	      )
+	      (plus:VSF
+		(vec_duplicate:VSF
+		  (vec_select:<VEL>
+		    (match_operand:VSF_LMUL1 4 "register_operand"      "   vr,   vr")
+		    (parallel [(const_int 0)])
+		  )
+		)
+		(match_operand:VSF           3 "register_operand"      "   vr,   vr")
+	      )
+	      (match_operand:VSF_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	    ] UNSPEC_REDUC
+	  )
+	] ORDER
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfred<order>sum.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfred<order>")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfred<order>")
+    (set_attr "mode" "<VSF:MODE>")
+  ]
+)
 
-(define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
-  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"            "=vd, vd, vr, vr")
-	(unspec:<VLMUL1_ZVE32>
-	  [(unspec:<VLMUL1_ZVE32>
-	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"           " vm, vm,Wc1,Wc1")
-	        (match_operand 5 "vector_length_operand"              " rK, rK, rK, rK")
-	        (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
-	        (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
-	        (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i")
-	        (reg:SI VL_REGNUM)
-	        (reg:SI VTYPE_REGNUM)
-	        (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	     (plus:VF_ZVE32
-	       (vec_duplicate:VF_ZVE32
-	         (vec_select:<VEL>
-	           (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
-	           (parallel [(const_int 0)])))
-	       (match_operand:VF_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
-	     (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC)] ORDER))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
+;; Float Ordered Reduction Sum for DF
+(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VDF_LMUL1               0 "register_operand"      "=vr,vr")
+      (unspec:VDF_LMUL1
+	[
+	  (unspec:VDF_LMUL1
+	    [
+	      (unspec:<VDF:VM>
+		[
+		  (match_operand:<VDF:VM>    1 "vector_mask_operand"   "vmWc1,vmWc1")
+		  (match_operand             5 "vector_length_operand" "   rK,   rK")
+		  (match_operand             6 "const_int_operand"     "    i,    i")
+		  (match_operand             7 "const_int_operand"     "    i,    i")
+		  (match_operand             8 "const_int_operand"     "    i,    i")
+		  (reg:SI VL_REGNUM)
+		  (reg:SI VTYPE_REGNUM)
+		  (reg:SI FRM_REGNUM)
+		] UNSPEC_VPREDICATE
+	      )
+	      (plus:VDF
+		(vec_duplicate:VDF
+		  (vec_select:<VEL>
+		    (match_operand:VDF_LMUL1 4 "register_operand"      "   vr,   vr")
+		    (parallel [(const_int 0)])
+		  )
+		)
+		(match_operand:VDF           3 "register_operand"      "   vr,   vr")
+	      )
+	      (match_operand:VDF_LMUL1       2 "vector_merge_operand"  "   vu,    0")
+	    ] UNSPEC_REDUC
+	  )
+	] ORDER
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfred<order>sum.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfred<order>")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfred<order>")
+    (set_attr "mode" "<VDF:MODE>")
+  ]
+)
 
-(define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1>"
-  [(set (match_operand:<VWLMUL1> 0 "register_operand"             "=&vr,  &vr")
-	(unspec:<VWLMUL1>
-	  [(unspec:<VWLMUL1>
-	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-	        (match_operand 5 "vector_length_operand"         "   rK,   rK")
-	        (match_operand 6 "const_int_operand"             "    i,    i")
-	        (match_operand 7 "const_int_operand"             "    i,    i")
-	        (match_operand 8 "const_int_operand"             "    i,    i")
-	        (reg:SI VL_REGNUM)
-	        (reg:SI VTYPE_REGNUM)
-	        (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	     (match_operand:VWF 3 "register_operand"             "   vr,   vr")
-	     (match_operand:<VWLMUL1> 4 "register_operand"       "   vr,   vr")
-	     (match_operand:<VWLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_WREDUC_SUM)] ORDER))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN >= 128"
+;; Float Widen Reduction for HF, aka SF = HF op SF
+(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VSF_LMUL1            0 "register_operand"      "=&vr, &vr")
+      (unspec:VSF_LMUL1
+	[
+	  (unspec:VSF_LMUL1
+	    [
+	      (unspec:<VHF:VM>
+		[
+		  (match_operand:<VHF:VM> 1 "vector_merge_operand"  "vmWc1,vmWc1")
+		  (match_operand          5 "vector_length_operand" "   rK,   rK")
+		  (match_operand          6 "const_int_operand"     "    i,    i")
+		  (match_operand          7 "const_int_operand"     "    i,    i")
+		  (match_operand          8 "const_int_operand"     "    i,    i")
+		  (reg:SI VL_REGNUM)
+		  (reg:SI VTYPE_REGNUM)
+		  (reg:SI FRM_REGNUM)
+		] UNSPEC_VPREDICATE
+	      )
+	      (match_operand:VHF          3 "register_operand"      "   vr,   vr")
+	      (match_operand:VSF_LMUL1    4 "register_operand"      "   vr,   vr")
+	      (match_operand:VSF_LMUL1    2 "vector_merge_operand"  "   vu,    0")
+	    ] UNSPEC_WREDUC_SUM
+	  )
+	] ORDER
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfwred<order>sum.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfwred<order>")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfwred<order>")
+    (set_attr "mode" "<VHF:MODE>")
+  ]
+)
 
-(define_insn "@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>"
-  [(set (match_operand:<VWLMUL1_ZVE64> 0 "register_operand"             "=&vr,  &vr")
-	(unspec:<VWLMUL1_ZVE64>
-	  [(unspec:<VWLMUL1_ZVE64>
-	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
-	        (match_operand 5 "vector_length_operand"         "   rK,   rK")
-	        (match_operand 6 "const_int_operand"             "    i,    i")
-	        (match_operand 7 "const_int_operand"             "    i,    i")
-	        (match_operand 8 "const_int_operand"             "    i,    i")
-	        (reg:SI VL_REGNUM)
-	        (reg:SI VTYPE_REGNUM)
-	        (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
-	     (match_operand:VWF_ZVE64 3 "register_operand"             "   vr,   vr")
-	     (match_operand:<VWLMUL1_ZVE64> 4 "register_operand"       "   vr,   vr")
-	     (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_WREDUC_SUM)] ORDER))]
-  "TARGET_VECTOR && TARGET_MIN_VLEN == 64"
+;; Float Widen Reduction for SF, aka DF = SF * DF
+(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
+  [
+    (set
+      (match_operand:VDF_LMUL1            0 "register_operand"      "=&vr, &vr")
+      (unspec:VDF_LMUL1
+	[
+	  (unspec:VDF_LMUL1
+	    [
+	      (unspec:<VSF:VM>
+		[
+		  (match_operand:<VSF:VM> 1 "vector_merge_operand"  "vmWc1,vmWc1")
+		  (match_operand          5 "vector_length_operand" "   rK,   rK")
+		  (match_operand          6 "const_int_operand"     "    i,    i")
+		  (match_operand          7 "const_int_operand"     "    i,    i")
+		  (match_operand          8 "const_int_operand"     "    i,    i")
+		  (reg:SI VL_REGNUM)
+		  (reg:SI VTYPE_REGNUM)
+		  (reg:SI FRM_REGNUM)
+		] UNSPEC_VPREDICATE
+	      )
+	      (match_operand:VSF          3 "register_operand"      "   vr,   vr")
+	      (match_operand:VDF_LMUL1    4 "register_operand"      "   vr,   vr")
+	      (match_operand:VDF_LMUL1    2 "vector_merge_operand"  "   vu,    0")
+	    ] UNSPEC_WREDUC_SUM
+	  )
+	] ORDER
+      )
+    )
+  ]
+  "TARGET_VECTOR"
   "vfwred<order>sum.vs\t%0,%3,%4%p1"
-  [(set_attr "type" "vfwred<order>")
-   (set_attr "mode" "<MODE>")])
+  [
+    (set_attr "type" "vfwred<order>")
+    (set_attr "mode" "<VSF:MODE>")
+  ]
+)
 
 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated permutation operations
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 534698e..a8f291c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3326,17 +3326,26 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
       case CODE_FOR_fmakf4_odd:
 	icode = CODE_FOR_fmatf4_odd;
 	break;
-      case CODE_FOR_xsxexpqp_kf:
-	icode = CODE_FOR_xsxexpqp_tf;
+      case CODE_FOR_xsxexpqp_kf_di:
+	icode = CODE_FOR_xsxexpqp_tf_di;
 	break;
-      case CODE_FOR_xsxsigqp_kf:
-	icode = CODE_FOR_xsxsigqp_tf;
+      case CODE_FOR_xsxexpqp_kf_v2di:
+	icode = CODE_FOR_xsxexpqp_tf_v2di;
+	break;
+      case CODE_FOR_xsxsigqp_kf_ti:
+	icode = CODE_FOR_xsxsigqp_tf_ti;
+	break;
+      case CODE_FOR_xsxsigqp_kf_v1ti:
+	icode = CODE_FOR_xsxsigqp_tf_v1ti;
 	break;
       case CODE_FOR_xststdcnegqp_kf:
 	icode = CODE_FOR_xststdcnegqp_tf;
 	break;
-      case CODE_FOR_xsiexpqp_kf:
-	icode = CODE_FOR_xsiexpqp_tf;
+      case CODE_FOR_xsiexpqp_kf_di:
+	icode = CODE_FOR_xsiexpqp_tf_di;
+	break;
+      case CODE_FOR_xsiexpqp_kf_v2di:
+	icode = CODE_FOR_xsiexpqp_tf_v2di;
 	break;
       case CODE_FOR_xsiexpqpf_kf:
 	icode = CODE_FOR_xsiexpqpf_tf;
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 5ac6af4..1062cd4 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2901,19 +2901,28 @@
     TRUNCF128_ODD trunckfdf2_odd {}
 
   const signed long long __builtin_vsx_scalar_extract_expq (_Float128);
-    VSEEQP xsxexpqp_kf {}
+    VSEEQP xsxexpqp_kf_di {}
+
+  vull __builtin_vsx_scalar_extract_exp_to_vec (_Float128);
+    VSEEQPV xsxexpqp_kf_v2di {}
 
   const signed __int128 __builtin_vsx_scalar_extract_sigq (_Float128);
-    VSESQP xsxsigqp_kf {}
+    VSESQP xsxsigqp_kf_ti {}
+
+  vuq __builtin_vsx_scalar_extract_sig_to_vec (_Float128);
+    VSESQPV xsxsigqp_kf_v1ti {}
 
   const _Float128 __builtin_vsx_scalar_insert_exp_q (unsigned __int128, \
                                                      unsigned long long);
-    VSIEQP xsiexpqp_kf {}
+    VSIEQP xsiexpqp_kf_di {}
 
   const _Float128 __builtin_vsx_scalar_insert_exp_qp (_Float128, \
                                                       unsigned long long);
     VSIEQPF xsiexpqpf_kf {}
 
+  const _Float128 __builtin_vsx_scalar_insert_exp_vqp (vuq, vull);
+    VSIEQPV xsiexpqp_kf_v2di {}
+
   const signed int __builtin_vsx_scalar_test_data_class_qp (_Float128, \
                                                             const int<7>);
     VSTDCQP xststdcqp_kf {}
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 8555174..11060f6 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -1929,11 +1929,15 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
 	   128-bit variant of built-in function.  */
 	if (GET_MODE_PRECISION (arg1_mode) > 64)
 	  {
-	    /* If first argument is of float variety, choose variant
-	       that expects __ieee128 argument.  Otherwise, expect
-	       __int128 argument.  */
+	    /* If first argument is of float variety, choose the variant that
+	       expects __ieee128 argument.  If the first argument is vector
+	       int, choose the variant that expects vector unsigned
+	       __int128 argument.  Otherwise, expect scalar __int128 argument.
+	    */
 	    if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT)
 	      instance_code = RS6000_BIF_VSIEQPF;
+	    else if (GET_MODE_CLASS (arg1_mode) == MODE_VECTOR_INT)
+	      instance_code = RS6000_BIF_VSIEQPV;
 	    else
 	      instance_code = RS6000_BIF_VSIEQP;
 	  }
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index c582490..470d718 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -4515,6 +4515,18 @@
     VSIEQP
   _Float128 __builtin_vec_scalar_insert_exp (_Float128, unsigned long long);
     VSIEQPF
+  _Float128 __builtin_vec_scalar_insert_exp (vuq, vull);
+    VSIEQPV
+
+[VEC_VSEEV, scalar_extract_exp_to_vec, \
+            __builtin_vec_scalar_extract_exp_to_vector]
+  vull __builtin_vec_scalar_extract_exp_to_vector (_Float128);
+    VSEEQPV
+
+[VEC_VSESV, scalar_extract_sig_to_vec, \
+            __builtin_vec_scalar_extract_sig_to_vector]
+  vuq __builtin_vec_scalar_extract_sig_to_vector (_Float128);
+    VSESQPV
 
 [VEC_VSTDC, scalar_test_data_class, __builtin_vec_scalar_test_data_class]
   unsigned int __builtin_vec_scalar_test_data_class (float, const int);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ea68ca6..546c353 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1760,6 +1760,10 @@ static const struct attribute_spec rs6000_attribute_table[] =
 
 #undef TARGET_UPDATE_IPA_FN_TARGET_INFO
 #define TARGET_UPDATE_IPA_FN_TARGET_INFO rs6000_update_ipa_fn_target_info
+
+#undef TARGET_CONST_ANCHOR
+#define TARGET_CONST_ANCHOR 0x8000
+
 
 
 /* Processor table.  */
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0a34cee..e017381 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -396,6 +396,9 @@
 			   V4SF
 			   V2DF
 			   V2DI])
+(define_mode_iterator V2DI_DI  [V2DI DI])
+(define_mode_attr DI_to_TI [(V2DI "V1TI")
+			    (DI   "TI")])
 
 (define_mode_attr VM3_char [(V2DI "d")
 			   (V4SI "w")
@@ -5008,9 +5011,10 @@
 ;; ISA 3.0 Binary Floating-Point Support
 
 ;; VSX Scalar Extract Exponent Quad-Precision
-(define_insn "xsxexpqp_<mode>"
-  [(set (match_operand:DI 0 "altivec_register_operand" "=v")
-	(unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+(define_insn "xsxexpqp_<IEEE128:mode>_<V2DI_DI:mode>"
+  [(set (match_operand:V2DI_DI 0 "altivec_register_operand" "=v")
+	(unspec:V2DI_DI
+	  [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
 	 UNSPEC_VSX_SXEXPDP))]
   "TARGET_P9_VECTOR"
   "xsxexpqp %0,%1"
@@ -5026,9 +5030,10 @@
   [(set_attr "type" "integer")])
 
 ;; VSX Scalar Extract Significand Quad-Precision
-(define_insn "xsxsigqp_<mode>"
-  [(set (match_operand:TI 0 "altivec_register_operand" "=v")
-	(unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+(define_insn "xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>"
+  [(set (match_operand:VEC_TI 0 "altivec_register_operand" "=v")
+	(unspec:VEC_TI [(match_operand:IEEE128 1
+			    "altivec_register_operand" "v")]
 	 UNSPEC_VSX_SXSIG))]
   "TARGET_P9_VECTOR"
   "xsxsigqp %0,%1"
@@ -5055,10 +5060,12 @@
   [(set_attr "type" "vecmove")])
 
 ;; VSX Scalar Insert Exponent Quad-Precision
-(define_insn "xsiexpqp_<mode>"
+(define_insn "xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>"
   [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
-	(unspec:IEEE128 [(match_operand:TI 1 "altivec_register_operand" "v")
-			 (match_operand:DI 2 "altivec_register_operand" "v")]
+	(unspec:IEEE128 [(match_operand:<DI_to_TI> 1
+			  "altivec_register_operand" "v")
+			 (match_operand:V2DI_DI 2
+			  "altivec_register_operand" "v")]
 	 UNSPEC_VSX_SIEXPQP))]
   "TARGET_P9_VECTOR"
   "xsiexpqp %0,%1,%2"
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 4622dba..5cb1795 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -9269,7 +9269,7 @@
 		 (match_operand:SF 3 "arith_reg_operand" "0")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
+  "TARGET_SH2E && flag_fp_contract_mode == FP_CONTRACT_FAST"
   "fmac	%1,%2,%0"
   "&& can_create_pseudo_p ()"
   [(parallel [(set (match_dup 0)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 3b5d25b..dd35e63 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -58,6 +58,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "insn-attr.h"
 #include "tree-pass.h"
 #include "print-rtl.h"
+#include <math.h>
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -131,7 +132,6 @@ static bool xtensa_rtx_costs (rtx, machine_mode, int, int, int *, bool);
 static int xtensa_insn_cost (rtx_insn *, bool);
 static int xtensa_register_move_cost (machine_mode, reg_class_t,
 				      reg_class_t);
-static int xtensa_memory_move_cost (machine_mode, reg_class_t, bool);
 static tree xtensa_build_builtin_va_list (void);
 static bool xtensa_return_in_memory (const_tree, const_tree);
 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *,
@@ -213,8 +213,6 @@ static rtx xtensa_delegitimize_address (rtx);
 
 #undef TARGET_REGISTER_MOVE_COST
 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost
-#undef TARGET_MEMORY_MOVE_COST
-#define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost
 #undef TARGET_RTX_COSTS
 #define TARGET_RTX_COSTS xtensa_rtx_costs
 #undef TARGET_INSN_COST
@@ -1070,7 +1068,7 @@ xtensa_constantsynth_2insn (rtx dst, HOST_WIDE_INT srcval,
 {
   HOST_WIDE_INT imm = INT_MAX;
   rtx x = NULL_RTX;
-  int shift;
+  int shift, sqr;
 
   gcc_assert (REG_P (dst));
 
@@ -1081,7 +1079,6 @@ xtensa_constantsynth_2insn (rtx dst, HOST_WIDE_INT srcval,
       x = gen_lshrsi3 (dst, dst, GEN_INT (32 - shift));
     }
 
-
   shift = ctz_hwi (srcval);
   if ((!x || (TARGET_DENSITY && ! IN_RANGE (imm, -32, 95)))
       && xtensa_simm12b (srcval >> shift))
@@ -1108,6 +1105,14 @@ xtensa_constantsynth_2insn (rtx dst, HOST_WIDE_INT srcval,
       x = gen_addsi3 (dst, dst, GEN_INT (imm1));
     }
 
+  sqr = (int) floorf (sqrtf (srcval));
+  if (TARGET_MUL32 && optimize_size
+      && !x && IN_RANGE (srcval, 0, (2047 * 2047)) && sqr * sqr == srcval)
+    {
+      imm = sqr;
+      x = gen_mulsi3 (dst, dst, dst);
+    }
+
   if (!x)
     return 0;
 
@@ -4356,16 +4361,6 @@ xtensa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
     return 10;
 }
 
-/* Worker function for TARGET_MEMORY_MOVE_COST.  */
-
-static int
-xtensa_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
-			 reg_class_t rclass ATTRIBUTE_UNUSED,
-			 bool in ATTRIBUTE_UNUSED)
-{
-  return 4;
-}
-
 /* Compute a (partial) cost for rtx X.  Return true if the complete
    cost has been computed, and false if subexpressions should be
    scanned.  In either case, *TOTAL contains the cost result.  */
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 9261bfa..7230564 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2023-06-16  Alex Coplan  <alex.coplan@arm.com>
+
+	* parser.cc (cp_parser_enum_specifier): Don't reject
+	elaborated-type-specifier with enum-base, instead emit new
+	Welaborated-enum-base warning.
+
 2023-06-14  Jason Merrill  <jason@redhat.com>
 
 	DR 2327
diff --git a/gcc/cse.cc b/gcc/cse.cc
index 2bb63ac..c468700 100644
--- a/gcc/cse.cc
+++ b/gcc/cse.cc
@@ -1312,11 +1312,10 @@ try_const_anchors (rtx src_const, machine_mode mode)
   rtx lower_exp = NULL_RTX, upper_exp = NULL_RTX;
   unsigned lower_old, upper_old;
 
-  /* CONST_INT is used for CC modes, but we should leave those alone.  */
-  if (GET_MODE_CLASS (mode) == MODE_CC)
+  /* CONST_INT may be in various modes, avoid non-scalar-int mode. */
+  if (!SCALAR_INT_MODE_P (mode))
     return NULL_RTX;
 
-  gcc_assert (SCALAR_INT_MODE_P (mode));
   if (!compute_const_anchors (src_const, &lower_base, &lower_offs,
 			      &upper_base, &upper_offs))
     return NULL_RTX;
@@ -2208,13 +2207,26 @@ hash_rtx_string (const char *ps)
   return hash;
 }
 
-/* Same as hash_rtx, but call CB on each rtx if it is not NULL.
+/* Hash an rtx.  We are careful to make sure the value is never negative.
+   Equivalent registers hash identically.
+   MODE is used in hashing for CONST_INTs only;
+   otherwise the mode of X is used.
+
+   Store 1 in DO_NOT_RECORD_P if any subexpression is volatile.
+
+   If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains
+   a MEM rtx which does not have the MEM_READONLY_P flag set.
+
+   Note that cse_insn knows that the hash code of a MEM expression
+   is just (int) MEM plus the hash code of the address.
+
+   Call CB on each rtx if CB is not NULL.
    When the callback returns true, we continue with the new rtx.  */
 
 unsigned
-hash_rtx_cb (const_rtx x, machine_mode mode,
-             int *do_not_record_p, int *hash_arg_in_memory_p,
-             bool have_reg_qty, hash_rtx_callback_function cb)
+hash_rtx (const_rtx x, machine_mode mode,
+	  int *do_not_record_p, int *hash_arg_in_memory_p,
+	  bool have_reg_qty, hash_rtx_callback_function cb)
 {
   int i, j;
   unsigned hash = 0;
@@ -2234,8 +2246,8 @@ hash_rtx_cb (const_rtx x, machine_mode mode,
   if (cb != NULL
       && ((*cb) (x, mode, &newx, &newmode)))
     {
-      hash += hash_rtx_cb (newx, newmode, do_not_record_p,
-                           hash_arg_in_memory_p, have_reg_qty, cb);
+      hash += hash_rtx (newx, newmode, do_not_record_p,
+			hash_arg_in_memory_p, have_reg_qty, cb);
       return hash;
     }
 
@@ -2355,9 +2367,9 @@ hash_rtx_cb (const_rtx x, machine_mode mode,
 	for (i = 0; i < units; ++i)
 	  {
 	    elt = CONST_VECTOR_ENCODED_ELT (x, i);
-	    hash += hash_rtx_cb (elt, GET_MODE (elt),
-                                 do_not_record_p, hash_arg_in_memory_p,
-                                 have_reg_qty, cb);
+	    hash += hash_rtx (elt, GET_MODE (elt),
+			      do_not_record_p, hash_arg_in_memory_p,
+			      have_reg_qty, cb);
 	  }
 
 	return hash;
@@ -2463,10 +2475,10 @@ hash_rtx_cb (const_rtx x, machine_mode mode,
 	    {
 	      for (i = 1; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
 		{
-		  hash += (hash_rtx_cb (ASM_OPERANDS_INPUT (x, i),
-                                        GET_MODE (ASM_OPERANDS_INPUT (x, i)),
-                                        do_not_record_p, hash_arg_in_memory_p,
-                                        have_reg_qty, cb)
+		  hash += (hash_rtx (ASM_OPERANDS_INPUT (x, i),
+				     GET_MODE (ASM_OPERANDS_INPUT (x, i)),
+				     do_not_record_p, hash_arg_in_memory_p,
+				     have_reg_qty, cb)
 			   + hash_rtx_string
                            (ASM_OPERANDS_INPUT_CONSTRAINT (x, i)));
 		}
@@ -2502,16 +2514,16 @@ hash_rtx_cb (const_rtx x, machine_mode mode,
 	      goto repeat;
 	    }
 
-	  hash += hash_rtx_cb (XEXP (x, i), VOIDmode, do_not_record_p,
-                               hash_arg_in_memory_p,
-                               have_reg_qty, cb);
+	  hash += hash_rtx (XEXP (x, i), VOIDmode, do_not_record_p,
+			    hash_arg_in_memory_p,
+			    have_reg_qty, cb);
 	  break;
 
 	case 'E':
 	  for (j = 0; j < XVECLEN (x, i); j++)
-	    hash += hash_rtx_cb (XVECEXP (x, i, j), VOIDmode, do_not_record_p,
-                                 hash_arg_in_memory_p,
-                                 have_reg_qty, cb);
+	    hash += hash_rtx (XVECEXP (x, i, j), VOIDmode, do_not_record_p,
+			      hash_arg_in_memory_p,
+			      have_reg_qty, cb);
 	  break;
 
 	case 's':
@@ -2538,27 +2550,6 @@ hash_rtx_cb (const_rtx x, machine_mode mode,
   return hash;
 }
 
-/* Hash an rtx.  We are careful to make sure the value is never negative.
-   Equivalent registers hash identically.
-   MODE is used in hashing for CONST_INTs only;
-   otherwise the mode of X is used.
-
-   Store 1 in DO_NOT_RECORD_P if any subexpression is volatile.
-
-   If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains
-   a MEM rtx which does not have the MEM_READONLY_P flag set.
-
-   Note that cse_insn knows that the hash code of a MEM expression
-   is just (int) MEM plus the hash code of the address.  */
-
-unsigned
-hash_rtx (const_rtx x, machine_mode mode, int *do_not_record_p,
-	  int *hash_arg_in_memory_p, bool have_reg_qty)
-{
-  return hash_rtx_cb (x, mode, do_not_record_p,
-                      hash_arg_in_memory_p, have_reg_qty, NULL);
-}
-
 /* Hash an rtx X for cse via hash_rtx.
    Stores 1 in do_not_record if any subexpression is volatile.
    Stores 1 in hash_arg_in_memory if X contains a mem rtx which
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index e01e244..3040a9b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -12839,6 +12839,50 @@ after addition, conditional jump on carry etc.
  
 @enddefbuiltin
 
+@defbuiltin{unsigned int __builtin_addc (unsigned int a, unsigned int b, unsigned int carry_in, unsigned int *carry_out)}
+@defbuiltinx{unsigned long int __builtin_addcl (unsigned long int a, unsigned long int b, unsigned int carry_in, unsigned long int *carry_out)}
+@defbuiltinx{unsigned long long int __builtin_addcll (unsigned long long int a, unsigned long long int b, unsigned long long int carry_in, unsigned long long int *carry_out)}
+
+These built-in functions are equivalent to:
+@smallexample
+  (@{ __typeof__ (@var{a}) s; \
+      __typeof__ (@var{a}) c1 = __builtin_add_overflow (@var{a}, @var{b}, &s); \
+      __typeof__ (@var{a}) c2 = __builtin_add_overflow (s, @var{carry_in}, &s); \
+      *(@var{carry_out}) = c1 | c2; \
+      s; @})
+@end smallexample
+
+i.e.@: they add 3 unsigned values, set what the last argument
+points to to 1 if any of the two additions overflowed (otherwise 0)
+and return the sum of those 3 unsigned values.  Note, while all
+the first 3 arguments can have arbitrary values, better code will be
+emitted if one of them (preferrably the third one) has only values
+0 or 1 (i.e.@: carry-in).
+
+@enddefbuiltin
+
+@defbuiltin{unsigned int __builtin_subc (unsigned int a, unsigned int b, unsigned int carry_in, unsigned int *carry_out)}
+@defbuiltinx{unsigned long int __builtin_subcl (unsigned long int a, unsigned long int b, unsigned int carry_in, unsigned long int *carry_out)}
+@defbuiltinx{unsigned long long int __builtin_subcll (unsigned long long int a, unsigned long long int b, unsigned long long int carry_in, unsigned long long int *carry_out)}
+
+These built-in functions are equivalent to:
+@smallexample
+  (@{ __typeof__ (@var{a}) s; \
+      __typeof__ (@var{a}) c1 = __builtin_sub_overflow (@var{a}, @var{b}, &s); \
+      __typeof__ (@var{a}) c2 = __builtin_sub_overflow (s, @var{carry_in}, &s); \
+      *(@var{carry_out}) = c1 | c2; \
+      s; @})
+@end smallexample
+
+i.e.@: they subtract 2 unsigned values from the first unsigned value,
+set what the last argument points to to 1 if any of the two subtractions
+overflowed (otherwise 0) and return the result of the subtractions.
+Note, while all the first 3 arguments can have arbitrary values, better code
+will be emitted if one of them (preferrably the third one) has only values
+0 or 1 (i.e.@: carry-in).
+
+@enddefbuiltin
+
 @node x86 specific memory model extensions for transactional memory
 @section x86-Specific Memory Model Extensions for Transactional Memory
 
@@ -19763,6 +19807,10 @@ double scalar_insert_exp (double significand, unsigned long long int exponent);
 ieee_128 scalar_insert_exp (unsigned __int128 significand,
                             unsigned long long int exponent);
 ieee_128 scalar_insert_exp (ieee_128 significand, unsigned long long int exponent);
+vector ieee_128 scalar_insert_exp (vector unsigned __int128 significand,
+                                   vector unsigned long long exponent);
+vector unsigned long long scalar_extract_exp_to_vec (ieee_128);
+vector unsigned __int128  scalar_extract_sig_to_vec (ieee_128);
 
 int scalar_cmp_exp_gt (double arg1, double arg2);
 int scalar_cmp_exp_lt (double arg1, double arg2);
@@ -19813,11 +19861,21 @@ of the result are composed of the least significant 11 bits of the
 
 When supplied with a 128-bit first argument, the
 @code{scalar_insert_exp} built-in function returns a quad-precision
-ieee floating point value.  The sign bit of the result is copied from
-the most significant bit of the @code{significand} argument.
-The significand and exponent components of the result are composed of
-the least significant 15 bits of the @code{exponent} argument and the
-least significant 112 bits of the @code{significand} argument respectively.
+IEEE floating point value if the two arguments were scalar.  If the two
+arguments are vectors, the return value is a vector IEEE floating point value.
+The sign bit of the result is copied from the most significant bit of the
+@code{significand} argument.  The significand and exponent components of the
+result are composed of the least significant 15 bits of the @code{exponent}
+argument (element 0 on big-endian and element 1 on little-endian) and the
+least significant 112 bits of the @code{significand} argument
+respectively.  Note, the @code{significand} is the scalar argument or in the
+case of vector arguments, @code{significand} is element 0 for big-endian and
+element 1 for little-endian.
+
+The @code{scalar_extract_exp_to_vec},
+and @code{scalar_extract_sig_to_vec} are similar to
+@code{scalar_extract_exp}, @code{scalar_extract_sig} except they return
+a vector result of type unsigned long long and unsigned __int128 respectively.
 
 The @code{scalar_cmp_exp_gt}, @code{scalar_cmp_exp_lt},
 @code{scalar_cmp_exp_eq}, and @code{scalar_cmp_exp_unordered} built-in
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index fafdee3..8c17a81 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -2718,7 +2718,7 @@ Typical command lines are
 
 @smallexample
 -foffload-options='-fno-math-errno -ffinite-math-only' -foffload-options=nvptx-none=-latomic
--foffload-options=amdgcn-amdhsa=-march=gfx906 -foffload-options=-O3
+-foffload-options=amdgcn-amdhsa=-march=gfx906
 @end smallexample
 
 @opindex fopenacc
@@ -12077,10 +12077,12 @@ This option is enabled by default at optimization levels @option{-O1},
 such as forming of fused multiply-add operations if the target has
 native support for them.
 @option{-ffp-contract=on} enables floating-point expression contraction
-if allowed by the language standard.  This is currently not implemented
-and treated equal to @option{-ffp-contract=off}.
+if allowed by the language standard.  This is implemented for C and C++,
+where it enables contraction within one expression, but not across
+different statements.
 
-The default is @option{-ffp-contract=fast}.
+The default is @option{-ffp-contract=off} for C in a standards compliant mode
+(@option{-std=c11} or similar), @option{-ffp-contract=fast} otherwise.
 
 @opindex fomit-frame-pointer
 @item -fomit-frame-pointer
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index a43fd65..9648fdc 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -27,6 +27,7 @@ See the next chapter for information on the C header file.
                         from such an insn.
 * Output Statement::    For more generality, write C code to output
                         the assembler code.
+* Compact Syntax::      Compact syntax for writing machine descriptors.
 * Predicates::          Controlling what kinds of operands can be used
                         for an insn.
 * Constraints::         Fine-tuning operand selection.
@@ -713,6 +714,168 @@ you can use @samp{*} inside of a @samp{@@} multi-alternative template:
 @end group
 @end smallexample
 
+@node Compact Syntax
+@section Compact Syntax
+@cindex compact syntax
+
+When a @code{define_insn} or @code{define_insn_and_split} has multiple
+alternatives it may be beneficial to use the compact syntax when specifying
+alternatives.
+
+This syntax puts the constraints and attributes on the same horizontal line as
+the instruction assembly template.
+
+As an example
+
+@smallexample
+@group
+(define_insn_and_split ""
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r")
+	(match_operand:SI 1 "aarch64_mov_operand"  " r,r,k,M,n,Usv"))]
+  ""
+  "@@
+   mov\\t%w0, %w1
+   mov\\t%w0, %w1
+   mov\\t%w0, %w1
+   mov\\t%w0, %1
+   #
+   * return aarch64_output_sve_cnt_immediate ('cnt', '%x0', operands[1]);"
+  "&& true"
+   [(const_int 0)]
+  @{
+     aarch64_expand_mov_immediate (operands[0], operands[1]);
+     DONE;
+  @}
+  [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,mov_imm")
+   (set_attr "arch"   "*,*,*,*,*,sve")
+   (set_attr "length" "4,4,4,4,*,  4")
+]
+)
+@end group
+@end smallexample
+
+can be better expressed as:
+
+@smallexample
+@group
+(define_insn_and_split ""
+  [(set (match_operand:SI 0 "nonimmediate_operand")
+	(match_operand:SI 1 "aarch64_mov_operand"))]
+  ""
+  @{@@ [cons: =0, 1; attrs: type, arch, length]
+     [r , r  ; mov_reg  , *   , 4] mov\t%w0, %w1
+     [k , r  ; mov_reg  , *   , 4] ^
+     [r , k  ; mov_reg  , *   , 4] ^
+     [r , M  ; mov_imm  , *   , 4] mov\t%w0, %1
+     [r , n  ; mov_imm  , *   , *] #
+     [r , Usv; mov_imm  , sve , 4] << aarch64_output_sve_cnt_immediate ("cnt", "%x0", operands[1]);
+  @}
+  "&& true"
+  [(const_int 0)]
+  @{
+    aarch64_expand_mov_immediate (operands[0], operands[1]);
+    DONE;
+  @}
+)
+@end group
+@end smallexample
+
+The syntax rules are as follows:
+@itemize @bullet
+@item
+Templates must start with @samp{@{@@} to use the new syntax.
+
+@item
+@samp{@{@@} is followed by a layout in square brackets which is @samp{cons:}
+followed by a comma-separated list of @code{match_operand}/@code{match_scratch}
+operand numbers, then a semicolon, followed by the same for attributes
+(@samp{attrs:}).  Operand modifiers like @code{=} and @code{+} can be placed
+before an operand number.
+Both sections are optional (so you can use only @samp{cons}, or only
+@samp{attrs}, or both), and @samp{cons} must come before @samp{attrs} if
+present.
+
+@item
+Each alternative begins with any amount of whitespace.
+
+@item
+Following the whitespace is a comma-separated list of "constraints" and/or
+"attributes" within brackets @code{[]}, with sections separated by a semicolon.
+
+@item
+Should you want to copy the previous asm line, the symbol @code{^} can be used.
+This allows less copy pasting between alternative and reduces the number of
+lines to update on changes.
+
+@item
+When using C functions for output, the idiom @samp{* return @var{function};}
+can be replaced with the shorthand @samp{<< @var{function};}.
+
+@item
+Following the closing @samp{]} is any amount of whitespace, and then the actual
+asm output.
+
+@item
+Spaces are allowed in the list (they will simply be removed).
+
+@item
+All constraint alternatives should be specified.  For example, a list of
+of three blank alternatives should be written @samp{[,,]} rather than
+@samp{[]}.
+
+@item
+All attribute alternatives should be non-empty, with @samp{*}
+representing the default attribute value.  For example, a list of three
+default attribute values should be written @samp{[*,*,*]} rather than
+@samp{[]}.
+
+@item
+Within an @samp{@{@@} block both multiline and singleline C comments are
+allowed, but when used outside of a C block they must be the only non-whitespace
+blocks on the line.
+
+@item
+Within an @samp{@{@@} block, any iterators that do not get expanded will result
+in an error.  If for some reason it is required to have @code{<} or @code{>} in
+the output then these must be escaped using @samp{\}.
+
+@item
+It is possible to use the @samp{attrs} list to specify some attributes and to
+use the normal @code{set_attr} syntax to specify other attributes.  There must
+not be any overlap between the two lists.
+
+In other words, the following is valid:
+@smallexample
+@group
+(define_insn_and_split ""
+  [(set (match_operand:SI 0 "nonimmediate_operand")
+	(match_operand:SI 1 "aarch64_mov_operand"))]
+  ""
+  @{@@ [cons: 0, 1; attrs: type, arch, length]@}
+  @dots{} 
+  [(set_attr "foo" "mov_imm")]
+)
+@end group
+@end smallexample
+
+but this is not valid:
+@smallexample
+@group
+(define_insn_and_split ""
+  [(set (match_operand:SI 0 "nonimmediate_operand")
+	(match_operand:SI 1 "aarch64_mov_operand"))]
+  ""
+  @{@@ [cons: 0, 1; attrs: type, arch, length]@}
+  @dots{} 
+  [(set_attr "arch" "bar")
+   (set_attr "foo" "mov_imm")]
+)
+@end group
+@end smallexample
+
+because it specifies @code{arch} twice.
+@end itemize
+
 @node Predicates
 @section Predicates
 @cindex predicates
@@ -5094,7 +5257,7 @@ This pattern is not allowed to @code{FAIL}.
 
 @cindex @code{len_load_@var{m}} instruction pattern
 @item @samp{len_load_@var{m}}
-Load (operand 2 - operand 3) elements from vector memory operand 1
+Load (operand 2 + operand 3) elements from memory operand 1
 into vector register operand 0, setting the other elements of
 operand 0 to undefined values.  Operands 0 and 1 have mode @var{m},
 which must be a vector mode.  Operand 2 has whichever integer mode the
@@ -5105,7 +5268,7 @@ constant bias: it is either a constant 0 or a constant -1.  The predicate on
 operand 3 must only accept the bias values that the target actually supports.
 GCC handles a bias of 0 more efficiently than a bias of -1.
 
-If (operand 2 - operand 3) exceeds the number of elements in mode
+If (operand 2 + operand 3) exceeds the number of elements in mode
 @var{m}, the behavior is undefined.
 
 If the target prefers the length to be measured in bytes rather than
@@ -5116,7 +5279,7 @@ This pattern is not allowed to @code{FAIL}.
 
 @cindex @code{len_store_@var{m}} instruction pattern
 @item @samp{len_store_@var{m}}
-Store (operand 2 - operand 3) vector elements from vector register operand 1
+Store (operand 2 + operand 3) vector elements from vector register operand 1
 into memory operand 0, leaving the other elements of
 operand 0 unchanged.  Operands 0 and 1 have mode @var{m}, which must be
 a vector mode.  Operand 2 has whichever integer mode the target prefers.
@@ -5127,7 +5290,60 @@ constant bias: it is either a constant 0 or a constant -1.  The predicate on
 operand 3 must only accept the bias values that the target actually supports.
 GCC handles a bias of 0 more efficiently than a bias of -1.
 
-If (operand 2 - operand 3) exceeds the number of elements in mode
+If (operand 2 + operand 3) exceeds the number of elements in mode
+@var{m}, the behavior is undefined.
+
+If the target prefers the length to be measured in bytes
+rather than elements, it should only implement this pattern for vectors
+of @code{QI} elements.
+
+This pattern is not allowed to @code{FAIL}.
+
+@cindex @code{len_maskload@var{m}@var{n}} instruction pattern
+@item @samp{len_maskload@var{m}@var{n}}
+Perform a masked load from the memory location pointed to by operand 1
+into register operand 0.  (operand 2 + operand 4) elements are loaded from
+memory and other elements in operand 0 are set to undefined values.
+This is a combination of len_load and maskload.
+Operands 0 and 1 have mode @var{m}, which must be a vector mode.  Operand 2
+has whichever integer mode the target prefers.  A mask is specified in
+operand 3 which must be of type @var{n}.  The mask has lower precedence than
+the length and is itself subject to length masking,
+i.e. only mask indices < (operand 2 + operand 4) are used.
+Operand 4 conceptually has mode @code{QI}.
+
+Operand 2 can be a variable or a constant amount.  Operand 4 specifies a
+constant bias: it is either a constant 0 or a constant -1.  The predicate on
+operand 4 must only accept the bias values that the target actually supports.
+GCC handles a bias of 0 more efficiently than a bias of -1.
+
+If (operand 2 + operand 4) exceeds the number of elements in mode
+@var{m}, the behavior is undefined.
+
+If the target prefers the length to be measured in bytes
+rather than elements, it should only implement this pattern for vectors
+of @code{QI} elements.
+
+This pattern is not allowed to @code{FAIL}.
+
+@cindex @code{len_maskstore@var{m}@var{n}} instruction pattern
+@item @samp{len_maskstore@var{m}@var{n}}
+Perform a masked store from vector register operand 1 into memory operand 0.
+(operand 2 + operand 4) elements are stored to memory
+and leave the other elements of operand 0 unchanged.
+This is a combination of len_store and maskstore.
+Operands 0 and 1 have mode @var{m}, which must be a vector mode.  Operand 2 has whichever
+integer mode the target prefers.  A mask is specified in operand 3 which must be
+of type @var{n}.  The mask has lower precedence than the length and is itself subject to
+length masking, i.e. only mask indices < (operand 2 + operand 4) are used.
+Operand 4 conceptually has mode @code{QI}.
+
+Operand 2 can be a variable or a constant amount.  Operand 3 specifies a
+constant bias: it is either a constant 0 or a constant -1.  The predicate on
+operand 4 must only accept the bias values that the target actually supports.
+GCC handles a bias of 0 more efficiently than a bias of -1.
+
+If (operand 2 + operand 4) exceeds the number of elements in mode
 @var{m}, the behavior is undefined.
 
 If the target prefers the length to be measured in bytes
diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index d89ffa6..e70c47c 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -26533,7 +26533,8 @@ process_scope_var (tree stmt, tree decl, tree origin, dw_die_ref context_die)
 
   if (die != NULL && die->die_parent == NULL)
     add_child_die (context_die, die);
-  else if (TREE_CODE (decl_or_origin) == IMPORTED_DECL)
+
+  if (TREE_CODE (decl_or_origin) == IMPORTED_DECL)
     {
       if (early_dwarf)
 	dwarf2out_imported_module_or_decl_1 (decl_or_origin, DECL_NAME (decl_or_origin),
diff --git a/gcc/early-remat.cc b/gcc/early-remat.cc
index 1ee63c7..700cb65 100644
--- a/gcc/early-remat.cc
+++ b/gcc/early-remat.cc
@@ -504,20 +504,20 @@ private:
 
 early_remat *early_remat::er;
 
-/* rtx_equal_p_cb callback that treats any two SCRATCHes as equal.
+/* rtx_equal_p callback that treats any two SCRATCHes as equal.
    This allows us to compare two copies of a pattern, even though their
    SCRATCHes are always distinct.  */
 
-static int
+static bool
 scratch_equal (const_rtx *x, const_rtx *y, rtx *nx, rtx *ny)
 {
   if (GET_CODE (*x) == SCRATCH && GET_CODE (*y) == SCRATCH)
     {
       *nx = const0_rtx;
       *ny = const0_rtx;
-      return 1;
+      return true;
     }
-  return 0;
+  return false;
 }
 
 /* Hash callback functions for remat_candidate.  */
@@ -534,10 +534,8 @@ remat_candidate_hasher::equal (const remat_candidate *cand1,
 {
   return (cand1->regno == cand2->regno
 	  && cand1->constant_p == cand2->constant_p
-	  && (cand1->constant_p
-	      ? rtx_equal_p (cand1->remat_rtx, cand2->remat_rtx)
-	      : rtx_equal_p_cb (cand1->remat_rtx, cand2->remat_rtx,
-				scratch_equal))
+	  && rtx_equal_p (cand1->remat_rtx, cand2->remat_rtx,
+			  cand1->constant_p ? NULL : scratch_equal)
 	  && (!cand1->uses || bitmap_equal_p (cand1->uses, cand2->uses)));
 }
 
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 7c6474e..f0424c6 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,53 @@
+2023-06-21  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/87477
+	PR fortran/88688
+	PR fortran/94380
+	PR fortran/107900
+	PR fortran/110224
+	* decl.cc (char_len_param_value): Fix memory leak.
+	(resolve_block_construct): Remove unnecessary static decls.
+	* expr.cc (gfc_is_ptr_fcn): New function.
+	(gfc_check_vardef_context): Use it to permit pointer function
+	result selectors to be used for associate names in variable
+	definition context.
+	* gfortran.h: Prototype for gfc_is_ptr_fcn.
+	* match.cc (build_associate_name): New function.
+	(gfc_match_select_type): Use the new function to replace inline
+	version and to build a new associate name for the case where
+	the supplied associate name is already used for that purpose.
+	* resolve.cc (resolve_assoc_var): Call gfc_is_ptr_fcn to allow
+	associate names with pointer function targets to be used in
+	variable definition context.
+	* trans-decl.cc (gfc_get_symbol_decl): Unlimited polymorphic
+	variables need deferred initialisation of the vptr.
+	(gfc_trans_deferred_vars): Do the vptr initialisation.
+	* trans-stmt.cc (trans_associate_var): Ensure that a pointer
+	associate name points to the target of the selector and not
+	the selector itself.
+
+2023-06-21  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/108961
+	* trans-expr.cc (gfc_conv_procedure_call): The hidden string
+	length must not be passed to a formal arg of type(cptr).
+
+2023-06-20  Tobias Burnus  <tobias@codesourcery.com>
+
+	* dump-parse-tree.cc (show_omp_namelist): Fix dump of the allocator
+	modifier of OMP_LIST_ALLOCATE.
+
+2023-06-20  Tobias Burnus  <tobias@codesourcery.com>
+
+	* match.cc (gfc_match_char): Match with '%S' a symbol
+	with host_assoc = 1.
+
+2023-06-19  Tobias Burnus  <tobias@codesourcery.com>
+
+	* intrinsic.texi (OpenMP Modules OMP_LIB and OMP_LIB_KINDS): Also
+	add references to the OpenMP 5.1 and 5.2 spec; add omp_initial_device
+	and omp_invalid_device named constants.
+
 2023-06-13  Harald Anlauf  <anlauf@gmx.de>
 	    Mikael Morin  <mikael@gcc.gnu.org>
 
diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc
index d09c8bc..844345d 100644
--- a/gcc/fortran/decl.cc
+++ b/gcc/fortran/decl.cc
@@ -1086,6 +1086,8 @@ char_len_param_value (gfc_expr **expr, bool *deferred)
   p = gfc_copy_expr (*expr);
   if (gfc_is_constant_expr (p) && gfc_simplify_expr (p, 1))
     gfc_replace_expr (*expr, p);
+  else
+    gfc_free_expr (p);
 
   if ((*expr)->expr_type == EXPR_FUNCTION)
     {
diff --git a/gcc/fortran/dump-parse-tree.cc b/gcc/fortran/dump-parse-tree.cc
index 99c8bda..effcebe 100644
--- a/gcc/fortran/dump-parse-tree.cc
+++ b/gcc/fortran/dump-parse-tree.cc
@@ -1374,7 +1374,7 @@ show_omp_namelist (int list_type, gfc_omp_namelist *n)
 	}
       if (list_type == OMP_LIST_ALLOCATE)
 	{
-	  if (n->expr)
+	  if (n->u2.allocator)
 	    {
 	      fputs ("allocator(", dumpfile);
 	      show_expr (n->u2.allocator);
@@ -1388,9 +1388,12 @@ show_omp_namelist (int list_type, gfc_omp_namelist *n)
 	      show_expr (n->u.align);
 	      fputc (')', dumpfile);
 	    }
-	  if (n->expr || n->u.align)
+	  if (n->u2.allocator || n->u.align)
 	    fputc (':', dumpfile);
-	  fputs (n->sym->name, dumpfile);
+	  if (n->expr)
+	    show_expr (n->expr);
+	  else
+	    fputs (n->sym->name, dumpfile);
 	  if (n->next)
 	    fputs (") ALLOCATE(", dumpfile);
 	  continue;
diff --git a/gcc/fortran/expr.cc b/gcc/fortran/expr.cc
index d5cfbe0..c960dfe 100644
--- a/gcc/fortran/expr.cc
+++ b/gcc/fortran/expr.cc
@@ -812,6 +812,16 @@ gfc_has_vector_index (gfc_expr *e)
 }
 
 
+bool
+gfc_is_ptr_fcn (gfc_expr *e)
+{
+  return e != NULL && e->expr_type == EXPR_FUNCTION
+	      && (gfc_expr_attr (e).pointer
+		  || (e->ts.type == BT_CLASS
+		      && CLASS_DATA (e)->attr.class_pointer));
+}
+
+
 /* Copy a shape array.  */
 
 mpz_t *
@@ -6470,6 +6480,22 @@ gfc_check_vardef_context (gfc_expr* e, bool pointer, bool alloc_obj,
 	    }
 	  return false;
 	}
+      else if (context && gfc_is_ptr_fcn (assoc->target))
+	{
+	  if (!gfc_notify_std (GFC_STD_F2018, "%qs at %L associated to "
+			       "pointer function target being used in a "
+			       "variable definition context (%s)", name,
+			       &e->where, context))
+	    return false;
+	  else if (gfc_has_vector_index (e))
+	    {
+	      gfc_error ("%qs at %L associated to vector-indexed target"
+			 " cannot be used in a variable definition"
+			 " context (%s)",
+			 name, &e->where, context);
+	      return false;
+	    }
+	}
 
       /* Target must be allowed to appear in a variable definition context.  */
       if (!gfc_check_vardef_context (assoc->target, pointer, false, false, NULL))
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index a58c60e..30631ab 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -3659,6 +3659,7 @@ bool gfc_is_constant_expr (gfc_expr *);
 bool gfc_simplify_expr (gfc_expr *, int);
 bool gfc_try_simplify_expr (gfc_expr *, int);
 bool gfc_has_vector_index (gfc_expr *);
+bool gfc_is_ptr_fcn (gfc_expr *);
 
 gfc_expr *gfc_get_expr (void);
 gfc_expr *gfc_get_array_expr (bt type, int kind, locus *);
diff --git a/gcc/fortran/intrinsic.texi b/gcc/fortran/intrinsic.texi
index 5555db2..6c7ad03 100644
--- a/gcc/fortran/intrinsic.texi
+++ b/gcc/fortran/intrinsic.texi
@@ -15247,8 +15247,9 @@ with the following options: @code{-fno-unsafe-math-optimizations
 @table @asis
 @item @emph{Standard}:
 OpenMP Application Program Interface v4.5,
-OpenMP Application Program Interface v5.0 (partially supported) and
-OpenMP Application Program Interface v5.1 (partially supported).
+OpenMP Application Program Interface v5.0 (partially supported),
+OpenMP Application Program Interface v5.1 (partially supported) and
+OpenMP Application Program Interface v5.2 (partially supported).
 @end table
 
 The OpenMP Fortran runtime library routines are provided both in
@@ -15262,9 +15263,13 @@ below.
 
 For details refer to the actual
 @uref{https://www.openmp.org/wp-content/uploads/openmp-4.5.pdf,
-OpenMP Application Program Interface v4.5} and
+OpenMP Application Program Interface v4.5},
 @uref{https://www.openmp.org/wp-content/uploads/OpenMP-API-Specification-5.0.pdf,
-OpenMP Application Program Interface v5.0}.
+OpenMP Application Program Interface v5.0},
+@uref{https://www.openmp.org/wp-content/uploads/OpenMP-API-Specification-5-1.pdf,
+OpenMP Application Program Interface v5.1} and
+@uref{https://www.openmp.org/wp-content/uploads/OpenMP-API-Specification-5-2.pdf,
+OpenMP Application Program Interface v5.2}.
 
 @code{OMP_LIB_KINDS} provides the following scalar default-integer
 named constants:
@@ -15295,6 +15300,13 @@ The following derived type:
 @item @code{omp_alloctrait}
 @end table
 
+The following scalar default-integer named constants:
+@table @asis
+@item @code{omp_initial_device}
+@item @code{omp_invalid_device}
+@end table
+
+
 The following scalar integer named constants of the
 kind @code{omp_sched_kind}:
 
diff --git a/gcc/fortran/match.cc b/gcc/fortran/match.cc
index e7be7fd..ca64e59 100644
--- a/gcc/fortran/match.cc
+++ b/gcc/fortran/match.cc
@@ -1084,7 +1084,8 @@ gfc_match_char (char c, bool gobble_ws)
 
    %%  Literal percent sign
    %e  Expression, pointer to a pointer is set
-   %s  Symbol, pointer to the symbol is set
+   %s  Symbol, pointer to the symbol is set (host_assoc = 0)
+   %S  Symbol, pointer to the symbol is set (host_assoc = 1)
    %n  Name, character buffer is set to name
    %t  Matches end of statement.
    %o  Matches an intrinsic operator, returned as an INTRINSIC enum.
@@ -1151,8 +1152,9 @@ loop:
 	  goto loop;
 
 	case 's':
+	case 'S':
 	  vp = va_arg (argp, void **);
-	  n = gfc_match_symbol ((gfc_symbol **) vp, 0);
+	  n = gfc_match_symbol ((gfc_symbol **) vp, c == 'S');
 	  if (n != MATCH_YES)
 	    {
 	      m = n;
@@ -6377,6 +6379,39 @@ build_class_sym:
 }
 
 
+/* Build the associate name  */
+static int
+build_associate_name (const char *name, gfc_expr **e1, gfc_expr **e2)
+{
+  gfc_expr *expr1 = *e1;
+  gfc_expr *expr2 = *e2;
+  gfc_symbol *sym;
+
+  /* For the case where the associate name is already an associate name.  */
+  if (!expr2)
+    expr2 = expr1;
+  expr1 = gfc_get_expr ();
+  expr1->expr_type = EXPR_VARIABLE;
+  expr1->where = expr2->where;
+  if (gfc_get_sym_tree (name, NULL, &expr1->symtree, false))
+    return 1;
+
+  sym = expr1->symtree->n.sym;
+  if (expr2->ts.type == BT_UNKNOWN)
+      sym->attr.untyped = 1;
+  else
+  copy_ts_from_selector_to_associate (expr1, expr2);
+
+  sym->attr.flavor = FL_VARIABLE;
+  sym->attr.referenced = 1;
+  sym->attr.class_ok = 1;
+
+  *e1 = expr1;
+  *e2 = expr2;
+  return 0;
+}
+
+
 /* Push the current selector onto the SELECT TYPE stack.  */
 
 static void
@@ -6532,7 +6567,6 @@ gfc_match_select_type (void)
   match m;
   char name[GFC_MAX_SYMBOL_LEN + 1];
   bool class_array;
-  gfc_symbol *sym;
   gfc_namespace *ns = gfc_current_ns;
 
   m = gfc_match_label ();
@@ -6554,24 +6588,11 @@ gfc_match_select_type (void)
   m = gfc_match (" %n => %e", name, &expr2);
   if (m == MATCH_YES)
     {
-      expr1 = gfc_get_expr ();
-      expr1->expr_type = EXPR_VARIABLE;
-      expr1->where = expr2->where;
-      if (gfc_get_sym_tree (name, NULL, &expr1->symtree, false))
+      if (build_associate_name (name, &expr1, &expr2))
 	{
 	  m = MATCH_ERROR;
 	  goto cleanup;
 	}
-
-      sym = expr1->symtree->n.sym;
-      if (expr2->ts.type == BT_UNKNOWN)
-	sym->attr.untyped = 1;
-      else
-	copy_ts_from_selector_to_associate (expr1, expr2);
-
-      sym->attr.flavor = FL_VARIABLE;
-      sym->attr.referenced = 1;
-      sym->attr.class_ok = 1;
     }
   else
     {
@@ -6618,6 +6639,17 @@ gfc_match_select_type (void)
       goto cleanup;
     }
 
+  /* Prevent an existing associate name from reuse here by pushing expr1 to
+     expr2 and building a new associate name.  */
+  if (!expr2 && expr1->symtree->n.sym->assoc
+      && !expr1->symtree->n.sym->attr.select_type_temporary
+      && !expr1->symtree->n.sym->attr.select_rank_temporary
+      && build_associate_name (expr1->symtree->n.sym->name, &expr1, &expr2))
+    {
+      m = MATCH_ERROR;
+      goto cleanup;
+    }
+
   new_st.op = EXEC_SELECT_TYPE;
   new_st.expr1 = expr1;
   new_st.expr2 = expr2;
diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc
index 50b49d0..82e6ac5 100644
--- a/gcc/fortran/resolve.cc
+++ b/gcc/fortran/resolve.cc
@@ -9254,9 +9254,10 @@ resolve_assoc_var (gfc_symbol* sym, bool resolve_target)
   gcc_assert (sym->ts.type != BT_UNKNOWN);
 
   /* See if this is a valid association-to-variable.  */
-  sym->assoc->variable = (target->expr_type == EXPR_VARIABLE
-			  && !parentheses
-			  && !gfc_has_vector_subscript (target));
+  sym->assoc->variable = ((target->expr_type == EXPR_VARIABLE
+			   && !parentheses
+			   && !gfc_has_vector_subscript (target))
+			  || gfc_is_ptr_fcn (target));
 
   /* Finally resolve if this is an array or not.  */
   if (sym->attr.dimension && target->rank == 0)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index e6a4337..18589e1 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -1875,6 +1875,15 @@ gfc_get_symbol_decl (gfc_symbol * sym)
 	  && !(sym->attr.use_assoc && !intrinsic_array_parameter)))
     gfc_defer_symbol_init (sym);
 
+  /* Set the vptr of unlimited polymorphic pointer variables so that
+     they do not cause segfaults in select type, when the selector
+     is an intrinsic type.  Arrays are captured above.  */
+  if (sym->ts.type == BT_CLASS && UNLIMITED_POLY (sym)
+      && CLASS_DATA (sym)->attr.class_pointer
+      && !CLASS_DATA (sym)->attr.dimension && !sym->attr.dummy
+      && sym->attr.flavor == FL_VARIABLE && !sym->assoc)
+    gfc_defer_symbol_init (sym);
+
   if (sym->ts.type == BT_CHARACTER
       && sym->attr.allocatable
       && !sym->attr.dimension
@@ -1906,6 +1915,7 @@ gfc_get_symbol_decl (gfc_symbol * sym)
 	gcc_assert (!sym->value || sym->value->expr_type == EXPR_NULL);
     }
 
+
   gfc_finish_var_decl (decl, sym);
 
   if (sym->ts.type == BT_CHARACTER)
@@ -4652,6 +4662,29 @@ gfc_trans_deferred_vars (gfc_symbol * proc_sym, gfc_wrapped_block * block)
       if (sym->assoc)
 	continue;
 
+      /* Set the vptr of unlimited polymorphic pointer variables so that
+	 they do not cause segfaults in select type, when the selector
+	 is an intrinsic type.  */
+      if (sym->ts.type == BT_CLASS && UNLIMITED_POLY (sym)
+	  && sym->attr.flavor == FL_VARIABLE && !sym->assoc
+	  && !sym->attr.dummy && CLASS_DATA (sym)->attr.class_pointer)
+	{
+	  gfc_symbol *vtab;
+	  gfc_init_block (&tmpblock);
+	  vtab = gfc_find_vtab (&sym->ts);
+	  if (!vtab->backend_decl)
+	    {
+	      if (!vtab->attr.referenced)
+		gfc_set_sym_referenced (vtab);
+	      gfc_get_symbol_decl (vtab);
+	    }
+	  tmp = gfc_class_vptr_get (sym->backend_decl);
+	  gfc_add_modify (&tmpblock, tmp,
+			  gfc_build_addr_expr (TREE_TYPE (tmp),
+					       vtab->backend_decl));
+	  gfc_add_init_cleanup (block, gfc_finish_block (&tmpblock), NULL);
+	}
+
       if (sym->ts.type == BT_DERIVED
 	  && sym->ts.u.derived
 	  && sym->ts.u.derived->attr.pdt_type)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 45a984b..3c209bc 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -7348,11 +7348,14 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym,
 	}
 
       /* Character strings are passed as two parameters, a length and a
-	 pointer - except for Bind(c) which only passes the pointer.
+	 pointer - except for Bind(c) and c_ptrs which only passe the pointer.
 	 An unlimited polymorphic formal argument likewise does not
 	 need the length.  */
       if (parmse.string_length != NULL_TREE
 	  && !sym->attr.is_bind_c
+	  && !(fsym && fsym->ts.type == BT_DERIVED && fsym->ts.u.derived
+	       && fsym->ts.u.derived->intmod_sym_id == ISOCBINDING_PTR
+	       && fsym->ts.u.derived->from_intmod == INTMOD_ISO_C_BINDING )
 	  && !(fsym && UNLIMITED_POLY (fsym)))
 	vec_safe_push (stringargs, parmse.string_length);
 
diff --git a/gcc/fortran/trans-stmt.cc b/gcc/fortran/trans-stmt.cc
index dcabeca..7e76834 100644
--- a/gcc/fortran/trans-stmt.cc
+++ b/gcc/fortran/trans-stmt.cc
@@ -2139,11 +2139,14 @@ trans_associate_var (gfc_symbol *sym, gfc_wrapped_block *block)
 	  tree ctree = gfc_get_class_from_expr (se.expr);
 	  tmp = TREE_TYPE (sym->backend_decl);
 
-	  /* Coarray scalar component expressions can emerge from
-	     the front end as array elements of the _data field.  */
+	  /* F2018:19.5.1.6 "If a selector has the POINTER attribute,
+	     it shall be associated; the associate name is associated
+	     with the target of the pointer and does not have the
+	     POINTER attribute."  */
 	  if (sym->ts.type == BT_CLASS
-	      && e->ts.type == BT_CLASS && e->rank == 0
-	      && !GFC_CLASS_TYPE_P (TREE_TYPE (se.expr)) && ctree)
+	      && e->ts.type == BT_CLASS && e->rank == 0 && ctree
+	      && (!GFC_CLASS_TYPE_P (TREE_TYPE (se.expr))
+		  || CLASS_DATA (e)->attr.class_pointer))
 	    {
 	      tree stmp;
 	      tree dtmp;
@@ -2153,10 +2156,10 @@ trans_associate_var (gfc_symbol *sym, gfc_wrapped_block *block)
 	      ctree = gfc_create_var (dtmp, "class");
 
 	      stmp = gfc_class_data_get (se.expr);
-	      gcc_assert (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (stmp)));
-
-	      /* Set the fields of the target class variable.  */
-	      stmp = gfc_conv_descriptor_data_get (stmp);
+	      /* Coarray scalar component expressions can emerge from
+		 the front end as array elements of the _data field.  */
+	      if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (stmp)))
+		stmp = gfc_conv_descriptor_data_get (stmp);
 	      dtmp = gfc_class_data_get (ctree);
 	      stmp = fold_convert (TREE_TYPE (dtmp), stmp);
 	      gfc_add_modify (&se.pre, dtmp, stmp);
@@ -2170,6 +2173,7 @@ trans_associate_var (gfc_symbol *sym, gfc_wrapped_block *block)
 		  dtmp = gfc_class_len_get (ctree);
 		  stmp = fold_convert (TREE_TYPE (dtmp), stmp);
 		  gfc_add_modify (&se.pre, dtmp, stmp);
+		  need_len_assign = false;
 		}
 	      se.expr = ctree;
 	    }
diff --git a/gcc/function.cc b/gcc/function.cc
index 82102ed..6a79a82 100644
--- a/gcc/function.cc
+++ b/gcc/function.cc
@@ -578,8 +578,8 @@ public:
   tree type;
   /* The alignment (in bits) of the slot.  */
   unsigned int align;
-  /* Nonzero if this temporary is currently in use.  */
-  char in_use;
+  /* True if this temporary is currently in use.  */
+  bool in_use;
   /* Nesting level at which this slot is being used.  */
   int level;
   /* The offset of the slot from the frame_pointer, including extra space
@@ -674,7 +674,7 @@ make_slot_available (class temp_slot *temp)
 {
   cut_slot_from_list (temp, temp_slots_at_level (temp->level));
   insert_slot_to_list (temp, &avail_temp_slots);
-  temp->in_use = 0;
+  temp->in_use = false;
   temp->level = -1;
   n_temp_slots_in_use--;
 }
@@ -848,7 +848,7 @@ assign_stack_temp_for_type (machine_mode mode, poly_int64 size, tree type)
 	  if (known_ge (best_p->size - rounded_size, alignment))
 	    {
 	      p = ggc_alloc<temp_slot> ();
-	      p->in_use = 0;
+	      p->in_use = false;
 	      p->size = best_p->size - rounded_size;
 	      p->base_offset = best_p->base_offset + rounded_size;
 	      p->full_size = best_p->full_size - rounded_size;
@@ -918,7 +918,7 @@ assign_stack_temp_for_type (machine_mode mode, poly_int64 size, tree type)
     }
 
   p = selected;
-  p->in_use = 1;
+  p->in_use = true;
   p->type = type;
   p->level = temp_slot_level;
   n_temp_slots_in_use++;
@@ -1340,7 +1340,7 @@ has_hard_reg_initial_val (machine_mode mode, unsigned int regno)
   return NULL_RTX;
 }
 
-unsigned int
+void
 emit_initial_value_sets (void)
 {
   struct initial_value_struct *ivs = crtl->hard_reg_initial_vals;
@@ -1348,7 +1348,7 @@ emit_initial_value_sets (void)
   rtx_insn *seq;
 
   if (ivs == 0)
-    return 0;
+    return;
 
   start_sequence ();
   for (i = 0; i < ivs->num_entries; i++)
@@ -1357,7 +1357,6 @@ emit_initial_value_sets (void)
   end_sequence ();
 
   emit_insn_at_entry (seq);
-  return 0;
 }
 
 /* Return the hardreg-pseudoreg initial values pair entry I and
@@ -1535,7 +1534,7 @@ instantiate_virtual_regs_in_rtx (rtx *loc)
 /* A subroutine of instantiate_virtual_regs_in_insn.  Return true if X
    matches the predicate for insn CODE operand OPERAND.  */
 
-static int
+static bool
 safe_insn_predicate (int code, int operand, rtx x)
 {
   return code < 0 || insn_operand_matches ((enum insn_code) code, operand, x);
@@ -1947,7 +1946,7 @@ instantiate_decls (tree fndecl)
 /* Pass through the INSNS of function FNDECL and convert virtual register
    references to hard register references.  */
 
-static unsigned int
+static void
 instantiate_virtual_regs (void)
 {
   rtx_insn *insn;
@@ -2001,8 +2000,6 @@ instantiate_virtual_regs (void)
   /* Indicate that, from now on, assign_stack_local should use
      frame_pointer_rtx.  */
   virtuals_instantiated = 1;
-
-  return 0;
 }
 
 namespace {
@@ -2030,7 +2027,8 @@ public:
   /* opt_pass methods: */
   unsigned int execute (function *) final override
     {
-      return instantiate_virtual_regs ();
+      instantiate_virtual_regs ();
+      return 0;
     }
 
 }; // class pass_instantiate_virtual_regs
@@ -2044,12 +2042,12 @@ make_pass_instantiate_virtual_regs (gcc::context *ctxt)
 }
 
 
-/* Return 1 if EXP is an aggregate type (or a value with aggregate type).
+/* Return true if EXP is an aggregate type (or a value with aggregate type).
    This means a type for which function calls must pass an address to the
    function or get an address back from the function.
    EXP may be a type node or an expression (whose type is tested).  */
 
-int
+bool
 aggregate_value_p (const_tree exp, const_tree fntype)
 {
   const_tree type = (TYPE_P (exp)) ? exp : TREE_TYPE (exp);
@@ -2069,7 +2067,7 @@ aggregate_value_p (const_tree exp, const_tree fntype)
 	  else
 	    /* For internal functions, assume nothing needs to be
 	       returned in memory.  */
-	    return 0;
+	    return false;
 	}
 	break;
       case FUNCTION_DECL:
@@ -2087,10 +2085,10 @@ aggregate_value_p (const_tree exp, const_tree fntype)
       }
 
   if (VOID_TYPE_P (type))
-    return 0;
+    return false;
 
   if (error_operand_p (fntype))
-    return 0;
+    return false;
 
   /* If a record should be passed the same as its first (and only) member
      don't pass it as an aggregate.  */
@@ -2101,25 +2099,25 @@ aggregate_value_p (const_tree exp, const_tree fntype)
      reference, do so.  */
   if ((TREE_CODE (exp) == PARM_DECL || TREE_CODE (exp) == RESULT_DECL)
       && DECL_BY_REFERENCE (exp))
-    return 1;
+    return true;
 
   /* Function types that are TREE_ADDRESSABLE force return in memory.  */
   if (fntype && TREE_ADDRESSABLE (fntype))
-    return 1;
+    return true;
 
   /* Types that are TREE_ADDRESSABLE must be constructed in memory,
      and thus can't be returned in registers.  */
   if (TREE_ADDRESSABLE (type))
-    return 1;
+    return true;
 
   if (TYPE_EMPTY_P (type))
-    return 0;
+    return false;
 
   if (flag_pcc_struct_return && AGGREGATE_TYPE_P (type))
-    return 1;
+    return true;
 
   if (targetm.calls.return_in_memory (type, fntype))
-    return 1;
+    return true;
 
   /* Make sure we have suitable call-clobbered regs to return
      the value in; if not, we must return it in memory.  */
@@ -2128,7 +2126,7 @@ aggregate_value_p (const_tree exp, const_tree fntype)
   /* If we have something other than a REG (e.g. a PARALLEL), then assume
      it is OK.  */
   if (!REG_P (reg))
-    return 0;
+    return false;
 
   /* Use the default ABI if the type of the function isn't known.
      The scheme for handling interoperability between different ABIs
@@ -2141,9 +2139,9 @@ aggregate_value_p (const_tree exp, const_tree fntype)
   nregs = hard_regno_nregs (regno, TYPE_MODE (type));
   for (i = 0; i < nregs; i++)
     if (!fixed_regs[regno + i] && !abi.clobbers_full_reg_p (regno + i))
-      return 1;
+      return true;
 
-  return 0;
+  return false;
 }
 
 /* Return true if we should assign DECL a pseudo register; false if it
@@ -5733,26 +5731,26 @@ contains (const rtx_insn *insn, hash_table<insn_cache_hasher> *hash)
   return hash->find (const_cast<rtx_insn *> (insn)) != NULL;
 }
 
-int
+bool
 prologue_contains (const rtx_insn *insn)
 {
   return contains (insn, prologue_insn_hash);
 }
 
-int
+bool
 epilogue_contains (const rtx_insn *insn)
 {
   return contains (insn, epilogue_insn_hash);
 }
 
-int
+bool
 prologue_epilogue_contains (const rtx_insn *insn)
 {
   if (contains (insn, prologue_insn_hash))
-    return 1;
+    return true;
   if (contains (insn, epilogue_insn_hash))
-    return 1;
-  return 0;
+    return true;
+  return false;
 }
 
 void
@@ -6386,14 +6384,13 @@ current_function_name (void)
 }
 
 
-static unsigned int
+static void
 rest_of_handle_check_leaf_regs (void)
 {
 #ifdef LEAF_REGISTERS
   crtl->uses_only_leaf_regs
     = optimize > 0 && only_leaf_regs_used () && leaf_function_p ();
 #endif
-  return 0;
 }
 
 /* Insert a TYPE into the used types hash table of CFUN.  */
@@ -6518,7 +6515,8 @@ public:
   /* opt_pass methods: */
   unsigned int execute (function *) final override
     {
-      return rest_of_handle_check_leaf_regs ();
+      rest_of_handle_check_leaf_regs ();
+      return 0;
     }
 
 }; // class pass_leaf_regs
@@ -6531,7 +6529,7 @@ make_pass_leaf_regs (gcc::context *ctxt)
   return new pass_leaf_regs (ctxt);
 }
 
-static unsigned int
+static void
 rest_of_handle_thread_prologue_and_epilogue (function *fun)
 {
   /* prepare_shrink_wrap is sensitive to the block structure of the control
@@ -6563,8 +6561,6 @@ rest_of_handle_thread_prologue_and_epilogue (function *fun)
   /* The stack usage info is finalized during prologue expansion.  */
   if (flag_stack_usage_info || flag_callgraph_info)
     output_stack_usage ();
-
-  return 0;
 }
 
 /* Record a final call to CALLEE at LOCATION.  */
@@ -6626,7 +6622,8 @@ public:
   /* opt_pass methods: */
   unsigned int execute (function * fun) final override
     {
-      return rest_of_handle_thread_prologue_and_epilogue (fun);
+      rest_of_handle_thread_prologue_and_epilogue (fun);
+      return 0;
     }
 
 }; // class pass_thread_prologue_and_epilogue
diff --git a/gcc/function.h b/gcc/function.h
index d4ce8a7..e290ff5 100644
--- a/gcc/function.h
+++ b/gcc/function.h
@@ -657,11 +657,11 @@ extern rtx get_hard_reg_initial_val (machine_mode, unsigned int);
 extern rtx has_hard_reg_initial_val (machine_mode, unsigned int);
 
 /* Called from gimple_expand_cfg.  */
-extern unsigned int emit_initial_value_sets (void);
+extern void emit_initial_value_sets (void);
 
 extern bool initial_value_entry (int i, rtx *, rtx *);
 extern void instantiate_decl_rtl (rtx x);
-extern int aggregate_value_p (const_tree, const_tree);
+extern bool aggregate_value_p (const_tree, const_tree);
 extern bool use_register_for_decl (const_tree);
 extern gimple_seq gimplify_parameters (gimple_seq *);
 extern void locate_and_pad_parm (machine_mode, tree, int, int, int,
@@ -702,9 +702,9 @@ extern void clobber_return_register (void);
 extern void expand_function_end (void);
 extern rtx get_arg_pointer_save_area (void);
 extern void maybe_copy_prologue_epilogue_insn (rtx, rtx);
-extern int prologue_contains (const rtx_insn *);
-extern int epilogue_contains (const rtx_insn *);
-extern int prologue_epilogue_contains (const rtx_insn *);
+extern bool prologue_contains (const rtx_insn *);
+extern bool epilogue_contains (const rtx_insn *);
+extern bool prologue_epilogue_contains (const rtx_insn *);
 extern void record_prologue_seq (rtx_insn *);
 extern void record_epilogue_seq (rtx_insn *);
 extern void emit_return_into_block (bool simple_p, basic_block bb);
diff --git a/gcc/gcc-ar.cc b/gcc/gcc-ar.cc
index 5e5b63e..4e4c525 100644
--- a/gcc/gcc-ar.cc
+++ b/gcc/gcc-ar.cc
@@ -128,6 +128,9 @@ main (int ac, char **av)
   const char *exe_name;
 #if HAVE_LTO_PLUGIN > 0
   char *plugin;
+  const int j = 2; /* Two extra args, --plugin <plugin>  */
+#else
+  const int j = 0; /* No extra args.  */
 #endif
   int k, status, err;
   const char *err_msg;
@@ -206,25 +209,21 @@ main (int ac, char **av)
 	}
     }
 
+  /* Prepend - if necessary.  */
+  if (is_ar && av[1] && av[1][0] != '-')
+    av[1] = concat ("-", av[1], NULL);
+  
   /* Create new command line with plugin - if we have one, otherwise just
      copy the command through.  */
-  nargv = XCNEWVEC (const char *, ac + 4);
+  nargv = XCNEWVEC (const char *, ac + j + 1); /* +j plugin args +1 for NULL.  */
   nargv[0] = exe_name;
 #if HAVE_LTO_PLUGIN > 0
   nargv[1] = "--plugin";
   nargv[2] = plugin;
-  if (is_ar && av[1] && av[1][0] != '-')
-    av[1] = concat ("-", av[1], NULL);
-  for (k = 1; k < ac; k++)
-    nargv[2 + k] = av[k];
-  nargv[2 + k] = NULL;
-#else
-  if (is_ar && av[1] && av[1][0] != '-')
-    av[1] = concat ("-", av[1], NULL);
-  for (k = 1; k < ac; k++)
-    nargv[k] = av[k];
-  nargv[k] = NULL;
 #endif
+  for (k = 1; k < ac; k++)
+    nargv[j + k] = av[k];
+  nargv[j + k] = NULL;
 
   /* Run utility */
   /* ??? the const is misplaced in pex_one's argv? */
diff --git a/gcc/genemit.cc b/gcc/genemit.cc
index 33c9ec0..1ce0564 100644
--- a/gcc/genemit.cc
+++ b/gcc/genemit.cc
@@ -688,26 +688,27 @@ output_added_clobbers_hard_reg_p (void)
 {
   struct clobber_pat *clobber;
   struct clobber_ent *ent;
-  int clobber_p, used;
+  int clobber_p;
+  bool used;
 
-  printf ("\n\nint\nadded_clobbers_hard_reg_p (int insn_code_number)\n");
+  printf ("\n\nbool\nadded_clobbers_hard_reg_p (int insn_code_number)\n");
   printf ("{\n");
   printf ("  switch (insn_code_number)\n");
   printf ("    {\n");
 
   for (clobber_p = 0; clobber_p <= 1; clobber_p++)
     {
-      used = 0;
+      used = false;
       for (clobber = clobber_list; clobber; clobber = clobber->next)
 	if (clobber->has_hard_reg == clobber_p)
 	  for (ent = clobber->insns; ent; ent = ent->next)
 	    {
 	      printf ("    case %d:\n", ent->code_number);
-	      used++;
+	      used = true;
 	    }
 
       if (used)
-	printf ("      return %d;\n\n", clobber_p);
+	printf ("      return %s;\n\n", clobber_p ? "true" : "false");
     }
 
   printf ("    default:\n");
diff --git a/gcc/genopinit.cc b/gcc/genopinit.cc
index 0c1b685..6bd8858 100644
--- a/gcc/genopinit.cc
+++ b/gcc/genopinit.cc
@@ -376,7 +376,8 @@ main (int argc, const char **argv)
 
   fprintf (s_file,
 	   "/* Returns TRUE if the target supports any of the partial vector\n"
-	   "   optabs: while_ult_optab, len_load_optab or len_store_optab,\n"
+	   "   optabs: while_ult_optab, len_load_optab, len_store_optab,\n"
+	   "   len_maskload_optab or len_maskstore_optab,\n"
 	   "   for any mode.  */\n"
 	   "bool\npartial_vectors_supported_p (void)\n{\n");
   bool any_match = false;
@@ -386,7 +387,8 @@ main (int argc, const char **argv)
     {
 #define CMP_NAME(N) !strncmp (p->name, (N), strlen ((N)))
       if (CMP_NAME("while_ult") || CMP_NAME ("len_load")
-	  || CMP_NAME ("len_store"))
+	  || CMP_NAME ("len_store")|| CMP_NAME ("len_maskload")
+	  || CMP_NAME ("len_maskstore"))
 	{
 	  if (first)
 	    fprintf (s_file, " HAVE_%s", p->name);
diff --git a/gcc/genoutput.cc b/gcc/genoutput.cc
index 163e8df..3fbdde7 100644
--- a/gcc/genoutput.cc
+++ b/gcc/genoutput.cc
@@ -157,6 +157,7 @@ public:
   int n_alternatives;		/* Number of alternatives in each constraint */
   int operand_number;		/* Operand index in the big array.  */
   int output_format;		/* INSN_OUTPUT_FORMAT_*.  */
+  bool compact_syntax_p;
   struct operand_data operand[MAX_MAX_OPERANDS];
 };
 
@@ -700,12 +701,51 @@ process_template (class data *d, const char *template_code)
 	  if (sp != ep)
 	    message_at (d->loc, "trailing whitespace in output template");
 
-	  while (cp < sp)
+	  /* Check for any unexpanded iterators.  */
+	  if (bp[0] != '*' && d->compact_syntax_p)
 	    {
-	      putchar (*cp);
-	      cp++;
+	      const char *p = cp;
+	      const char *last_bracket = nullptr;
+	      while (p < sp)
+		{
+		  if (*p == '\\' && p + 1 < sp)
+		    {
+		      putchar (*p);
+		      putchar (*(p+1));
+		      p += 2;
+		      continue;
+		    }
+
+		  if (*p == '>' && last_bracket && *last_bracket == '<')
+		    {
+		      int len = p - last_bracket;
+		      fatal_at (d->loc, "unresolved iterator '%.*s' in '%s'",
+				len - 1, last_bracket + 1, cp);
+		    }
+		  else if (*p == '<' || *p == '>')
+		    last_bracket = p;
+
+		  putchar (*p);
+		  p += 1;
+		}
+
+	      if (last_bracket)
+		{
+		  char *nl = strchr (const_cast<char*> (cp), '\n');
+		  if (nl)
+		    *nl = '\0';
+		  fatal_at (d->loc, "unmatched angle brackets, likely an "
+			    "error in iterator syntax in %s", cp);
+		}
+	    }
+	  else
+	    {
+	      while (cp < sp)
+		putchar (*(cp++));
 	    }
 
+	  cp = sp;
+
 	  if (!found_star)
 	    puts ("\",");
 	  else if (*bp != '*')
@@ -881,6 +921,8 @@ gen_insn (md_rtx_info *info)
   else
     d->name = 0;
 
+  d->compact_syntax_p = compact_syntax.contains (insn);
+
   /* Build up the list in the same order as the insns are seen
      in the machine description.  */
   d->next = 0;
diff --git a/gcc/gensupport.cc b/gcc/gensupport.cc
index f9efc6e..e39e6da 100644
--- a/gcc/gensupport.cc
+++ b/gcc/gensupport.cc
@@ -18,6 +18,8 @@
    <http://www.gnu.org/licenses/>.  */
 
 #include "bconfig.h"
+#define INCLUDE_STRING
+#define INCLUDE_VECTOR
 #include "system.h"
 #include "coretypes.h"
 #include "tm.h"
@@ -33,6 +35,8 @@
 static rtx operand_data[MAX_OPERANDS];
 static rtx match_operand_entries_in_pattern[MAX_OPERANDS];
 static char used_operands_numbers[MAX_OPERANDS];
+/* List of entries which are part of the new syntax.  */
+hash_set<rtx> compact_syntax;
 
 
 /* In case some macros used by files we include need it, define this here.  */
@@ -545,6 +549,498 @@ gen_rewrite_sequence (rtvec vec)
   return new_vec;
 }
 
+/* The following is for handling the compact syntax for constraints and
+   attributes.
+
+   The normal syntax looks like this:
+
+       ...
+       (match_operand: 0 "s_register_operand" "r,I,k")
+       (match_operand: 2 "s_register_operand" "r,k,I")
+       ...
+       "@
+	<asm>
+	<asm>
+	<asm>"
+       ...
+       (set_attr "length" "4,8,8")
+
+   The compact syntax looks like this:
+
+       ...
+       (match_operand: 0 "s_register_operand")
+       (match_operand: 2 "s_register_operand")
+       ...
+       {@ [cons: 0, 2; attrs: length]
+	[r,r; 4] <asm>
+	[I,k; 8] <asm>
+	[k,I; 8] <asm>
+       }
+       ...
+       [<other attributes>]
+
+   This is the only place where this syntax needs to be handled.  Relevant
+   patterns are transformed from compact to the normal syntax before they are
+   queued, so none of the gen* programs need to know about this syntax at all.
+
+   Conversion process (convert_syntax):
+
+   0) Check that pattern actually uses new syntax (check for {@ ... }).
+
+   1) Get the "layout", i.e. the "[cons: 0 2; attrs: length]" from the above
+      example.  cons must come first; both are optional. Set up two vecs,
+      convec and attrvec, for holding the results of the transformation.
+
+   2) For each alternative: parse the list of constraints and/or attributes,
+      and enqueue them in the relevant lists in convec and attrvec.  By the end
+      of this process, convec[N].con and attrvec[N].con should contain regular
+      syntax constraint/attribute lists like "r,I,k".  Copy the asm to a string
+      as we go.
+
+   3) Search the rtx and write the constraint and attribute lists into the
+      correct places. Write the asm back into the template.  */
+
+/* Helper class for shuffling constraints/attributes in convert_syntax and
+   add_constraints/add_attributes.  This includes commas but not whitespace.  */
+
+class conlist {
+private:
+  std::string con;
+
+public:
+  std::string name;
+  int idx = -1;
+
+  conlist () = default;
+
+  /* [ns..ns + len) should be a string with the id of the rtx to match
+     i.e. if rtx is the relevant match_operand or match_scratch then
+     [ns..ns + len) should equal itoa (XINT (rtx, 0)), and if set_attr then
+     [ns..ns + len) should equal XSTR (rtx, 0).  */
+  conlist (const char *ns, unsigned int len, bool numeric)
+  {
+    /* Trim leading whitespaces.  */
+    while (ISBLANK (*ns))
+      {
+	ns++;
+	len--;
+      }
+
+    /* Trim trailing whitespace.  */
+    for (int i = len - 1; i >= 0; i--, len--)
+      if (!ISBLANK (ns[i]))
+	break;
+
+    /* Parse off any modifiers.  */
+    while (!ISALNUM (*ns))
+      {
+	con += *(ns++);
+	len--;
+      }
+
+    name.assign (ns, len);
+    if (numeric)
+      idx = std::stoi (name);
+  }
+
+  /* Adds a character to the end of the string.  */
+  void add (char c)
+  {
+    con += c;
+  }
+
+  /* Output the string in the form of a brand-new char *, then effectively
+     clear the internal string by resetting len to 0.  */
+  char *out ()
+  {
+    /* Final character is always a trailing comma, so strip it out.  */
+    char *q = xstrndup (con.c_str (), con.size () - 1);
+    con.clear ();
+    return q;
+  }
+};
+
+typedef std::vector<conlist> vec_conlist;
+
+/* Add constraints to an rtx.  This function is similar to remove_constraints.
+   Errors if adding the constraints would overwrite existing constraints.  */
+
+static void
+add_constraints (rtx part, file_location loc, vec_conlist &cons)
+{
+  const char *format_ptr;
+
+  if (part == NULL_RTX)
+    return;
+
+  /* If match_op or match_scr, check if we have the right one, and if so, copy
+     over the constraint list.  */
+  if (GET_CODE (part) == MATCH_OPERAND || GET_CODE (part) == MATCH_SCRATCH)
+    {
+      int field = GET_CODE (part) == MATCH_OPERAND ? 2 : 1;
+      unsigned id = XINT (part, 0);
+
+      if (id >= cons.size () || cons[id].idx == -1)
+	return;
+
+      if (XSTR (part, field)[0] != '\0')
+	{
+	  error_at (loc, "can't mix normal and compact constraint syntax");
+	  return;
+	}
+      XSTR (part, field) = cons[id].out ();
+      cons[id].idx = -1;
+    }
+
+  format_ptr = GET_RTX_FORMAT (GET_CODE (part));
+
+  /* Recursively search the rtx.  */
+  for (int i = 0; i < GET_RTX_LENGTH (GET_CODE (part)); i++)
+    switch (*format_ptr++)
+      {
+      case 'e':
+      case 'u':
+	add_constraints (XEXP (part, i), loc, cons);
+	break;
+      case 'E':
+	if (XVEC (part, i) != NULL)
+	  for (int j = 0; j < XVECLEN (part, i); j++)
+	    add_constraints (XVECEXP (part, i, j), loc, cons);
+	break;
+      default:
+	continue;
+      }
+}
+
+/* Add ATTRS to definition X's attribute list.  */
+
+static void
+add_attributes (rtx x, vec_conlist &attrs)
+{
+  unsigned int attr_index = GET_CODE (x) == DEFINE_INSN ? 4 : 3;
+  rtvec orig = XVEC (x, attr_index);
+  if (orig)
+    {
+      size_t n_curr = XVECLEN (x, attr_index);
+      rtvec copy = rtvec_alloc (n_curr + attrs.size ());
+
+      /* Create a shallow copy of existing entries.  */
+      memcpy (&copy->elem[attrs.size ()], &orig->elem[0],
+	      sizeof (rtx) * n_curr);
+      XVEC (x, attr_index) = copy;
+    }
+   else
+    XVEC (x, attr_index) = rtvec_alloc (attrs.size ());
+
+  /* Create the new elements.  */
+  for (unsigned i = 0; i < attrs.size (); i++)
+    {
+      rtx attr = rtx_alloc (SET_ATTR);
+      XSTR (attr, 0) = xstrdup (attrs[i].name.c_str ());
+      XSTR (attr, 1) = attrs[i].out ();
+      XVECEXP (x, attr_index, i) = attr;
+    }
+}
+
+/* Consumes spaces and tabs.  */
+
+static inline void
+skip_spaces (const char **str)
+{
+  while (ISBLANK (**str))
+    (*str)++;
+}
+
+/* Consumes the given character, if it's there.  */
+
+static inline bool
+expect_char (const char **str, char c)
+{
+  if (**str != c)
+    return false;
+  (*str)++;
+  return true;
+}
+
+/* Parses the section layout that follows a "{@" if using new syntax. Builds
+   a vector for a single section. E.g. if we have "attrs: length, arch]..."
+   then list will have two elements, the first for "length" and the second
+   for "arch".  */
+
+static void
+parse_section_layout (file_location loc, const char **templ, const char *label,
+		      vec_conlist &list, bool numeric)
+{
+  const char *name_start;
+  size_t label_len = strlen (label);
+  if (strncmp (label, *templ, label_len) == 0)
+    {
+      *templ += label_len;
+
+      /* Gather the names.  */
+      while (**templ != ';' && **templ != ']')
+	{
+	  skip_spaces (templ);
+	  name_start = *templ;
+	  int len = 0;
+	  char val = (*templ)[len];
+	  while (val != ',' && val != ';' && val != ']')
+	    {
+	      if (val == 0 || val == '\n')
+	        fatal_at (loc, "missing ']'");
+	      val = (*templ)[++len];
+	    }
+	  *templ += len;
+	  if (val == ',')
+	    (*templ)++;
+	  list.push_back (conlist (name_start, len, numeric));
+	}
+    }
+}
+
+/* Parse a section, a section is defined as a named space separated list, e.g.
+
+   foo: a, b, c
+
+   is a section named "foo" with entries a, b and c.  */
+
+static void
+parse_section (const char **templ, unsigned int n_elems, unsigned int alt_no,
+	       vec_conlist &list, file_location loc, const char *name)
+{
+  unsigned int i;
+
+  /* Go through the list, one character at a time, adding said character
+     to the correct string.  */
+  for (i = 0; **templ != ']' && **templ != ';'; (*templ)++)
+    if (!ISBLANK (**templ))
+      {
+	if (**templ == 0 || **templ == '\n')
+	  fatal_at (loc, "missing ']'");
+	list[i].add (**templ);
+	if (**templ == ',')
+	  {
+	    ++i;
+	    if (i == n_elems)
+	      fatal_at (loc, "too many %ss in alternative %d: expected %d",
+			name, alt_no, n_elems);
+	  }
+      }
+
+  if (i + 1 < n_elems)
+    fatal_at (loc, "too few %ss in alternative %d: expected %d, got %d",
+	      name, alt_no, n_elems, i);
+
+  list[i].add (',');
+}
+
+/* The compact syntax has more convience syntaxes.  As such we post process
+   the lines to get them back to something the normal syntax understands.  */
+
+static void
+preprocess_compact_syntax (file_location loc, int alt_no, std::string &line,
+			   std::string &last_line)
+{
+  /* Check if we're copying the last statement.  */
+  if (line.find ("^") == 0 && line.size () == 1)
+    {
+      if (last_line.empty ())
+	fatal_at (loc, "found instruction to copy previous line (^) in"
+		       "alternative %d but no previous line to copy", alt_no);
+      line = last_line;
+      return;
+    }
+
+  std::string result;
+  std::string buffer;
+  /* Check if we have << which means return c statement.  */
+  if (line.find ("<<") == 0)
+    {
+      result.append ("* return ");
+      const char *chunk = line.c_str () + 2;
+      skip_spaces (&chunk);
+      result.append (chunk);
+    }
+  else
+    result.append (line);
+
+  line = result;
+  return;
+}
+
+/* Converts an rtx from compact syntax to normal syntax if possible.  */
+
+static void
+convert_syntax (rtx x, file_location loc)
+{
+  int alt_no;
+  unsigned int templ_index;
+  const char *templ;
+  vec_conlist tconvec, convec, attrvec;
+
+  templ_index = 3;
+  gcc_assert (GET_CODE (x) == DEFINE_INSN);
+
+  templ = XTMPL (x, templ_index);
+
+  /* Templates with constraints start with "{@".  */
+  if (strncmp ("*{@", templ, 3))
+    return;
+
+  /* Get the layout for the template.  */
+  templ += 3;
+  skip_spaces (&templ);
+
+  if (!expect_char (&templ, '['))
+    fatal_at (loc, "expecing `[' to begin section list");
+
+  parse_section_layout (loc, &templ, "cons:", tconvec, true);
+
+  /* Check for any duplicate cons entries and sort based on i.  */
+  for (auto e : tconvec)
+    {
+      unsigned idx = e.idx;
+      if (idx >= convec.size ())
+	convec.resize (idx + 1);
+
+      if (convec[idx].idx >= 0)
+	fatal_at (loc, "duplicate cons number found: %d", idx);
+      convec[idx] = e;
+    }
+  tconvec.clear ();
+
+  if (*templ != ']')
+    {
+      if (*templ == ';')
+	skip_spaces (&(++templ));
+      parse_section_layout (loc, &templ, "attrs:", attrvec, false);
+    }
+
+  if (!expect_char (&templ, ']'))
+    fatal_at (loc, "expecting `]` to end section list - section list must have "
+		   "cons first, attrs second");
+
+  /* We will write the un-constrainified template into new_templ.  */
+  std::string new_templ;
+  new_templ.append ("@");
+
+  /* Skip to the first proper line.  */
+  skip_spaces (&templ);
+  if (*templ == 0)
+    fatal_at (loc, "'{@...}' blocks must have at least one alternative");
+  if (*templ != '\n')
+    fatal_at (loc, "unexpected character '%c' after ']'", *templ);
+  templ++;
+
+  alt_no = 0;
+  std::string last_line;
+
+  /* Process the alternatives.  */
+  while (*(templ - 1) != '\0')
+    {
+      /* Skip leading whitespace.  */
+      std::string buffer;
+      skip_spaces (&templ);
+
+      /* Check if we're at the end.  */
+      if (templ[0] == '}' && templ[1] == '\0')
+	break;
+
+      if (expect_char (&templ, '['))
+	{
+	  new_templ += '\n';
+	  new_templ.append (buffer);
+	  /* Parse the constraint list, then the attribute list.  */
+	  if (convec.size () > 0)
+	    parse_section (&templ, convec.size (), alt_no, convec, loc,
+			   "constraint");
+
+	  if (attrvec.size () > 0)
+	    {
+	      if (convec.size () > 0 && !expect_char (&templ, ';'))
+		fatal_at (loc, "expected `;' to separate constraints "
+			       "and attributes in alternative %d", alt_no);
+
+	      parse_section (&templ, attrvec.size (), alt_no,
+			     attrvec, loc, "attribute");
+	    }
+
+	  if (!expect_char (&templ, ']'))
+	    fatal_at (loc, "expected end of constraint/attribute list but "
+			   "missing an ending `]' in alternative %d", alt_no);
+	}
+      else if (templ[0] == '/' && templ[1] == '/')
+	{
+	  templ += 2;
+	  /* Glob till newline or end of string.  */
+	  while (*templ != '\n' || *templ != '\0')
+	    templ++;
+
+	  /* Skip any newlines or whitespaces needed.  */
+	  while (ISSPACE(*templ))
+	    templ++;
+	  continue;
+	}
+      else if (templ[0] == '/' && templ[1] == '*')
+	{
+	  templ += 2;
+	  /* Glob till newline or end of multiline comment.  */
+	  while (templ[0] != 0 && templ[0] != '*' && templ[1] != '/')
+	    templ++;
+
+	while (templ[0] != '*' || templ[1] != '/')
+	  {
+	    if (templ[0] == 0)
+	      fatal_at (loc, "unterminated '/*'");
+	    templ++;
+	  }
+	templ += 2;
+
+	  /* Skip any newlines or whitespaces needed.  */
+	  while (ISSPACE(*templ))
+	    templ++;
+	  continue;
+	}
+      else
+	fatal_at (loc, "expected constraint/attribute list at beginning of "
+		       "alternative %d but missing a starting `['", alt_no);
+
+      /* Skip whitespace between list and asm.  */
+      skip_spaces (&templ);
+
+      /* Copy asm to new template.  */
+      std::string line;
+      while (*templ != '\n' && *templ != '\0')
+	line += *templ++;
+
+      /* Apply any pre-processing needed to the line.  */
+      preprocess_compact_syntax (loc, alt_no, line, last_line);
+      new_templ.append (line);
+      last_line = line;
+
+      /* Normal "*..." syntax expects the closing quote to be on the final
+	 line of asm, whereas we allow the closing "}" to be on its own line.
+	 Postpone copying the '\n' until we know that there is another
+	 alternative in the list.  */
+      while (ISSPACE (*templ))
+	templ++;
+      ++alt_no;
+    }
+
+  /* Write the constraints and attributes into their proper places.  */
+  if (convec.size () > 0)
+    add_constraints (x, loc, convec);
+
+  if (attrvec.size () > 0)
+    add_attributes (x, attrvec);
+
+  /* Copy over the new un-constrainified template.  */
+  XTMPL (x, templ_index) = xstrdup (new_templ.c_str ());
+
+  /* Register for later checks during iterator expansions.  */
+  compact_syntax.add (x);
+}
+
 /* Process a top level rtx in some way, queuing as appropriate.  */
 
 static void
@@ -553,6 +1049,7 @@ process_rtx (rtx desc, file_location loc)
   switch (GET_CODE (desc))
     {
     case DEFINE_INSN:
+      convert_syntax (desc, loc);
       queue_pattern (desc, &define_insn_tail, loc);
       break;
 
@@ -631,6 +1128,7 @@ process_rtx (rtx desc, file_location loc)
 	attr = XVEC (desc, split_code + 1);
 	PUT_CODE (desc, DEFINE_INSN);
 	XVEC (desc, 4) = attr;
+	convert_syntax (desc, loc);
 
 	/* Queue them.  */
 	insn_elem = queue_pattern (desc, &define_insn_tail, loc);
diff --git a/gcc/gensupport.h b/gcc/gensupport.h
index a1edfbd..7925e22 100644
--- a/gcc/gensupport.h
+++ b/gcc/gensupport.h
@@ -20,6 +20,7 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_GENSUPPORT_H
 #define GCC_GENSUPPORT_H
 
+#include "hash-set.h"
 #include "read-md.h"
 
 struct obstack;
@@ -218,6 +219,8 @@ struct pattern_stats
   int num_operand_vars;
 };
 
+extern hash_set<rtx> compact_syntax;
+
 extern void get_pattern_stats (struct pattern_stats *ranges, rtvec vec);
 extern void compute_test_codes (rtx, file_location, char *);
 extern file_location get_file_location (rtx);
diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE
index 7022570..a028350 100644
--- a/gcc/go/gofrontend/MERGE
+++ b/gcc/go/gofrontend/MERGE
@@ -1,4 +1,4 @@
-737de90a63002d4872b19772a7116404ee5815b4
+195060166e6045408a2cb95e6aa88c6f0b98f20b
 
 The first line of this file holds the git revision number of the last
 merge done from the gofrontend repository.
diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc
index 4ac55af..2112de6 100644
--- a/gcc/go/gofrontend/expressions.cc
+++ b/gcc/go/gofrontend/expressions.cc
@@ -18307,6 +18307,16 @@ Slice_value_expression::do_traverse(Traverse* traverse)
   return TRAVERSE_CONTINUE;
 }
 
+// Determine type of a slice value.
+
+void
+Slice_value_expression::do_determine_type(const Type_context*)
+{
+  this->valmem_->determine_type_no_context();
+  this->len_->determine_type_no_context();
+  this->cap_->determine_type_no_context();
+}
+
 Expression*
 Slice_value_expression::do_copy()
 {
diff --git a/gcc/go/gofrontend/expressions.h b/gcc/go/gofrontend/expressions.h
index 3d7e787..bdb7ccd 100644
--- a/gcc/go/gofrontend/expressions.h
+++ b/gcc/go/gofrontend/expressions.h
@@ -4364,8 +4364,7 @@ class Slice_value_expression : public Expression
   { return this->type_; }
 
   void
-  do_determine_type(const Type_context*)
-  { }
+  do_determine_type(const Type_context*);
 
   Expression*
   do_copy();
@@ -4419,7 +4418,7 @@ class Slice_info_expression : public Expression
 
   void
   do_determine_type(const Type_context*)
-  { }
+  { this->slice_->determine_type_no_context(); }
 
   Expression*
   do_copy()
diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc
index 208bdf4..c911ae7 100644
--- a/gcc/internal-fn.cc
+++ b/gcc/internal-fn.cc
@@ -165,6 +165,7 @@ init_internal_fns ()
 #define mask_load_lanes_direct { -1, -1, false }
 #define gather_load_direct { 3, 1, false }
 #define len_load_direct { -1, -1, false }
+#define len_maskload_direct { -1, 3, false }
 #define mask_store_direct { 3, 2, false }
 #define store_lanes_direct { 0, 0, false }
 #define mask_store_lanes_direct { 0, 0, false }
@@ -172,6 +173,7 @@ init_internal_fns ()
 #define vec_cond_direct { 2, 0, false }
 #define scatter_store_direct { 3, 1, false }
 #define len_store_direct { 3, 3, false }
+#define len_maskstore_direct { 4, 3, false }
 #define vec_set_direct { 3, 3, false }
 #define unary_direct { 0, 0, true }
 #define unary_convert_direct { -1, 0, true }
@@ -2873,12 +2875,13 @@ expand_call_mem_ref (tree type, gcall *stmt, int index)
   return fold_build2 (MEM_REF, type, addr, build_int_cst (alias_ptr_type, 0));
 }
 
-/* Expand MASK_LOAD{,_LANES} or LEN_LOAD call STMT using optab OPTAB.  */
+/* Expand MASK_LOAD{,_LANES}, LEN_MASK_LOAD or LEN_LOAD call STMT using optab
+ * OPTAB.  */
 
 static void
 expand_partial_load_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
 {
-  class expand_operand ops[4];
+  class expand_operand ops[5];
   tree type, lhs, rhs, maskt, biast;
   rtx mem, target, mask, bias;
   insn_code icode;
@@ -2913,6 +2916,20 @@ expand_partial_load_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
       create_input_operand (&ops[3], bias, QImode);
       expand_insn (icode, 4, ops);
     }
+  else if (optab == len_maskload_optab)
+    {
+      create_convert_operand_from (&ops[2], mask, TYPE_MODE (TREE_TYPE (maskt)),
+				   TYPE_UNSIGNED (TREE_TYPE (maskt)));
+      maskt = gimple_call_arg (stmt, 3);
+      mask = expand_normal (maskt);
+      create_input_operand (&ops[3], mask, TYPE_MODE (TREE_TYPE (maskt)));
+      icode = convert_optab_handler (optab, TYPE_MODE (type),
+				     TYPE_MODE (TREE_TYPE (maskt)));
+      biast = gimple_call_arg (stmt, 4);
+      bias = expand_normal (biast);
+      create_input_operand (&ops[4], bias, QImode);
+      expand_insn (icode, 5, ops);
+    }
   else
     {
       create_input_operand (&ops[2], mask, TYPE_MODE (TREE_TYPE (maskt)));
@@ -2926,13 +2943,15 @@ expand_partial_load_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
 #define expand_mask_load_optab_fn expand_partial_load_optab_fn
 #define expand_mask_load_lanes_optab_fn expand_mask_load_optab_fn
 #define expand_len_load_optab_fn expand_partial_load_optab_fn
+#define expand_len_maskload_optab_fn expand_partial_load_optab_fn
 
-/* Expand MASK_STORE{,_LANES} or LEN_STORE call STMT using optab OPTAB.  */
+/* Expand MASK_STORE{,_LANES}, LEN_MASK_STORE or LEN_STORE call STMT using optab
+ * OPTAB.  */
 
 static void
 expand_partial_store_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
 {
-  class expand_operand ops[4];
+  class expand_operand ops[5];
   tree type, lhs, rhs, maskt, biast;
   rtx mem, reg, mask, bias;
   insn_code icode;
@@ -2965,6 +2984,19 @@ expand_partial_store_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
       create_input_operand (&ops[3], bias, QImode);
       expand_insn (icode, 4, ops);
     }
+  else if (optab == len_maskstore_optab)
+    {
+      create_convert_operand_from (&ops[2], mask, TYPE_MODE (TREE_TYPE (maskt)),
+				   TYPE_UNSIGNED (TREE_TYPE (maskt)));
+      maskt = gimple_call_arg (stmt, 3);
+      mask = expand_normal (maskt);
+      create_input_operand (&ops[3], mask, TYPE_MODE (TREE_TYPE (maskt)));
+      biast = gimple_call_arg (stmt, 4);
+      bias = expand_normal (biast);
+      create_input_operand (&ops[4], bias, QImode);
+      icode = convert_optab_handler (optab, TYPE_MODE (type), GET_MODE (mask));
+      expand_insn (icode, 5, ops);
+    }
   else
     {
       create_input_operand (&ops[2], mask, TYPE_MODE (TREE_TYPE (maskt)));
@@ -2975,6 +3007,7 @@ expand_partial_store_optab_fn (internal_fn, gcall *stmt, convert_optab optab)
 #define expand_mask_store_optab_fn expand_partial_store_optab_fn
 #define expand_mask_store_lanes_optab_fn expand_mask_store_optab_fn
 #define expand_len_store_optab_fn expand_partial_store_optab_fn
+#define expand_len_maskstore_optab_fn expand_partial_store_optab_fn
 
 /* Expand VCOND, VCONDU and VCONDEQ optab internal functions.
    The expansion of STMT happens based on OPTAB table associated.  */
@@ -3928,6 +3961,7 @@ multi_vector_optab_supported_p (convert_optab optab, tree_pair types,
 #define direct_mask_load_lanes_optab_supported_p multi_vector_optab_supported_p
 #define direct_gather_load_optab_supported_p convert_optab_supported_p
 #define direct_len_load_optab_supported_p direct_optab_supported_p
+#define direct_len_maskload_optab_supported_p convert_optab_supported_p
 #define direct_mask_store_optab_supported_p convert_optab_supported_p
 #define direct_store_lanes_optab_supported_p multi_vector_optab_supported_p
 #define direct_mask_store_lanes_optab_supported_p multi_vector_optab_supported_p
@@ -3935,6 +3969,7 @@ multi_vector_optab_supported_p (convert_optab optab, tree_pair types,
 #define direct_vec_cond_optab_supported_p convert_optab_supported_p
 #define direct_scatter_store_optab_supported_p convert_optab_supported_p
 #define direct_len_store_optab_supported_p direct_optab_supported_p
+#define direct_len_maskstore_optab_supported_p convert_optab_supported_p
 #define direct_while_optab_supported_p convert_optab_supported_p
 #define direct_fold_extract_optab_supported_p direct_optab_supported_p
 #define direct_fold_left_optab_supported_p direct_optab_supported_p
diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def
index 9da5f31..bc947c0 100644
--- a/gcc/internal-fn.def
+++ b/gcc/internal-fn.def
@@ -50,12 +50,14 @@ along with GCC; see the file COPYING3.  If not see
    - mask_load_lanes: currently just vec_mask_load_lanes
    - gather_load: used for {mask_,}gather_load
    - len_load: currently just len_load
+   - len_maskload: currently just len_maskload
 
    - mask_store: currently just maskstore
    - store_lanes: currently just vec_store_lanes
    - mask_store_lanes: currently just vec_mask_store_lanes
    - scatter_store: used for {mask_,}scatter_store
    - len_store: currently just len_store
+   - len_maskstore: currently just len_maskstore
 
    - unary: a normal unary optab, such as vec_reverse_<mode>
    - binary: a normal binary optab, such as vec_interleave_lo_<mode>
@@ -157,6 +159,7 @@ DEF_INTERNAL_OPTAB_FN (MASK_GATHER_LOAD, ECF_PURE,
 		       mask_gather_load, gather_load)
 
 DEF_INTERNAL_OPTAB_FN (LEN_LOAD, ECF_PURE, len_load, len_load)
+DEF_INTERNAL_OPTAB_FN (LEN_MASK_LOAD, ECF_PURE, len_maskload, len_maskload)
 
 DEF_INTERNAL_OPTAB_FN (SCATTER_STORE, 0, scatter_store, scatter_store)
 DEF_INTERNAL_OPTAB_FN (MASK_SCATTER_STORE, 0,
@@ -175,6 +178,7 @@ DEF_INTERNAL_OPTAB_FN (VCOND_MASK, 0, vcond_mask, vec_cond_mask)
 DEF_INTERNAL_OPTAB_FN (VEC_SET, 0, vec_set, vec_set)
 
 DEF_INTERNAL_OPTAB_FN (LEN_STORE, 0, len_store, len_store)
+DEF_INTERNAL_OPTAB_FN (LEN_MASK_STORE, 0, len_maskstore, len_maskstore)
 
 DEF_INTERNAL_OPTAB_FN (WHILE_ULT, ECF_CONST | ECF_NOTHROW, while_ult, while)
 DEF_INTERNAL_OPTAB_FN (SELECT_VL, ECF_CONST | ECF_NOTHROW, select_vl, binary)
diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc
index f0a314c..846dcf8 100644
--- a/gcc/ipa-cp.cc
+++ b/gcc/ipa-cp.cc
@@ -6779,3 +6779,79 @@ ipa_cp_cc_finalize (void)
   orig_overall_size = 0;
   ipcp_free_transformation_sum ();
 }
+
+/* Given PARAM which must be a parameter of function FNDECL described by THIS,
+   return its index in the DECL_ARGUMENTS chain, using a pre-computed
+   DECL_UID-sorted vector if available (which is pre-computed only if there are
+   many parameters).  Can return -1 if param is static chain not represented
+   among DECL_ARGUMENTS. */
+
+int
+ipcp_transformation::get_param_index (const_tree fndecl, const_tree param) const
+{
+  gcc_assert (TREE_CODE (param) == PARM_DECL);
+  if (m_uid_to_idx)
+    {
+      unsigned puid = DECL_UID (param);
+      const ipa_uid_to_idx_map_elt *res
+	= std::lower_bound (m_uid_to_idx->begin(), m_uid_to_idx->end (), puid,
+			    [] (const ipa_uid_to_idx_map_elt &elt, unsigned uid)
+			    {
+			      return elt.uid < uid;
+			    });
+      if (res == m_uid_to_idx->end ()
+	  || res->uid != puid)
+	{
+	  gcc_assert (DECL_STATIC_CHAIN (fndecl));
+	  return -1;
+	}
+      return res->index;
+    }
+
+  unsigned index = 0;
+  for (tree p = DECL_ARGUMENTS (fndecl); p; p = DECL_CHAIN (p), index++)
+    if (p == param)
+      return (int) index;
+
+  gcc_assert (DECL_STATIC_CHAIN (fndecl));
+  return -1;
+}
+
+/* Helper function to qsort a vector of ipa_uid_to_idx_map_elt elements
+   according to the uid.  */
+
+static int
+compare_uids (const void *a, const void *b)
+{
+  const ipa_uid_to_idx_map_elt *e1 = (const ipa_uid_to_idx_map_elt *) a;
+  const ipa_uid_to_idx_map_elt *e2 = (const ipa_uid_to_idx_map_elt *) b;
+  if (e1->uid < e2->uid)
+    return -1;
+  if (e1->uid > e2->uid)
+    return 1;
+  gcc_unreachable ();
+}
+
+/* Assuming THIS describes FNDECL and it has sufficiently many parameters to
+   justify the overhead, create a DECL_UID-sorted vector to speed up mapping
+   from parameters to their indices in DECL_ARGUMENTS chain.  */
+
+void
+ipcp_transformation::maybe_create_parm_idx_map (tree fndecl)
+{
+  int c = count_formal_params (fndecl);
+  if (c < 32)
+    return;
+
+  m_uid_to_idx = NULL;
+  vec_safe_reserve (m_uid_to_idx, c, true);
+  unsigned index = 0;
+  for (tree p = DECL_ARGUMENTS (fndecl); p; p = DECL_CHAIN (p), index++)
+    {
+      ipa_uid_to_idx_map_elt elt;
+      elt.uid = DECL_UID (p);
+      elt.index = index;
+      m_uid_to_idx->quick_push (elt);
+    }
+  m_uid_to_idx->qsort (compare_uids);
+}
diff --git a/gcc/ipa-fnsummary.cc b/gcc/ipa-fnsummary.cc
index a301396..a5f5a50 100644
--- a/gcc/ipa-fnsummary.cc
+++ b/gcc/ipa-fnsummary.cc
@@ -371,7 +371,8 @@ evaluate_conditions_for_known_args (struct cgraph_node *node,
 				    bool inline_p,
 				    ipa_auto_call_arg_values *avals,
 				    clause_t *ret_clause,
-				    clause_t *ret_nonspec_clause)
+				    clause_t *ret_nonspec_clause,
+				    ipa_call_summary *es)
 {
   clause_t clause = inline_p ? 0 : 1 << ipa_predicate::not_inlined_condition;
   clause_t nonspec_clause = 1 << ipa_predicate::not_inlined_condition;
@@ -386,6 +387,17 @@ evaluate_conditions_for_known_args (struct cgraph_node *node,
       int j;
       struct expr_eval_op *op;
 
+      if (c->code == ipa_predicate::not_sra_candidate)
+	{
+	  if (!inline_p
+	      || !es
+	      || (int)es->param.length () <= c->operand_num
+	      || !es->param[c->operand_num].points_to_possible_sra_candidate)
+	    clause |= 1 << (i + ipa_predicate::first_dynamic_condition);
+	  nonspec_clause |= 1 << (i + ipa_predicate::first_dynamic_condition);
+	  continue;
+	}
+
       if (c->agg_contents)
 	{
 	  if (c->code == ipa_predicate::changed
@@ -592,6 +604,7 @@ evaluate_properties_for_edge (struct cgraph_edge *e, bool inline_p,
   struct cgraph_node *callee = e->callee->ultimate_alias_target ();
   class ipa_fn_summary *info = ipa_fn_summaries->get (callee);
   class ipa_edge_args *args;
+  class ipa_call_summary *es = NULL;
 
   if (clause_ptr)
     *clause_ptr = inline_p ? 0 : 1 << ipa_predicate::not_inlined_condition;
@@ -603,8 +616,8 @@ evaluate_properties_for_edge (struct cgraph_edge *e, bool inline_p,
     {
       struct cgraph_node *caller;
       class ipa_node_params *caller_parms_info, *callee_pi = NULL;
-      class ipa_call_summary *es = ipa_call_summaries->get (e);
       int i, count = ipa_get_cs_argument_count (args);
+      es = ipa_call_summaries->get (e);
 
       if (count)
 	{
@@ -720,7 +733,7 @@ evaluate_properties_for_edge (struct cgraph_edge *e, bool inline_p,
     }
 
   evaluate_conditions_for_known_args (callee, inline_p, avals, clause_ptr,
-				      nonspec_clause_ptr);
+				      nonspec_clause_ptr, es);
 }
 
 
@@ -847,6 +860,7 @@ ipa_fn_summary_t::duplicate (cgraph_node *src,
 					  &possible_truths,
 					  /* We are going to specialize,
 					     so ignore nonspec truths.  */
+					  NULL,
 					  NULL);
 
       info->account_size_time (0, 0, true_pred, true_pred);
@@ -1035,6 +1049,9 @@ dump_ipa_call_summary (FILE *f, int indent, struct cgraph_node *node,
 	    if (es->param[i].points_to_local_or_readonly_memory)
 	      fprintf (f, "%*s op%i points to local or readonly memory\n",
 		       indent + 2, "", i);
+	    if (es->param[i].points_to_possible_sra_candidate)
+	      fprintf (f, "%*s op%i points to possible sra candidate\n",
+		       indent + 2, "", i);
 	  }
       if (!edge->inline_failed)
 	{
@@ -1291,6 +1308,35 @@ unmodified_parm_or_parm_agg_item (struct ipa_func_body_info *fbi,
 				 size_p, &aggpos->by_ref);
 }
 
+/* If stmt is simple load or store of value pointed to by a function parmaeter,
+   return its index.  */
+
+static int
+load_or_store_of_ptr_parameter (ipa_func_body_info *fbi, gimple *stmt)
+{
+  if (!optimize)
+    return -1;
+  gassign *assign = dyn_cast <gassign *> (stmt);
+  if (!assign)
+    return -1;
+  tree param;
+  if (gimple_assign_load_p (stmt))
+    param = gimple_assign_rhs1 (stmt);
+  else if (gimple_store_p (stmt))
+    param = gimple_assign_lhs (stmt);
+  else
+    return -1;
+  tree base = get_base_address (param);
+  if (TREE_CODE (base) != MEM_REF
+      || TREE_CODE (TREE_OPERAND (base, 0)) != SSA_NAME
+      || !SSA_NAME_IS_DEFAULT_DEF (TREE_OPERAND (base, 0)))
+    return -1;
+  tree p = SSA_NAME_VAR (TREE_OPERAND (base, 0));
+  if (TREE_CODE (p) != PARM_DECL)
+    return -1;
+  return ipa_get_param_decl_index (fbi->info, p);
+}
+
 /* See if statement might disappear after inlining.
    0 - means not eliminated
    1 - half of statements goes away
@@ -2585,6 +2631,23 @@ points_to_local_or_readonly_memory_p (tree t)
   return false;
 }
 
+/* Return true if T is a pointer pointing to memory location that is possible
+   sra candidate if all functions it is passed to are inlined.  */
+
+static bool
+points_to_possible_sra_candidate_p (tree t)
+{
+  if (TREE_CODE (t) != ADDR_EXPR)
+    return false;
+
+  t = get_base_address (TREE_OPERAND (t, 0));
+
+  /* Automatic variables are fine.  */
+  if (DECL_P (t)
+      && auto_var_in_fn_p (t, current_function_decl))
+    return true;
+  return false;
+}
 
 /* Analyze function body for NODE.
    EARLY indicates run from early optimization pipeline.  */
@@ -2797,6 +2860,9 @@ analyze_function_body (struct cgraph_node *node, bool early)
 		      es->param[i].points_to_local_or_readonly_memory
 			 = points_to_local_or_readonly_memory_p
 			     (gimple_call_arg (stmt, i));
+		      es->param[i].points_to_possible_sra_candidate
+			 = points_to_possible_sra_candidate_p
+			     (gimple_call_arg (stmt, i));
 		    }
 		}
 	      /* We cannot setup VLA parameters during inlining.  */
@@ -2847,7 +2913,6 @@ analyze_function_body (struct cgraph_node *node, bool early)
 	  if (this_time || this_size)
 	    {
 	      sreal final_time = (sreal)this_time * freq;
-
 	      prob = eliminated_by_inlining_prob (&fbi, stmt);
 	      if (prob == 1 && dump_file && (dump_flags & TDF_DETAILS))
 		fprintf (dump_file,
@@ -2856,6 +2921,12 @@ analyze_function_body (struct cgraph_node *node, bool early)
 		fprintf (dump_file, "\t\tWill be eliminated by inlining\n");
 
 	      ipa_predicate p = bb_predicate & will_be_nonconstant;
+	      int parm = load_or_store_of_ptr_parameter (&fbi, stmt);
+	      ipa_predicate sra_predicate = true;
+	      if (parm != -1)
+		sra_predicate &= add_condition (info, params_summary, parm,
+						ptr_type_node, NULL,
+						ipa_predicate::not_sra_candidate, NULL, 0);
 
 	      /* We can ignore statement when we proved it is never going
 		 to happen, but we cannot do that for call statements
@@ -2875,7 +2946,7 @@ analyze_function_body (struct cgraph_node *node, bool early)
 		  if (prob)
 		    {
 		      ipa_predicate ip
-			= bb_predicate & ipa_predicate::not_inlined ();
+			= bb_predicate & ipa_predicate::not_inlined () & sra_predicate;
 		      info->account_size_time (this_size * prob,
 					       (final_time * prob) / 2, ip,
 					       p);
@@ -2883,7 +2954,7 @@ analyze_function_body (struct cgraph_node *node, bool early)
 		  if (prob != 2)
 		    info->account_size_time (this_size * (2 - prob),
 					     (final_time * (2 - prob) / 2),
-					     bb_predicate,
+					     bb_predicate & sra_predicate,
 					     p);
 		}
 
@@ -3930,7 +4001,7 @@ estimate_ipcp_clone_size_and_time (struct cgraph_node *node,
   clause_t clause, nonspec_clause;
 
   evaluate_conditions_for_known_args (node, false, avals, &clause,
-				      &nonspec_clause);
+				      &nonspec_clause, NULL);
   ipa_call_context ctx (node, clause, nonspec_clause, vNULL, avals);
   ctx.estimate_size_and_time (estimates);
 }
@@ -4024,6 +4095,9 @@ remap_edge_params (struct cgraph_edge *inlined_edge,
 		  if (inlined_es
 			->param[id].points_to_local_or_readonly_memory)
 		    es->param[i].points_to_local_or_readonly_memory = true;
+		  if (inlined_es
+			->param[id].points_to_possible_sra_candidate)
+		    es->param[i].points_to_possible_sra_candidate = true;
 		}
 	      if (!es->param[i].points_to_local_or_readonly_memory
 		  && jfunc->type == IPA_JF_CONST
@@ -4420,8 +4494,11 @@ read_ipa_call_summary (class lto_input_block *ib, struct cgraph_edge *e,
       for (i = 0; i < length; i++)
 	{
 	  es->param[i].change_prob = streamer_read_uhwi (ib);
+	  bitpack_d bp = streamer_read_bitpack (ib);
 	  es->param[i].points_to_local_or_readonly_memory
-	    = streamer_read_uhwi (ib);
+	    = bp_unpack_value (&bp, 1);	
+	  es->param[i].points_to_possible_sra_candidate
+	    = bp_unpack_value (&bp, 1);	
 	}
     }
   else
@@ -4692,7 +4769,10 @@ write_ipa_call_summary (struct output_block *ob, struct cgraph_edge *e)
   for (i = 0; i < (int) es->param.length (); i++)
     {
       streamer_write_uhwi (ob, es->param[i].change_prob);
-      streamer_write_uhwi (ob, es->param[i].points_to_local_or_readonly_memory);
+      bp = bitpack_create (ob->main_stream);
+      bp_pack_value (&bp, es->param[i].points_to_local_or_readonly_memory, 1);
+      bp_pack_value (&bp, es->param[i].points_to_possible_sra_candidate, 1);
+      streamer_write_bitpack (&bp);
     }
 }
 
diff --git a/gcc/ipa-predicate.cc b/gcc/ipa-predicate.cc
index 2947869..09a253a 100644
--- a/gcc/ipa-predicate.cc
+++ b/gcc/ipa-predicate.cc
@@ -132,7 +132,7 @@ ipa_predicate::add_clause (conditions conditions, clause_t new_clause)
 	cc1 = &(*conditions)[c1 - ipa_predicate::first_dynamic_condition];
 	/* We have no way to represent !changed and !is_not_constant
 	   and thus there is no point for looking for them.  */
-	if (cc1->code == changed || cc1->code == is_not_constant)
+	if (cc1->code == changed || cc1->code == is_not_constant || cc1->code == not_sra_candidate)
 	  continue;
 	for (c2 = c1 + 1; c2 < num_conditions; c2++)
 	  if (new_clause & (1 << c2))
@@ -142,6 +142,7 @@ ipa_predicate::add_clause (conditions conditions, clause_t new_clause)
 	      if (cc1->operand_num == cc2->operand_num
 		  && vrp_operand_equal_p (cc1->val, cc2->val)
 		  && cc2->code != is_not_constant
+		  && cc2->code != not_sra_candidate
 		  && cc2->code != changed
 		  && expr_eval_ops_equal_p (cc1->param_ops, cc2->param_ops)
 		  && cc2->agg_contents == cc1->agg_contents
@@ -416,6 +417,11 @@ dump_condition (FILE *f, conditions conditions, int cond)
 	  fprintf (f, " changed");
 	  return;
 	}
+      if (c->code == ipa_predicate::not_sra_candidate)
+	{
+	  fprintf (f, " not sra candidate");
+	  return;
+	}
       fprintf (f, " %s ", op_symbol_code (c->code));
       print_generic_expr (f, c->val);
     }
diff --git a/gcc/ipa-predicate.h b/gcc/ipa-predicate.h
index 2882bf8e..5abf253 100644
--- a/gcc/ipa-predicate.h
+++ b/gcc/ipa-predicate.h
@@ -78,16 +78,20 @@ struct inline_param_summary
      Value 0 is reserved for compile time invariants. */
   short change_prob;
   unsigned points_to_local_or_readonly_memory : 1;
+  unsigned points_to_possible_sra_candidate : 1;
   bool equal_to (const inline_param_summary &other) const
   {
     return change_prob == other.change_prob
 	   && points_to_local_or_readonly_memory
-	      == other.points_to_local_or_readonly_memory;
+	      == other.points_to_local_or_readonly_memory
+	   && points_to_possible_sra_candidate
+	      == other.points_to_possible_sra_candidate;
   }
   bool useless_p (void) const
   {
     return change_prob == REG_BR_PROB_BASE
-	   && !points_to_local_or_readonly_memory;
+	   && !points_to_local_or_readonly_memory
+	   && !points_to_possible_sra_candidate;
   }
 };
 
@@ -135,6 +139,9 @@ public:
      percentage of executions even when they are not compile time constants.  */
   static const tree_code changed = IDENTIFIER_NODE;
 
+  /* Special condition code we use to check that the parameter is likely SRA
+     candidate.  */
+  static const tree_code not_sra_candidate = TREE_LIST;
 
 
   /* Initialize predicate either to true of false depending on P.  */
diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc
index eea8117..704fe01 100644
--- a/gcc/ipa-prop.cc
+++ b/gcc/ipa-prop.cc
@@ -5778,16 +5778,9 @@ ipcp_get_parm_bits (tree parm, tree *value, widest_int *mask)
   if (!ts || vec_safe_length (ts->bits) == 0)
     return false;
 
-  int i = 0;
-  for (tree p = DECL_ARGUMENTS (current_function_decl);
-       p != parm; p = DECL_CHAIN (p))
-    {
-      i++;
-      /* Ignore static chain.  */
-      if (!p)
-	return false;
-    }
-
+  int i = ts->get_param_index (current_function_decl, parm);
+  if (i < 0)
+    return false;
   clone_info *cinfo = clone_info::get (cnode);
   if (cinfo && cinfo->param_adjustments)
     {
@@ -5804,16 +5797,12 @@ ipcp_get_parm_bits (tree parm, tree *value, widest_int *mask)
   return true;
 }
 
-
-/* Update bits info of formal parameters as described in
-   ipcp_transformation.  */
+/* Update bits info of formal parameters of NODE as described in TS.  */
 
 static void
-ipcp_update_bits (struct cgraph_node *node)
+ipcp_update_bits (struct cgraph_node *node, ipcp_transformation *ts)
 {
-  ipcp_transformation *ts = ipcp_get_transformation_summary (node);
-
-  if (!ts || vec_safe_length (ts->bits) == 0)
+  if (vec_safe_is_empty (ts->bits))
     return;
   vec<ipa_bits *, va_gc> &bits = *ts->bits;
   unsigned count = bits.length ();
@@ -5915,14 +5904,12 @@ ipcp_update_bits (struct cgraph_node *node)
     }
 }
 
-/* Update value range of formal parameters as described in
-   ipcp_transformation.  */
+/* Update value range of formal parameters of NODE as described in TS.  */
 
 static void
-ipcp_update_vr (struct cgraph_node *node)
+ipcp_update_vr (struct cgraph_node *node, ipcp_transformation *ts)
 {
-  ipcp_transformation *ts = ipcp_get_transformation_summary (node);
-  if (!ts || vec_safe_length (ts->m_vr) == 0)
+  if (vec_safe_is_empty (ts->m_vr))
     return;
   const vec<ipa_vr, va_gc> &vr = *ts->m_vr;
   unsigned count = vr.length ();
@@ -5998,10 +5985,17 @@ ipcp_transform_function (struct cgraph_node *node)
     fprintf (dump_file, "Modification phase of node %s\n",
 	     node->dump_name ());
 
-  ipcp_update_bits (node);
-  ipcp_update_vr (node);
   ipcp_transformation *ts = ipcp_get_transformation_summary (node);
-  if (!ts || vec_safe_is_empty (ts->m_agg_values))
+  if (!ts
+      || (vec_safe_is_empty (ts->m_agg_values)
+	  && vec_safe_is_empty (ts->bits)
+	  && vec_safe_is_empty (ts->m_vr)))
+    return 0;
+
+  ts->maybe_create_parm_idx_map (cfun->decl);
+  ipcp_update_bits (node, ts);
+  ipcp_update_vr (node, ts);
+  if (vec_safe_is_empty (ts->m_agg_values))
       return 0;
   param_count = count_formal_params (node->decl);
   if (param_count == 0)
diff --git a/gcc/ipa-prop.h b/gcc/ipa-prop.h
index 3a591a8..9b7fee4 100644
--- a/gcc/ipa-prop.h
+++ b/gcc/ipa-prop.h
@@ -921,20 +921,24 @@ ipa_is_param_used_by_polymorphic_call (class ipa_node_params *info, int i)
   return (*info->descriptors)[i].used_by_polymorphic_call;
 }
 
+/* GTY-marked structure used to map DECL_UIDs of APRAMs to their indices in
+   their DECL_ARGUMENTs chain.  */
+struct GTY(()) ipa_uid_to_idx_map_elt
+{
+  /* DECL_UID of the PARAM.  */
+  unsigned uid;
+  /* Its index in the DECL_ARGUMETs chain.  */
+  unsigned index;
+};
+
 /* Structure holding information for the transformation phase of IPA-CP.  */
 
 struct GTY(()) ipcp_transformation
 {
-  /* Known aggregate values.  */
-  vec<ipa_argagg_value, va_gc>  *m_agg_values;
-  /* Known bits information.  */
-  vec<ipa_bits *, va_gc> *bits;
-  /* Value range information.  */
-  vec<ipa_vr, va_gc> *m_vr;
-
   /* Default constructor.  */
   ipcp_transformation ()
-  : m_agg_values (NULL), bits (NULL), m_vr (NULL)
+    : m_agg_values (nullptr), bits (nullptr), m_vr (nullptr),
+    m_uid_to_idx (nullptr)
   { }
 
   /* Default destructor.  */
@@ -944,6 +948,30 @@ struct GTY(()) ipcp_transformation
     vec_free (bits);
     vec_free (m_vr);
   }
+
+  /* Given PARAM which must be a parameter of function FNDECL described by
+     THIS, return its index in the DECL_ARGUMENTS chain, using a pre-computed
+     DECL_UID-sorted vector if available (which is pre-computed only if there
+     are many parameters).  Can return -1 if param is static chain not
+     represented among DECL_ARGUMENTS. */
+
+  int get_param_index (const_tree fndecl, const_tree param) const;
+
+  /* Assuming THIS describes FNDECL and it has sufficiently many parameters to
+     justify the overhead, create a DECL_UID-sorted vector to speed up mapping
+     from parameters to their indices in DECL_ARGUMENTS chain.  */
+
+  void maybe_create_parm_idx_map (tree fndecl);
+
+  /* Known aggregate values.  */
+  vec<ipa_argagg_value, va_gc>  *m_agg_values;
+  /* Known bits information.  */
+  vec<ipa_bits *, va_gc> *bits;
+  /* Value range information.  */
+  vec<ipa_vr, va_gc> *m_vr;
+  /* If there are many parameters, this is a vector sorted by their DECL_UIDs
+     to map them to their indices in the DECL_ARGUMENT chain.  */
+  vec<ipa_uid_to_idx_map_elt, va_gc> *m_uid_to_idx;
 };
 
 inline
diff --git a/gcc/ipa-sra.cc b/gcc/ipa-sra.cc
index 3fee8fb..21d281a 100644
--- a/gcc/ipa-sra.cc
+++ b/gcc/ipa-sra.cc
@@ -3074,6 +3074,8 @@ struct caller_issues
   cgraph_node *candidate;
   /* There is a thunk among callers.  */
   bool thunk;
+  /* Set if there is at least one caller that is OK.  */
+  bool there_is_one;
   /* Call site with no available information.  */
   bool unknown_callsite;
   /* Call from outside the candidate's comdat group.  */
@@ -3116,6 +3118,8 @@ check_for_caller_issues (struct cgraph_node *node, void *data)
 
       if (csum->m_bit_aligned_arg)
 	issues->bit_aligned_aggregate_argument = true;
+
+      issues->there_is_one = true;
     }
   return false;
 }
@@ -3170,6 +3174,13 @@ check_all_callers_for_issues (cgraph_node *node)
       for (unsigned i = 0; i < param_count; i++)
 	(*ifs->m_parameters)[i].split_candidate = false;
     }
+  if (!issues.there_is_one)
+    {
+      if (dump_file && (dump_flags & TDF_DETAILS))
+	fprintf (dump_file, "There is no call to %s that we can modify.  "
+		 "Disabling all modifications.\n", node->dump_name ());
+      return true;
+    }
   return false;
 }
 
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 41e38a85..70ea865 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,13 @@
+2023-06-18  Gaius Mulley  <gaiusmod2@gmail.com>
+
+	PR modula2/110284
+	* Make-lang.in (m2_OBJS): Assign $(GM2_C_OBJS).
+	(GM2_C_OBJS): Remove m2/stor-layout.o.
+	(m2/stor-layout.o): Remove rule.
+	* gm2-gcc/gcc-consolidation.h (rtl.h): Remove include.
+	(df.h): Remove include.
+	(except.h): Remove include.
+
 2023-06-15  Marek Polacek  <polacek@redhat.com>
 
 	* Make-lang.in: New var, GM2_PICFLAGS.  Use it.
diff --git a/gcc/m2/Make-lang.in b/gcc/m2/Make-lang.in
index 15da74a..f6f7b48 100644
--- a/gcc/m2/Make-lang.in
+++ b/gcc/m2/Make-lang.in
@@ -490,7 +490,6 @@ SO=-O0 -g -fPIC
 # Language-specific object files for the gm2 compiler.
 
 GM2_C_OBJS        = m2/gm2-lang.o \
-                    m2/stor-layout.o \
                     m2/m2pp.o \
                     m2/gm2-gcc/m2assert.o \
                     m2/gm2-gcc/m2block.o \
@@ -516,7 +515,7 @@ GM2_LIBS_BOOT     = m2/gm2-compiler-boot/gm2.a \
                     m2/gm2-libs-boot/libgm2.a \
                     $(GM2-BOOT-O)
 
-$(GM2_C_OBJS) : | $(generated_files)
+m2_OBJS = $(GM2_C_OBJS)
 
 cc1gm2$(exeext): m2/stage1/cc1gm2$(exeext) $(m2.prev)
 	cp -p $< $@
@@ -576,10 +575,6 @@ m2/gm2-lang.o: $(srcdir)/m2/gm2-lang.cc gt-m2-gm2-lang.h $(GCC_HEADER_DEPENDENCI
 	    -DLIBSUBDIR=\"$(libsubdir)\" \
             $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION)
 
-m2/stor-layout.o: $(srcdir)/stor-layout.cc $(GCC_HEADER_DEPENDENCIES_FOR_M2)
-	$(COMPILER) -c -DSET_WORD_SIZE=INT_TYPE_SIZE $(ALL_COMPILERFLAGS) \
-            $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION)
-
 m2/m2pp.o : $(srcdir)/m2/m2pp.cc $(GCC_HEADER_DEPENDENCIES_FOR_M2)
 	$(COMPILER) -c -g -DGM2 $(ALL_COMPILERFLAGS) \
             $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION)
diff --git a/gcc/m2/gm2-gcc/gcc-consolidation.h b/gcc/m2/gm2-gcc/gcc-consolidation.h
index 6abb182..3892bdd 100644
--- a/gcc/m2/gm2-gcc/gcc-consolidation.h
+++ b/gcc/m2/gm2-gcc/gcc-consolidation.h
@@ -25,10 +25,8 @@ along with GNU Modula-2; see the file COPYING3.  If not see
 #include "realmpfr.h"
 #include "backend.h"
 #include "stringpool.h"
-#include "rtl.h"
 #include "tree.h"
 #include "predict.h"
-#include "df.h"
 #include "tm.h"
 #include "hash-set.h"
 #include "machmode.h"
@@ -69,7 +67,6 @@ along with GNU Modula-2; see the file COPYING3.  If not see
 #include "cfganal.h"
 #include "predict.h"
 #include "basic-block.h"
-#include "df.h"
 #include "tree-ssa-alias.h"
 #include "internal-fn.h"
 #include "gimple-expr.h"
@@ -80,7 +77,6 @@ along with GNU Modula-2; see the file COPYING3.  If not see
 #include "stringpool.h"
 #include "tree-nested.h"
 #include "print-tree.h"
-#include "except.h"
 #include "toplev.h"
 #include "convert.h"
 #include "tree-dump.h"
diff --git a/gcc/optabs-query.cc b/gcc/optabs-query.cc
index 276f840..2fdd0d3 100644
--- a/gcc/optabs-query.cc
+++ b/gcc/optabs-query.cc
@@ -558,72 +558,6 @@ can_mult_highpart_p (machine_mode mode, bool uns_p)
   return 0;
 }
 
-/* Return true if target supports vector masked load/store for mode.  */
-
-bool
-can_vec_mask_load_store_p (machine_mode mode,
-			   machine_mode mask_mode,
-			   bool is_load)
-{
-  optab op = is_load ? maskload_optab : maskstore_optab;
-  machine_mode vmode;
-
-  /* If mode is vector mode, check it directly.  */
-  if (VECTOR_MODE_P (mode))
-    return convert_optab_handler (op, mode, mask_mode) != CODE_FOR_nothing;
-
-  /* Otherwise, return true if there is some vector mode with
-     the mask load/store supported.  */
-
-  /* See if there is any chance the mask load or store might be
-     vectorized.  If not, punt.  */
-  scalar_mode smode;
-  if (!is_a <scalar_mode> (mode, &smode))
-    return false;
-
-  vmode = targetm.vectorize.preferred_simd_mode (smode);
-  if (VECTOR_MODE_P (vmode)
-      && targetm.vectorize.get_mask_mode (vmode).exists (&mask_mode)
-      && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
-    return true;
-
-  auto_vector_modes vector_modes;
-  targetm.vectorize.autovectorize_vector_modes (&vector_modes, true);
-  for (machine_mode base_mode : vector_modes)
-    if (related_vector_mode (base_mode, smode).exists (&vmode)
-	&& targetm.vectorize.get_mask_mode (vmode).exists (&mask_mode)
-	&& convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
-      return true;
-  return false;
-}
-
-/* If target supports vector load/store with length for vector mode MODE,
-   return the corresponding vector mode, otherwise return opt_machine_mode ().
-   There are two flavors for vector load/store with length, one is to measure
-   length with bytes, the other is to measure length with lanes.
-   As len_{load,store} optabs point out, for the flavor with bytes, we use
-   VnQI to wrap the other supportable same size vector modes.  */
-
-opt_machine_mode
-get_len_load_store_mode (machine_mode mode, bool is_load)
-{
-  optab op = is_load ? len_load_optab : len_store_optab;
-  gcc_assert (VECTOR_MODE_P (mode));
-
-  /* Check if length in lanes supported for this mode directly.  */
-  if (direct_optab_handler (op, mode))
-    return mode;
-
-  /* Check if length in bytes supported for same vector size VnQI.  */
-  machine_mode vmode;
-  poly_uint64 nunits = GET_MODE_SIZE (mode);
-  if (related_vector_mode (mode, QImode, nunits).exists (&vmode)
-      && direct_optab_handler (op, vmode))
-    return vmode;
-
-  return opt_machine_mode ();
-}
-
 /* Return true if there is a compare_and_swap pattern.  */
 
 bool
diff --git a/gcc/optabs-query.h b/gcc/optabs-query.h
index b266d2f..043e979 100644
--- a/gcc/optabs-query.h
+++ b/gcc/optabs-query.h
@@ -187,8 +187,6 @@ enum insn_code find_widening_optab_handler_and_mode (optab, machine_mode,
 						     machine_mode,
 						     machine_mode *);
 int can_mult_highpart_p (machine_mode, bool);
-bool can_vec_mask_load_store_p (machine_mode, machine_mode, bool);
-opt_machine_mode get_len_load_store_mode (machine_mode, bool);
 bool can_compare_and_swap_p (machine_mode, bool);
 bool can_atomic_exchange_p (machine_mode, bool);
 bool can_atomic_load_p (machine_mode);
diff --git a/gcc/optabs-tree.cc b/gcc/optabs-tree.cc
index 33ca529..77bf745 100644
--- a/gcc/optabs-tree.cc
+++ b/gcc/optabs-tree.cc
@@ -543,3 +543,68 @@ target_supports_op_p (tree type, enum tree_code code,
 	  && optab_handler (ot, TYPE_MODE (type)) != CODE_FOR_nothing);
 }
 
+/* Return true if target supports vector masked load/store for mode.  */
+
+bool
+can_vec_mask_load_store_p (machine_mode mode,
+			   machine_mode mask_mode,
+			   bool is_load)
+{
+  optab op = is_load ? maskload_optab : maskstore_optab;
+  machine_mode vmode;
+
+  /* If mode is vector mode, check it directly.  */
+  if (VECTOR_MODE_P (mode))
+    return convert_optab_handler (op, mode, mask_mode) != CODE_FOR_nothing;
+
+  /* Otherwise, return true if there is some vector mode with
+     the mask load/store supported.  */
+
+  /* See if there is any chance the mask load or store might be
+     vectorized.  If not, punt.  */
+  scalar_mode smode;
+  if (!is_a <scalar_mode> (mode, &smode))
+    return false;
+
+  vmode = targetm.vectorize.preferred_simd_mode (smode);
+  if (VECTOR_MODE_P (vmode)
+      && targetm.vectorize.get_mask_mode (vmode).exists (&mask_mode)
+      && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
+    return true;
+
+  auto_vector_modes vector_modes;
+  targetm.vectorize.autovectorize_vector_modes (&vector_modes, true);
+  for (machine_mode base_mode : vector_modes)
+    if (related_vector_mode (base_mode, smode).exists (&vmode)
+	&& targetm.vectorize.get_mask_mode (vmode).exists (&mask_mode)
+	&& convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
+      return true;
+  return false;
+}
+
+/* If target supports vector load/store with length for vector mode MODE,
+   return the corresponding vector mode, otherwise return opt_machine_mode ().
+   There are two flavors for vector load/store with length, one is to measure
+   length with bytes, the other is to measure length with lanes.
+   As len_{load,store} optabs point out, for the flavor with bytes, we use
+   VnQI to wrap the other supportable same size vector modes.  */
+
+opt_machine_mode
+get_len_load_store_mode (machine_mode mode, bool is_load)
+{
+  optab op = is_load ? len_load_optab : len_store_optab;
+  gcc_assert (VECTOR_MODE_P (mode));
+
+  /* Check if length in lanes supported for this mode directly.  */
+  if (direct_optab_handler (op, mode))
+    return mode;
+
+  /* Check if length in bytes supported for same vector size VnQI.  */
+  machine_mode vmode;
+  poly_uint64 nunits = GET_MODE_SIZE (mode);
+  if (related_vector_mode (mode, QImode, nunits).exists (&vmode)
+      && direct_optab_handler (op, vmode))
+    return vmode;
+
+  return opt_machine_mode ();
+}
diff --git a/gcc/optabs-tree.h b/gcc/optabs-tree.h
index 526bfe8..a3f79b6 100644
--- a/gcc/optabs-tree.h
+++ b/gcc/optabs-tree.h
@@ -47,5 +47,7 @@ bool expand_vec_cond_expr_p (tree, tree, enum tree_code);
 void init_tree_optimization_optabs (tree);
 bool target_supports_op_p (tree, enum tree_code,
 			   enum optab_subtype = optab_default);
+bool can_vec_mask_load_store_p (machine_mode, machine_mode, bool);
+opt_machine_mode get_len_load_store_mode (machine_mode, bool);
 
 #endif
diff --git a/gcc/optabs.def b/gcc/optabs.def
index 22b31be..9533eb1 100644
--- a/gcc/optabs.def
+++ b/gcc/optabs.def
@@ -91,6 +91,8 @@ OPTAB_CD(vec_cmpu_optab, "vec_cmpu$a$b")
 OPTAB_CD(vec_cmpeq_optab, "vec_cmpeq$a$b")
 OPTAB_CD(maskload_optab, "maskload$a$b")
 OPTAB_CD(maskstore_optab, "maskstore$a$b")
+OPTAB_CD(len_maskload_optab, "len_maskload$a$b")
+OPTAB_CD(len_maskstore_optab, "len_maskstore$a$b")
 OPTAB_CD(gather_load_optab, "gather_load$a$b")
 OPTAB_CD(mask_gather_load_optab, "mask_gather_load$a$b")
 OPTAB_CD(scatter_store_optab, "scatter_store$a$b")
diff --git a/gcc/passes.def b/gcc/passes.def
index c9a8f19..faa5208 100644
--- a/gcc/passes.def
+++ b/gcc/passes.def
@@ -88,6 +88,8 @@ along with GCC; see the file COPYING3.  If not see
 	  /* pass_build_ealias is a dummy pass that ensures that we
 	     execute TODO_rebuild_alias at this point.  */
 	  NEXT_PASS (pass_build_ealias);
+	  /* Do phiprop before FRE so we optimize std::min and std::max well.  */
+	  NEXT_PASS (pass_phiprop);
 	  NEXT_PASS (pass_fre, true /* may_iterate */);
 	  NEXT_PASS (pass_early_vrp);
 	  NEXT_PASS (pass_merge_phi);
diff --git a/gcc/recog.cc b/gcc/recog.cc
index fd09145..3743208 100644
--- a/gcc/recog.cc
+++ b/gcc/recog.cc
@@ -133,7 +133,7 @@ asm_labels_ok (rtx body)
 /* Check that X is an insn-body for an `asm' with operands
    and that the operands mentioned in it are legitimate.  */
 
-int
+bool
 check_asm_operands (rtx x)
 {
   int noperands;
@@ -142,7 +142,7 @@ check_asm_operands (rtx x)
   int i;
 
   if (!asm_labels_ok (x))
-    return 0;
+    return false;
 
   /* Post-reload, be more strict with things.  */
   if (reload_completed)
@@ -156,9 +156,9 @@ check_asm_operands (rtx x)
 
   noperands = asm_noperands (x);
   if (noperands < 0)
-    return 0;
+    return false;
   if (noperands == 0)
-    return 1;
+    return true;
 
   operands = XALLOCAVEC (rtx, noperands);
   constraints = XALLOCAVEC (const char *, noperands);
@@ -171,10 +171,10 @@ check_asm_operands (rtx x)
       if (c[0] == '%')
 	c++;
       if (! asm_operand_ok (operands[i], c, constraints))
-	return 0;
+	return false;
     }
 
-  return 1;
+  return true;
 }
 
 /* Static data for the next two routines.  */
@@ -212,8 +212,8 @@ static int temporarily_undone_changes = 0;
 
    If IN_GROUP is zero, this is a single change.  Try to recognize the insn
    or validate the memory reference with the change applied.  If the result
-   is not valid for the machine, suppress the change and return zero.
-   Otherwise, perform the change and return 1.  */
+   is not valid for the machine, suppress the change and return false.
+   Otherwise, perform the change and return true.  */
 
 static bool
 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group,
@@ -232,7 +232,7 @@ validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group,
 
   if ((old == new_rtx || rtx_equal_p (old, new_rtx))
       && (new_len < 0 || XVECLEN (new_rtx, 0) == new_len))
-    return 1;
+    return true;
 
   gcc_assert ((in_group != 0 || num_changes == 0)
 	      && (new_len < 0 || new_rtx == *loc));
@@ -275,7 +275,7 @@ validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group,
      change group we made.  */
 
   if (in_group)
-    return 1;
+    return true;
   else
     return apply_change_group ();
 }
@@ -348,7 +348,7 @@ check_invalid_inc_dec (rtx reg, const_rtx, void *data)
    match the instructions will be added to the current change group.
    Otherwise the changes will take effect immediately.  */
 
-int
+bool
 insn_invalid_p (rtx_insn *insn, bool in_group)
 {
   rtx pat = PATTERN (insn);
@@ -360,14 +360,14 @@ insn_invalid_p (rtx_insn *insn, bool in_group)
 		      && ! reload_completed 
                       && ! reload_in_progress)
 		     ? &num_clobbers : 0);
-  int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
+  bool is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
 
 
   /* If this is an asm and the operand aren't legal, then fail.  Likewise if
      this is not an asm and the insn wasn't recognized.  */
   if ((is_asm && ! check_asm_operands (PATTERN (insn)))
       || (!is_asm && icode < 0))
-    return 1;
+    return true;
 
   /* If we have to add CLOBBERs, fail if we have to add ones that reference
      hard registers since our callers can't know if they are live or not.
@@ -377,7 +377,7 @@ insn_invalid_p (rtx_insn *insn, bool in_group)
       rtx newpat;
 
       if (added_clobbers_hard_reg_p (icode))
-	return 1;
+	return true;
 
       newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
       XVECEXP (newpat, 0, 0) = pat;
@@ -394,7 +394,7 @@ insn_invalid_p (rtx_insn *insn, bool in_group)
       extract_insn (insn);
 
       if (! constrain_operands (1, get_preferred_alternatives (insn)))
-	return 1;
+	return true;
     }
 
   /* Punt if REG_INC argument overlaps some stored REG.  */
@@ -405,11 +405,11 @@ insn_invalid_p (rtx_insn *insn, bool in_group)
 	rtx reg = XEXP (link, 0);
 	note_stores (insn, check_invalid_inc_dec, &reg);
 	if (reg == NULL_RTX)
-	  return 1;
+	  return true;
       }
 
   INSN_CODE (insn) = icode;
-  return 0;
+  return false;
 }
 
 /* Return number of changes made and not validated yet.  */
@@ -420,9 +420,9 @@ num_changes_pending (void)
 }
 
 /* Tentatively apply the changes numbered NUM and up.
-   Return 1 if all changes are valid, zero otherwise.  */
+   Return true if all changes are valid, false otherwise.  */
 
-int
+bool
 verify_changes (int num)
 {
   int i;
@@ -554,21 +554,21 @@ confirm_change_group (void)
 }
 
 /* Apply a group of changes previously issued with `validate_change'.
-   If all changes are valid, call confirm_change_group and return 1,
-   otherwise, call cancel_changes and return 0.  */
+   If all changes are valid, call confirm_change_group and return true,
+   otherwise, call cancel_changes and return false.  */
 
-int
+bool
 apply_change_group (void)
 {
   if (verify_changes (0))
     {
       confirm_change_group ();
-      return 1;
+      return true;
     }
   else
     {
       cancel_changes (0);
-      return 0;
+      return false;
     }
 }
 
@@ -894,7 +894,7 @@ validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object,
    with TO.  After all changes have been made, validate by seeing
    if INSN is still valid.  */
 
-int
+bool
 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
 {
   validate_replace_rtx_1 (loc, from, to, insn, true);
@@ -904,7 +904,7 @@ validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc)
 /* Try replacing every occurrence of FROM in INSN with TO.  After all
    changes have been made, validate by seeing if INSN is still valid.  */
 
-int
+bool
 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
 {
   validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true);
@@ -917,7 +917,7 @@ validate_replace_rtx (rtx from, rtx to, rtx_insn *insn)
    validate_replace_rtx (from, to, insn) is equivalent to
    validate_replace_rtx_part (from, to, &PATTERN (insn), insn).  */
 
-int
+bool
 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
 {
   validate_replace_rtx_1 (where, from, to, insn, true);
@@ -925,7 +925,7 @@ validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn)
 }
 
 /* Same as above, but do not simplify rtx afterwards.  */
-int
+bool
 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where,
 				      rtx_insn *insn)
 {
@@ -953,7 +953,7 @@ struct validate_replace_src_data
 {
   rtx from;			/* Old RTX */
   rtx to;			/* New RTX */
-  rtx_insn *insn;			/* Insn in which substitution is occurring.  */
+  rtx_insn *insn;		/* Insn in which substitution is occurring.  */
 };
 
 static void
@@ -2705,13 +2705,13 @@ extract_constrain_insn_cached (rtx_insn *insn)
 }
 
 /* Do cached constrain_operands on INSN and complain about failures.  */
-int
+bool
 constrain_operands_cached (rtx_insn *insn, int strict)
 {
   if (which_alternative == -1)
     return constrain_operands (strict, get_enabled_alternatives (insn));
   else
-    return 1;
+    return true;
 }
 
 /* Analyze INSN and fill in recog_data.  */
@@ -3029,7 +3029,7 @@ struct funny_match
   int this_op, other;
 };
 
-int
+bool
 constrain_operands (int strict, alternative_mask alternatives)
 {
   const char *constraints[MAX_RECOG_OPERANDS];
@@ -3042,7 +3042,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 
   which_alternative = 0;
   if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
-    return 1;
+    return true;
 
   for (c = 0; c < recog_data.n_operands; c++)
     constraints[c] = recog_data.constraints[c];
@@ -3051,7 +3051,7 @@ constrain_operands (int strict, alternative_mask alternatives)
     {
       int seen_earlyclobber_at = -1;
       int opno;
-      int lose = 0;
+      bool lose = false;
       funny_match_index = 0;
 
       if (!TEST_BIT (alternatives, which_alternative))
@@ -3074,7 +3074,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 	  machine_mode mode = GET_MODE (op);
 	  const char *p = constraints[opno];
 	  int offset = 0;
-	  int win = 0;
+	  bool win = false;
 	  int val;
 	  int len;
 
@@ -3101,7 +3101,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 	  /* An empty constraint or empty alternative
 	     allows anything which matched the pattern.  */
 	  if (*p == 0 || *p == ',')
-	    win = 1;
+	    win = true;
 
 	  do
 	    switch (c = *p, len = CONSTRAINT_LEN (c, p), c)
@@ -3167,7 +3167,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 		  matching_operands[match] = opno;
 
 		  if (val != 0)
-		    win = 1;
+		    win = true;
 
 		  /* If output is *x and input is *--x, arrange later
 		     to change the output to *--x as well, since the
@@ -3192,7 +3192,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 		    && (strict <= 0
 			|| (strict_memory_address_p
 			     (recog_data.operand_mode[opno], op))))
-		  win = 1;
+		  win = true;
 		break;
 
 		/* No need to check general_operand again;
@@ -3209,10 +3209,10 @@ constrain_operands (int strict, alternative_mask alternatives)
 			|| (reload_in_progress
 			    && REGNO (op) >= FIRST_PSEUDO_REGISTER)
 			|| reg_fits_class_p (op, GENERAL_REGS, offset, mode))
-		      win = 1;
+		      win = true;
 		  }
 		else if (strict < 0 || general_operand (op, mode))
-		  win = 1;
+		  win = true;
 		break;
 
 	      default:
@@ -3228,11 +3228,11 @@ constrain_operands (int strict, alternative_mask alternatives)
 			  || (strict == 0 && GET_CODE (op) == SCRATCH)
 			  || (REG_P (op)
 			      && reg_fits_class_p (op, cl, offset, mode)))
-		        win = 1;
+			win = true;
 		    }
 
 		  else if (constraint_satisfied_p (op, cn))
-		    win = 1;
+		    win = true;
 
 		  else if ((insn_extra_memory_constraint (cn)
 			    || insn_extra_relaxed_memory_constraint (cn))
@@ -3247,11 +3247,11 @@ constrain_operands (int strict, alternative_mask alternatives)
 			       /* During reload, accept a pseudo  */
 			       || (reload_in_progress && REG_P (op)
 				   && REGNO (op) >= FIRST_PSEUDO_REGISTER)))
-		    win = 1;
+		    win = true;
 		  else if (insn_extra_address_constraint (cn)
 			   /* Every address operand can be reloaded to fit.  */
 			   && strict < 0)
-		    win = 1;
+		    win = true;
 		  /* Cater to architectures like IA-64 that define extra memory
 		     constraints without using define_memory_constraint.  */
 		  else if (reload_in_progress
@@ -3261,7 +3261,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 			   && reg_equiv_mem (REGNO (op)) != 0
 			   && constraint_satisfied_p
 			      (reg_equiv_mem (REGNO (op)), cn))
-		    win = 1;
+		    win = true;
 		  break;
 		}
 	      }
@@ -3271,7 +3271,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 	  /* If this operand did not win somehow,
 	     this alternative loses.  */
 	  if (! win)
-	    lose = 1;
+	    lose = true;
 	}
       /* This alternative won; the operands are ok.
 	 Change whichever operands this alternative says to change.  */
@@ -3302,7 +3302,7 @@ constrain_operands (int strict, alternative_mask alternatives)
 						 recog_data.operand[eopno]))
 		      && ! safe_from_earlyclobber (recog_data.operand[opno],
 						   recog_data.operand[eopno]))
-		    lose = 1;
+		    lose = true;
 
 	  if (! lose)
 	    {
@@ -3328,14 +3328,14 @@ constrain_operands (int strict, alternative_mask alternatives)
 			  if (strchr (recog_data.constraints[opno], '<') == NULL
 			      && strchr (recog_data.constraints[opno], '>')
 				 == NULL)
-			    return 0;
+			    return false;
 			  break;
 			default:
 			  break;
 			}
 		}
 
-	      return 1;
+	      return true;
 	    }
 	}
 
@@ -3349,7 +3349,7 @@ constrain_operands (int strict, alternative_mask alternatives)
   if (strict == 0)
     return constrain_operands (-1, alternatives);
   else
-    return 0;
+    return false;
 }
 
 /* Return true iff OPERAND (assumed to be a REG rtx)
@@ -3517,7 +3517,7 @@ split_all_insns (void)
 /* Same as split_all_insns, but do not expect CFG to be available.
    Used by machine dependent reorg passes.  */
 
-unsigned int
+void
 split_all_insns_noflow (void)
 {
   rtx_insn *next, *insn;
@@ -3547,7 +3547,6 @@ split_all_insns_noflow (void)
 	    split_insn (insn);
 	}
     }
-  return 0;
 }
 
 struct peep2_insn_data
@@ -3596,7 +3595,7 @@ peep2_next_insn (int n)
 /* Return true if REGNO is dead before the Nth non-note insn
    after `current'.  */
 
-int
+bool
 peep2_regno_dead_p (int ofs, int regno)
 {
   gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
@@ -3610,7 +3609,7 @@ peep2_regno_dead_p (int ofs, int regno)
 
 /* Similarly for a REG.  */
 
-int
+bool
 peep2_reg_dead_p (int ofs, rtx reg)
 {
   gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
@@ -3622,8 +3621,8 @@ peep2_reg_dead_p (int ofs, rtx reg)
   unsigned int end_regno = END_REGNO (reg);
   for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno)
     if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno))
-      return 0;
-  return 1;
+      return false;
+  return true;
 }
 
 /* Regno offset to be used in the register search.  */
@@ -3673,7 +3672,8 @@ peep2_find_free_register (int from, int to, const char *class_str,
 
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     {
-      int raw_regno, regno, success, j;
+      int raw_regno, regno, j;
+      bool success;
 
       /* Distribute the free registers as much as possible.  */
       raw_regno = search_ofs + i;
@@ -3689,38 +3689,38 @@ peep2_find_free_register (int from, int to, const char *class_str,
       if (!targetm.hard_regno_mode_ok (regno, mode))
 	continue;
 
-      success = 1;
+      success = true;
       for (j = 0; success && j < hard_regno_nregs (regno, mode); j++)
 	{
 	  /* Don't allocate fixed registers.  */
 	  if (fixed_regs[regno + j])
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 	  /* Don't allocate global registers.  */
 	  if (global_regs[regno + j])
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 	  /* Make sure the register is of the right class.  */
 	  if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j))
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 	  /* And that we don't create an extra save/restore.  */
 	  if (! crtl->abi->clobbers_full_reg_p (regno + j)
 	      && ! df_regs_ever_live_p (regno + j))
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 
 	  if (! targetm.hard_regno_scratch_ok (regno + j))
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 
@@ -3729,14 +3729,14 @@ peep2_find_free_register (int from, int to, const char *class_str,
 	       || regno + j == HARD_FRAME_POINTER_REGNUM)
 	      && (! reload_completed || frame_pointer_needed))
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 
 	  if (TEST_HARD_REG_BIT (*reg_set, regno + j)
 	      || TEST_HARD_REG_BIT (live, regno + j))
 	    {
-	      success = 0;
+	      success = false;
 	      break;
 	    }
 	}
@@ -4244,7 +4244,7 @@ store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set)
    data not the address operand(s) of the store.  IN_INSN and OUT_INSN
    must be either a single_set or a PARALLEL with SETs inside.  */
 
-int
+bool
 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
 {
   rtx in_set = single_set (in_insn);
@@ -4276,7 +4276,7 @@ store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
    or multiple set; IN_INSN should be single_set for truth, but for convenience
    of insn categorization may be any JUMP or CALL insn.  */
 
-int
+bool
 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
 {
   rtx out_set, in_set;
@@ -4618,7 +4618,8 @@ public:
 
   unsigned int execute (function *) final override
     {
-      return split_all_insns_noflow ();
+      split_all_insns_noflow ();
+      return 0;
     }
 
 }; // class pass_split_for_shorten_branches
diff --git a/gcc/recog.h b/gcc/recog.h
index 539a27c..badf8e3 100644
--- a/gcc/recog.h
+++ b/gcc/recog.h
@@ -184,22 +184,22 @@ inline insn_propagation::insn_propagation (rtx_insn *insn)
 
 extern void init_recog (void);
 extern void init_recog_no_volatile (void);
-extern int check_asm_operands (rtx);
+extern bool check_asm_operands (rtx);
 extern int asm_operand_ok (rtx, const char *, const char **);
 extern bool validate_change (rtx, rtx *, rtx, bool);
 extern bool validate_unshare_change (rtx, rtx *, rtx, bool);
 extern bool validate_change_xveclen (rtx, rtx *, int, bool);
 extern bool canonicalize_change_group (rtx_insn *insn, rtx x);
-extern int insn_invalid_p (rtx_insn *, bool);
-extern int verify_changes (int);
+extern bool insn_invalid_p (rtx_insn *, bool);
+extern bool verify_changes (int);
 extern void confirm_change_group (void);
-extern int apply_change_group (void);
+extern bool apply_change_group (void);
 extern int num_validated_changes (void);
 extern void cancel_changes (int);
 extern void temporarily_undo_changes (int);
 extern void redo_changes (int);
-extern int constrain_operands (int, alternative_mask);
-extern int constrain_operands_cached (rtx_insn *, int);
+extern bool constrain_operands (int, alternative_mask);
+extern bool constrain_operands_cached (rtx_insn *, int);
 extern bool memory_address_addr_space_p (machine_mode, rtx, addr_space_t);
 #define memory_address_p(mode,addr) \
 	memory_address_addr_space_p ((mode), (addr), ADDR_SPACE_GENERIC)
@@ -207,10 +207,10 @@ extern bool strict_memory_address_addr_space_p (machine_mode, rtx,
 						addr_space_t);
 #define strict_memory_address_p(mode,addr) \
 	strict_memory_address_addr_space_p ((mode), (addr), ADDR_SPACE_GENERIC)
-extern int validate_replace_rtx_subexp (rtx, rtx, rtx_insn *, rtx *);
-extern int validate_replace_rtx (rtx, rtx, rtx_insn *);
-extern int validate_replace_rtx_part (rtx, rtx, rtx *, rtx_insn *);
-extern int validate_replace_rtx_part_nosimplify (rtx, rtx, rtx *, rtx_insn *);
+extern bool validate_replace_rtx_subexp (rtx, rtx, rtx_insn *, rtx *);
+extern bool validate_replace_rtx (rtx, rtx, rtx_insn *);
+extern bool validate_replace_rtx_part (rtx, rtx, rtx *, rtx_insn *);
+extern bool validate_replace_rtx_part_nosimplify (rtx, rtx, rtx *, rtx_insn *);
 extern void validate_replace_rtx_group (rtx, rtx, rtx_insn *);
 extern void validate_replace_src_group (rtx, rtx, rtx_insn *);
 extern bool validate_simplify_insn (rtx_insn *insn);
@@ -232,7 +232,7 @@ extern int recog (rtx, rtx_insn *, int *);
 inline int recog_memoized (rtx_insn *insn);
 #endif
 extern void add_clobbers (rtx, int);
-extern int added_clobbers_hard_reg_p (int);
+extern bool added_clobbers_hard_reg_p (int);
 extern void insn_extract (rtx_insn *);
 extern void extract_insn (rtx_insn *);
 extern void extract_constrain_insn (rtx_insn *insn);
@@ -243,16 +243,16 @@ extern void preprocess_constraints (int, int, const char **,
 extern const operand_alternative *preprocess_insn_constraints (unsigned int);
 extern void preprocess_constraints (rtx_insn *);
 extern rtx_insn *peep2_next_insn (int);
-extern int peep2_regno_dead_p (int, int);
-extern int peep2_reg_dead_p (int, rtx);
+extern bool peep2_regno_dead_p (int, int);
+extern bool peep2_reg_dead_p (int, rtx);
 #ifdef HARD_CONST
 extern rtx peep2_find_free_register (int, int, const char *,
 				     machine_mode, HARD_REG_SET *);
 #endif
 extern rtx_insn *peephole2_insns (rtx, rtx_insn *, int *);
 
-extern int store_data_bypass_p (rtx_insn *, rtx_insn *);
-extern int if_test_bypass_p (rtx_insn *, rtx_insn *);
+extern bool store_data_bypass_p (rtx_insn *, rtx_insn *);
+extern bool if_test_bypass_p (rtx_insn *, rtx_insn *);
 
 extern void copy_frame_info_to_split_insn (rtx_insn *, rtx_insn *);
 
diff --git a/gcc/rtl.cc b/gcc/rtl.cc
index 0748427..6354102 100644
--- a/gcc/rtl.cc
+++ b/gcc/rtl.cc
@@ -412,13 +412,14 @@ int currently_expanding_to_rtl;
 
 
 
-/* Same as rtx_equal_p, but call CB on each pair of rtx if CB is not NULL.
-   When the callback returns true, we continue with the new pair.
-   Whenever changing this function check if rtx_equal_p below doesn't need
-   changing as well.  */
+/* Return true if X and Y are identical-looking rtx's.
+   This is the Lisp function EQUAL for rtx arguments.
+
+   Call CB on each pair of rtx if CB is not NULL.
+   When the callback returns true, we continue with the new pair.  */
 
-int
-rtx_equal_p_cb (const_rtx x, const_rtx y, rtx_equal_p_callback_function cb)
+bool
+rtx_equal_p (const_rtx x, const_rtx y, rtx_equal_p_callback_function cb)
 {
   int i;
   int j;
@@ -427,176 +428,29 @@ rtx_equal_p_cb (const_rtx x, const_rtx y, rtx_equal_p_callback_function cb)
   rtx nx, ny;
 
   if (x == y)
-    return 1;
+    return true;
   if (x == 0 || y == 0)
-    return 0;
+    return false;
 
   /* Invoke the callback first.  */
   if (cb != NULL
       && ((*cb) (&x, &y, &nx, &ny)))
-    return rtx_equal_p_cb (nx, ny, cb);
-
-  code = GET_CODE (x);
-  /* Rtx's of different codes cannot be equal.  */
-  if (code != GET_CODE (y))
-    return 0;
-
-  /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
-     (REG:SI x) and (REG:HI x) are NOT equivalent.  */
-
-  if (GET_MODE (x) != GET_MODE (y))
-    return 0;
-
-  /* MEMs referring to different address space are not equivalent.  */
-  if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y))
-    return 0;
-
-  /* Some RTL can be compared nonrecursively.  */
-  switch (code)
-    {
-    case REG:
-      return (REGNO (x) == REGNO (y));
-
-    case LABEL_REF:
-      return label_ref_label (x) == label_ref_label (y);
-
-    case SYMBOL_REF:
-      return XSTR (x, 0) == XSTR (y, 0);
-
-    case DEBUG_EXPR:
-    case VALUE:
-    case SCRATCH:
-    CASE_CONST_UNIQUE:
-      return 0;
-
-    case CONST_VECTOR:
-      if (!same_vector_encodings_p (x, y))
-	return false;
-      break;
-
-    case DEBUG_IMPLICIT_PTR:
-      return DEBUG_IMPLICIT_PTR_DECL (x)
-	     == DEBUG_IMPLICIT_PTR_DECL (y);
-
-    case DEBUG_PARAMETER_REF:
-      return DEBUG_PARAMETER_REF_DECL (x)
-	     == DEBUG_PARAMETER_REF_DECL (y);
-
-    case ENTRY_VALUE:
-      return rtx_equal_p_cb (ENTRY_VALUE_EXP (x), ENTRY_VALUE_EXP (y), cb);
-
-    default:
-      break;
-    }
-
-  /* Compare the elements.  If any pair of corresponding elements
-     fail to match, return 0 for the whole thing.  */
-
-  fmt = GET_RTX_FORMAT (code);
-  for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
-    {
-      switch (fmt[i])
-	{
-	case 'w':
-	  if (XWINT (x, i) != XWINT (y, i))
-	    return 0;
-	  break;
-
-	case 'n':
-	case 'i':
-	  if (XINT (x, i) != XINT (y, i))
-	    {
-#ifndef GENERATOR_FILE
-	      if (((code == ASM_OPERANDS && i == 6)
-		   || (code == ASM_INPUT && i == 1))
-		  && XINT (x, i) == XINT (y, i))
-		break;
-#endif
-	      return 0;
-	    }
-	  break;
-
-	case 'p':
-	  if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
-	    return 0;
-	  break;
-
-	case 'V':
-	case 'E':
-	  /* Two vectors must have the same length.  */
-	  if (XVECLEN (x, i) != XVECLEN (y, i))
-	    return 0;
-
-	  /* And the corresponding elements must match.  */
-	  for (j = 0; j < XVECLEN (x, i); j++)
-	    if (rtx_equal_p_cb (XVECEXP (x, i, j),
-                                XVECEXP (y, i, j), cb) == 0)
-	      return 0;
-	  break;
-
-	case 'e':
-	  if (rtx_equal_p_cb (XEXP (x, i), XEXP (y, i), cb) == 0)
-	    return 0;
-	  break;
-
-	case 'S':
-	case 's':
-	  if ((XSTR (x, i) || XSTR (y, i))
-	      && (! XSTR (x, i) || ! XSTR (y, i)
-		  || strcmp (XSTR (x, i), XSTR (y, i))))
-	    return 0;
-	  break;
-
-	case 'u':
-	  /* These are just backpointers, so they don't matter.  */
-	  break;
-
-	case '0':
-	case 't':
-	  break;
-
-	  /* It is believed that rtx's at this level will never
-	     contain anything but integers and other rtx's,
-	     except for within LABEL_REFs and SYMBOL_REFs.  */
-	default:
-	  gcc_unreachable ();
-	}
-    }
-  return 1;
-}
-
-/* Return 1 if X and Y are identical-looking rtx's.
-   This is the Lisp function EQUAL for rtx arguments.
-   Whenever changing this function check if rtx_equal_p_cb above doesn't need
-   changing as well.  */
-
-int
-rtx_equal_p (const_rtx x, const_rtx y)
-{
-  int i;
-  int j;
-  enum rtx_code code;
-  const char *fmt;
-
-  if (x == y)
-    return 1;
-  if (x == 0 || y == 0)
-    return 0;
+    return rtx_equal_p (nx, ny, cb);
 
   code = GET_CODE (x);
   /* Rtx's of different codes cannot be equal.  */
   if (code != GET_CODE (y))
-    return 0;
+    return false;
 
   /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
      (REG:SI x) and (REG:HI x) are NOT equivalent.  */
 
   if (GET_MODE (x) != GET_MODE (y))
-    return 0;
+    return false;
 
   /* MEMs referring to different address space are not equivalent.  */
   if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y))
-    return 0;
+    return false;
 
   /* Some RTL can be compared nonrecursively.  */
   switch (code)
@@ -614,7 +468,7 @@ rtx_equal_p (const_rtx x, const_rtx y)
     case VALUE:
     case SCRATCH:
     CASE_CONST_UNIQUE:
-      return 0;
+      return false;
 
     case CONST_VECTOR:
       if (!same_vector_encodings_p (x, y))
@@ -630,7 +484,7 @@ rtx_equal_p (const_rtx x, const_rtx y)
 	     == DEBUG_PARAMETER_REF_DECL (y);
 
     case ENTRY_VALUE:
-      return rtx_equal_p (ENTRY_VALUE_EXP (x), ENTRY_VALUE_EXP (y));
+      return rtx_equal_p (ENTRY_VALUE_EXP (x), ENTRY_VALUE_EXP (y), cb);
 
     default:
       break;
@@ -646,7 +500,7 @@ rtx_equal_p (const_rtx x, const_rtx y)
 	{
 	case 'w':
 	  if (XWINT (x, i) != XWINT (y, i))
-	    return 0;
+	    return false;
 	  break;
 
 	case 'n':
@@ -659,30 +513,30 @@ rtx_equal_p (const_rtx x, const_rtx y)
 		  && XINT (x, i) == XINT (y, i))
 		break;
 #endif
-	      return 0;
+	      return false;
 	    }
 	  break;
 
 	case 'p':
 	  if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
-	    return 0;
+	    return false;
 	  break;
 
 	case 'V':
 	case 'E':
 	  /* Two vectors must have the same length.  */
 	  if (XVECLEN (x, i) != XVECLEN (y, i))
-	    return 0;
+	    return false;
 
 	  /* And the corresponding elements must match.  */
 	  for (j = 0; j < XVECLEN (x, i); j++)
-	    if (rtx_equal_p (XVECEXP (x, i, j),  XVECEXP (y, i, j)) == 0)
-	      return 0;
+	    if (!rtx_equal_p (XVECEXP (x, i, j), XVECEXP (y, i, j), cb))
+	      return false;
 	  break;
 
 	case 'e':
-	  if (rtx_equal_p (XEXP (x, i), XEXP (y, i)) == 0)
-	    return 0;
+	  if (!rtx_equal_p (XEXP (x, i), XEXP (y, i), cb))
+	    return false;
 	  break;
 
 	case 'S':
@@ -690,7 +544,7 @@ rtx_equal_p (const_rtx x, const_rtx y)
 	  if ((XSTR (x, i) || XSTR (y, i))
 	      && (! XSTR (x, i) || ! XSTR (y, i)
 		  || strcmp (XSTR (x, i), XSTR (y, i))))
-	    return 0;
+	    return false;
 	  break;
 
 	case 'u':
@@ -708,7 +562,7 @@ rtx_equal_p (const_rtx x, const_rtx y)
 	  gcc_unreachable ();
 	}
     }
-  return 1;
+  return true;
 }
 
 /* Return true if all elements of VEC are equal.  */
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 988691f..9c6803f 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -3008,7 +3008,12 @@ extern rtx copy_rtx_if_shared (rtx);
 /* In rtl.cc */
 extern unsigned int rtx_size (const_rtx);
 extern rtx shallow_copy_rtx (const_rtx CXX_MEM_STAT_INFO);
-extern int rtx_equal_p (const_rtx, const_rtx);
+
+typedef bool (*rtx_equal_p_callback_function) (const_rtx *, const_rtx *,
+					       rtx *, rtx *);
+extern bool rtx_equal_p (const_rtx, const_rtx,
+			 rtx_equal_p_callback_function = NULL);
+
 extern bool rtvec_all_equal_p (const_rtvec);
 extern bool rtvec_series_p (rtvec, int);
 
@@ -3710,16 +3715,6 @@ typedef int (*for_each_inc_dec_fn) (rtx mem, rtx op, rtx dest, rtx src,
 				    rtx srcoff, void *arg);
 extern int for_each_inc_dec (rtx, for_each_inc_dec_fn, void *arg);
 
-typedef int (*rtx_equal_p_callback_function) (const_rtx *, const_rtx *,
-                                              rtx *, rtx *);
-extern int rtx_equal_p_cb (const_rtx, const_rtx,
-                           rtx_equal_p_callback_function);
-
-typedef int (*hash_rtx_callback_function) (const_rtx, machine_mode, rtx *,
-                                           machine_mode *);
-extern unsigned hash_rtx_cb (const_rtx, machine_mode, int *, int *,
-                             bool, hash_rtx_callback_function);
-
 extern rtx regno_use_in (unsigned int, rtx);
 extern bool auto_inc_p (const_rtx);
 extern bool in_insn_list_p (const rtx_insn_list *, const rtx_insn *);
@@ -3800,7 +3795,7 @@ extern void setup_reg_classes (int, enum reg_class, enum reg_class,
 			       enum reg_class);
 
 extern void split_all_insns (void);
-extern unsigned int split_all_insns_noflow (void);
+extern void split_all_insns_noflow (void);
 
 #define MAX_SAVED_CONST_INT 64
 extern GTY(()) rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
@@ -4142,7 +4137,11 @@ extern int rtx_to_tree_code (enum rtx_code);
 /* In cse.cc */
 extern int delete_trivially_dead_insns (rtx_insn *, int);
 extern bool exp_equiv_p (const_rtx, const_rtx, int, bool);
-extern unsigned hash_rtx (const_rtx x, machine_mode, int *, int *, bool);
+
+typedef bool (*hash_rtx_callback_function) (const_rtx, machine_mode, rtx *,
+					    machine_mode *);
+extern unsigned hash_rtx (const_rtx, machine_mode, int *, int *,
+			  bool, hash_rtx_callback_function = NULL);
 
 /* In dse.cc */
 extern bool check_for_inc_dec (rtx_insn *insn);
diff --git a/gcc/sel-sched-ir.cc b/gcc/sel-sched-ir.cc
index 9241987..a829ba6 100644
--- a/gcc/sel-sched-ir.cc
+++ b/gcc/sel-sched-ir.cc
@@ -1076,10 +1076,10 @@ free_nop_pool (void)
 }
 
 
-/* Skip unspec to support ia64 speculation. Called from rtx_equal_p_cb.
+/* Skip unspec to support ia64 speculation. Called from rtx_equal_p.
    The callback is given two rtxes XX and YY and writes the new rtxes
    to NX and NY in case some needs to be skipped.  */
-static int
+static bool
 skip_unspecs_callback (const_rtx *xx, const_rtx *yy, rtx *nx, rtx* ny)
 {
   const_rtx x = *xx;
@@ -1091,7 +1091,7 @@ skip_unspecs_callback (const_rtx *xx, const_rtx *yy, rtx *nx, rtx* ny)
     {
       *nx = XVECEXP (x, 0, 0);
       *ny = CONST_CAST_RTX (y);
-      return 1;
+      return true;
     }
 
   if (GET_CODE (y) == UNSPEC
@@ -1100,16 +1100,16 @@ skip_unspecs_callback (const_rtx *xx, const_rtx *yy, rtx *nx, rtx* ny)
     {
       *nx = CONST_CAST_RTX (x);
       *ny = XVECEXP (y, 0, 0);
-      return 1;
+      return true;
     }
 
-  return 0;
+  return false;
 }
 
-/* Callback, called from hash_rtx_cb.  Helps to hash UNSPEC rtx X in a correct way
+/* Callback, called from hash_rtx.  Helps to hash UNSPEC rtx X in a correct way
    to support ia64 speculation.  When changes are needed, new rtx X and new mode
    NMODE are written, and the callback returns true.  */
-static int
+static bool
 hash_with_unspec_callback (const_rtx x, machine_mode mode ATTRIBUTE_UNUSED,
                            rtx *nx, machine_mode* nmode)
 {
@@ -1119,10 +1119,10 @@ hash_with_unspec_callback (const_rtx x, machine_mode mode ATTRIBUTE_UNUSED,
     {
       *nx = XVECEXP (x, 0 ,0);
       *nmode = VOIDmode;
-      return 1;
+      return true;
     }
 
-  return 0;
+  return false;
 }
 
 /* Returns LHS and RHS are ok to be scheduled separately.  */
@@ -1188,16 +1188,16 @@ vinsn_init (vinsn_t vi, insn_t insn, bool force_unique_p)
     {
       rtx rhs = VINSN_RHS (vi);
 
-      VINSN_HASH (vi) = hash_rtx_cb (rhs, GET_MODE (rhs),
-                                     NULL, NULL, false, hrcf);
-      VINSN_HASH_RTX (vi) = hash_rtx_cb (VINSN_PATTERN (vi),
-                                         VOIDmode, NULL, NULL,
-                                         false, hrcf);
+      VINSN_HASH (vi) = hash_rtx (rhs, GET_MODE (rhs),
+				  NULL, NULL, false, hrcf);
+      VINSN_HASH_RTX (vi) = hash_rtx (VINSN_PATTERN (vi),
+				      VOIDmode, NULL, NULL,
+				      false, hrcf);
     }
   else
     {
-      VINSN_HASH (vi) = hash_rtx_cb (VINSN_PATTERN (vi), VOIDmode,
-                                     NULL, NULL, false, hrcf);
+      VINSN_HASH (vi) = hash_rtx (VINSN_PATTERN (vi), VOIDmode,
+				  NULL, NULL, false, hrcf);
       VINSN_HASH_RTX (vi) = VINSN_HASH (vi);
     }
 
@@ -1602,10 +1602,10 @@ vinsn_equal_p (vinsn_t x, vinsn_t y)
       gcc_assert (VINSN_RHS (x));
       gcc_assert (VINSN_RHS (y));
 
-      return rtx_equal_p_cb (VINSN_RHS (x), VINSN_RHS (y), repcf);
+      return rtx_equal_p (VINSN_RHS (x), VINSN_RHS (y), repcf);
     }
 
-  return rtx_equal_p_cb (VINSN_PATTERN (x), VINSN_PATTERN (y), repcf);
+  return rtx_equal_p (VINSN_PATTERN (x), VINSN_PATTERN (y), repcf);
 }
 
 
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index 21b7eb4..1b58144 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -2831,7 +2831,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code,
 	 when x is NaN, infinite, or finite and nonzero.  They aren't
 	 when x is -0 and the rounding mode is not towards -infinity,
 	 since (-0) + 0 is then 0.  */
-      if (!HONOR_SIGNED_ZEROS (mode) && trueop1 == CONST0_RTX (mode))
+      if (!HONOR_SIGNED_ZEROS (mode) && !HONOR_SNANS (mode)
+	  && trueop1 == CONST0_RTX (mode))
 	return op0;
 
       /* ((-a) + b) -> (b - a) and similarly for (a + (-b)).  These
@@ -4860,6 +4861,17 @@ simplify_ashift:
 	    return simplify_gen_binary (VEC_SELECT, mode, XEXP (trueop0, 0),
 					gen_rtx_PARALLEL (VOIDmode, vec));
 	  }
+	/* (vec_concat:
+	     (subreg_lowpart:N OP)
+	     (vec_select:N OP P))  -->  OP when P selects the high half
+	    of the OP.  */
+	if (GET_CODE (trueop0) == SUBREG
+	    && subreg_lowpart_p (trueop0)
+	    && GET_CODE (trueop1) == VEC_SELECT
+	    && SUBREG_REG (trueop0) == XEXP (trueop1, 0)
+	    && !side_effects_p (XEXP (trueop1, 0))
+	    && vec_series_highpart_p (op1_mode, mode, XEXP (trueop1, 1)))
+	  return XEXP (trueop1, 0);
       }
       return 0;
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 34bad04..6ff4c0d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,672 @@
+2023-06-21  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/87477
+	PR fortran/107900
+	PR fortran/110224
+	PR fortran/88688
+	PR fortran/94380
+	PR fortran/95398
+	* gfortran.dg/pr107900.f90 : New test
+	* gfortran.dg/pr110224.f90 : New test
+	* gfortran.dg/pr88688.f90 : New test
+	* gfortran.dg/pr94380.f90 : New test
+	* gfortran.dg/pr95398.f90 : Set -std=f2008, bump the line
+	numbers in the error tests by two and change the text in two.
+
+2023-06-21  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/108961
+	* gfortran.dg/pr108961.f90: New test.
+
+2023-06-21  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/110018
+	* gcc.target/i386/pr110018-1.c: Use explicit signed types.
+	* gcc.target/i386/pr110018-2.c: New test.
+
+2023-06-21  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/sve/gather_earlyclobber.c: New test.
+	* gcc.target/aarch64/sve2/gather_earlyclobber.c: New test.
+
+2023-06-21  Richard Biener  <rguenther@suse.de>
+
+	* gcc.target/i386/vect-partial-vectors-1.c: New testcase.
+	* gcc.target/i386/vect-partial-vectors-2.c: Likewise.
+
+2023-06-21  Jan Beulich  <jbeulich@suse.com>
+
+	* gcc.target/i386/avx512f-copysign.c: New test.
+
+2023-06-21  Jan Beulich  <jbeulich@suse.com>
+
+	* gcc.target/i386/avx512f-dupv2di.c: Add
+	-mprefer-vector-width=512.
+
+2023-06-21  liuhongt  <hongtao.liu@intel.com>
+
+	* gcc.target/i386/pr110018-1.c: New test.
+
+2023-06-20  Lewis Hyatt  <lhyatt@gmail.com>
+
+	PR c++/66290
+	* c-c++-common/cpp/macro-ranges.c: New test.
+	* c-c++-common/cpp/line-2.c: Adapt to check for column information
+	on macro-related libcpp warnings.
+	* c-c++-common/cpp/line-3.c: Likewise.
+	* c-c++-common/cpp/macro-arg-count-1.c: Likewise.
+	* c-c++-common/cpp/pr58844-1.c: Likewise.
+	* c-c++-common/cpp/pr58844-2.c: Likewise.
+	* c-c++-common/cpp/warning-zero-location.c: Likewise.
+	* c-c++-common/pragma-diag-14.c: Likewise.
+	* c-c++-common/pragma-diag-15.c: Likewise.
+	* g++.dg/modules/macro-2_d.C: Likewise.
+	* g++.dg/modules/macro-4_d.C: Likewise.
+	* g++.dg/modules/macro-4_e.C: Likewise.
+	* g++.dg/spellcheck-macro-ordering.C: Likewise.
+	* gcc.dg/builtin-redefine.c: Likewise.
+	* gcc.dg/cpp/Wunused.c: Likewise.
+	* gcc.dg/cpp/redef2.c: Likewise.
+	* gcc.dg/cpp/redef3.c: Likewise.
+	* gcc.dg/cpp/redef4.c: Likewise.
+	* gcc.dg/cpp/ucnid-11-utf8.c: Likewise.
+	* gcc.dg/cpp/ucnid-11.c: Likewise.
+	* gcc.dg/cpp/undef2.c: Likewise.
+	* gcc.dg/cpp/warn-redefined-2.c: Likewise.
+	* gcc.dg/cpp/warn-redefined.c: Likewise.
+	* gcc.dg/cpp/warn-unused-macros-2.c: Likewise.
+	* gcc.dg/cpp/warn-unused-macros.c: Likewise.
+
+2023-06-20  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sve/pcs/args_1.c: Match moves from the stack
+	pointer to indirect argument registers and allow either to be used
+	as the base register in subsequent stores.
+	* gcc.target/aarch64/sve/pcs/args_8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_2.c: Allow the store of the
+	indirect argument to happen via the argument register or the
+	stack pointer.
+	* gcc.target/aarch64/sve/pcs/args_3.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_4.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_bf16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_5_le_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_bf16.c: Disable
+	-fcprop-registers and combine.
+	* gcc.target/aarch64/sve/pcs/args_6_be_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_be_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_bf16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/args_6_le_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_1.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_f16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_f32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_f64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_s8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u16.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u32.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u64.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_2_u8.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_3_nosc.c: Likewise.
+	* gcc.target/aarch64/sve/pcs/varargs_3_sc.c: Likewise.
+
+2023-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/79173
+	* g++.target/i386/pr79173-1.C: New test.
+
+2023-06-20  Martin Jambor  <mjambor@suse.cz>
+
+	PR ipa/110276
+	* gcc.dg/ipa/pr110276.c: New test.
+
+2023-06-20  Carl Love  <cel@us.ibm.com>
+
+	* gcc.target/powerpc/bfp/scalar-extract-exp-8.c: New test case.
+	* gcc.target/powerpc/bfp/scalar-extract-sig-8.c: New test case.
+	* gcc.target/powerpc/bfp/scalar-insert-exp-16.c: New test case.
+
+2023-06-20  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Add
+	-mabi=lp64d.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
+
+2023-06-20  Li Xu  <xuli1@eswincomputing.com>
+
+	* gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: New test.
+
+2023-06-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/partial/slp-1.c: Adapt testcase.
+	* gcc.target/riscv/rvv/autovec/partial/slp-16.c: New test.
+	* gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: New test.
+
+2023-06-20  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Add
+	-Wno-psabi.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c:
+	Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Dito.
+
+2023-06-20  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Add
+	-ffast-math.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Remove
+	-ffast-math
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Check for
+	vfmul.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/tree-ssa/ssa-dse-47.c: New testcase.
+	* c-c++-common/asan/pr106558.c: Avoid undefined behavior
+	due to missing return.
+
+2023-06-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/simd/addp-same-low_1.c: New test.
+
+2023-06-20  Jan Beulich  <jbeulich@suse.com>
+
+	* gcc.target/i386/avx512f-dupv2di.c: New test.
+
+2023-06-20  Richard Biener  <rguenther@suse.de>
+
+	PR debug/110295
+	* g++.dg/debug/pr110295.C: New testcase.
+
+2023-06-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Fix fail.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c: Ditto.
+
+2023-06-20  Lehua Ding  <lehua.ding@rivai.ai>
+
+	* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Add -Wno-psabi option.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.
+	* gcc.target/riscv/rvv/base/pr110119-1.c: Ditto.
+	* gcc.target/riscv/rvv/base/pr110119-2.c: Ditto.
+	* gcc.target/riscv/vector-abi-1.c: Ditto.
+	* gcc.target/riscv/vector-abi-2.c: Ditto.
+	* gcc.target/riscv/vector-abi-3.c: Ditto.
+	* gcc.target/riscv/vector-abi-4.c: Ditto.
+	* gcc.target/riscv/vector-abi-5.c: Ditto.
+	* gcc.target/riscv/vector-abi-6.c: Ditto.
+	* gcc.target/riscv/vector-abi-7.c: New test.
+	* gcc.target/riscv/vector-abi-8.c: New test.
+	* gcc.target/riscv/vector-abi-9.c: New test.
+
+2023-06-19  Jin Ma  <jinma@linux.alibaba.com>
+
+	* gcc.target/riscv/interrupt-fcsr-1.c: New test.
+	* gcc.target/riscv/interrupt-fcsr-2.c: New test.
+	* gcc.target/riscv/interrupt-fcsr-3.c: New test.
+
+2023-06-19  Jan Hubicka  <jh@suse.cz>
+
+	PR tree-optimization/109811
+	PR tree-optimization/109849
+	* gcc.dg/tree-ssa/phiprop-1.c: New test.
+	* gcc.dg/tree-ssa/pr21463.c: Adjust template.
+
+2023-06-19  Pan Li  <pan2.li@intel.com>
+
+	PR target/110299
+	* gcc.target/riscv/rvv/base/pr110299-1.c: New test.
+	* gcc.target/riscv/rvv/base/pr110299-1.h: New test.
+	* gcc.target/riscv/rvv/base/pr110299-2.c: New test.
+	* gcc.target/riscv/rvv/base/pr110299-2.h: New test.
+	* gcc.target/riscv/rvv/base/pr110299-3.c: New test.
+	* gcc.target/riscv/rvv/base/pr110299-3.h: New test.
+	* gcc.target/riscv/rvv/base/pr110299-4.c: New test.
+	* gcc.target/riscv/rvv/base/pr110299-4.h: New test.
+
+2023-06-19  Pan Li  <pan2.li@intel.com>
+
+	PR target/110277
+	* gcc.target/riscv/rvv/base/pr110277-1.c: New test.
+	* gcc.target/riscv/rvv/base/pr110277-1.h: New test.
+	* gcc.target/riscv/rvv/base/pr110277-2.c: New test.
+	* gcc.target/riscv/rvv/base/pr110277-2.h: New test.
+
+2023-06-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* gcc.dg/tree-ssa/predcom-2.c: Avoid vectors on amdgcn.
+	* gcc.dg/unroll-8.c: Likewise.
+	* gcc.dg/vect/slp-26.c: Change expected results on amdgdn.
+	* lib/target-supports.exp
+	(check_effective_target_vect_int_mod): Add amdgcn.
+	(check_effective_target_divmod): Likewise.
+	* gcc.target/gcn/simd-math-3-16.c: New test.
+	* gcc.target/gcn/simd-math-3-2.c: New test.
+	* gcc.target/gcn/simd-math-3-32.c: New test.
+	* gcc.target/gcn/simd-math-3-4.c: New test.
+	* gcc.target/gcn/simd-math-3-8.c: New test.
+	* gcc.target/gcn/simd-math-3-char-16.c: New test.
+	* gcc.target/gcn/simd-math-3-char-2.c: New test.
+	* gcc.target/gcn/simd-math-3-char-32.c: New test.
+	* gcc.target/gcn/simd-math-3-char-4.c: New test.
+	* gcc.target/gcn/simd-math-3-char-8.c: New test.
+	* gcc.target/gcn/simd-math-3-char-run-16.c: New test.
+	* gcc.target/gcn/simd-math-3-char-run-2.c: New test.
+	* gcc.target/gcn/simd-math-3-char-run-32.c: New test.
+	* gcc.target/gcn/simd-math-3-char-run-4.c: New test.
+	* gcc.target/gcn/simd-math-3-char-run-8.c: New test.
+	* gcc.target/gcn/simd-math-3-char-run.c: New test.
+	* gcc.target/gcn/simd-math-3-char.c: New test.
+	* gcc.target/gcn/simd-math-3-long-16.c: New test.
+	* gcc.target/gcn/simd-math-3-long-2.c: New test.
+	* gcc.target/gcn/simd-math-3-long-32.c: New test.
+	* gcc.target/gcn/simd-math-3-long-4.c: New test.
+	* gcc.target/gcn/simd-math-3-long-8.c: New test.
+	* gcc.target/gcn/simd-math-3-long-run-16.c: New test.
+	* gcc.target/gcn/simd-math-3-long-run-2.c: New test.
+	* gcc.target/gcn/simd-math-3-long-run-32.c: New test.
+	* gcc.target/gcn/simd-math-3-long-run-4.c: New test.
+	* gcc.target/gcn/simd-math-3-long-run-8.c: New test.
+	* gcc.target/gcn/simd-math-3-long-run.c: New test.
+	* gcc.target/gcn/simd-math-3-long.c: New test.
+	* gcc.target/gcn/simd-math-3-run-16.c: New test.
+	* gcc.target/gcn/simd-math-3-run-2.c: New test.
+	* gcc.target/gcn/simd-math-3-run-32.c: New test.
+	* gcc.target/gcn/simd-math-3-run-4.c: New test.
+	* gcc.target/gcn/simd-math-3-run-8.c: New test.
+	* gcc.target/gcn/simd-math-3-run.c: New test.
+	* gcc.target/gcn/simd-math-3-short-16.c: New test.
+	* gcc.target/gcn/simd-math-3-short-2.c: New test.
+	* gcc.target/gcn/simd-math-3-short-32.c: New test.
+	* gcc.target/gcn/simd-math-3-short-4.c: New test.
+	* gcc.target/gcn/simd-math-3-short-8.c: New test.
+	* gcc.target/gcn/simd-math-3-short-run-16.c: New test.
+	* gcc.target/gcn/simd-math-3-short-run-2.c: New test.
+	* gcc.target/gcn/simd-math-3-short-run-32.c: New test.
+	* gcc.target/gcn/simd-math-3-short-run-4.c: New test.
+	* gcc.target/gcn/simd-math-3-short-run-8.c: New test.
+	* gcc.target/gcn/simd-math-3-short-run.c: New test.
+	* gcc.target/gcn/simd-math-3-short.c: New test.
+	* gcc.target/gcn/simd-math-3.c: New test.
+	* gcc.target/gcn/simd-math-4-char-run.c: New test.
+	* gcc.target/gcn/simd-math-4-char.c: New test.
+	* gcc.target/gcn/simd-math-4-long-run.c: New test.
+	* gcc.target/gcn/simd-math-4-long.c: New test.
+	* gcc.target/gcn/simd-math-4-run.c: New test.
+	* gcc.target/gcn/simd-math-4-short-run.c: New test.
+	* gcc.target/gcn/simd-math-4-short.c: New test.
+	* gcc.target/gcn/simd-math-4.c: New test.
+	* gcc.target/gcn/simd-math-5-16.c: New test.
+	* gcc.target/gcn/simd-math-5-32.c: New test.
+	* gcc.target/gcn/simd-math-5-4.c: New test.
+	* gcc.target/gcn/simd-math-5-8.c: New test.
+	* gcc.target/gcn/simd-math-5-char-16.c: New test.
+	* gcc.target/gcn/simd-math-5-char-32.c: New test.
+	* gcc.target/gcn/simd-math-5-char-4.c: New test.
+	* gcc.target/gcn/simd-math-5-char-8.c: New test.
+	* gcc.target/gcn/simd-math-5-char-run-16.c: New test.
+	* gcc.target/gcn/simd-math-5-char-run-32.c: New test.
+	* gcc.target/gcn/simd-math-5-char-run-4.c: New test.
+	* gcc.target/gcn/simd-math-5-char-run-8.c: New test.
+	* gcc.target/gcn/simd-math-5-char-run.c: New test.
+	* gcc.target/gcn/simd-math-5-char.c: New test.
+	* gcc.target/gcn/simd-math-5-long-16.c: New test.
+	* gcc.target/gcn/simd-math-5-long-32.c: New test.
+	* gcc.target/gcn/simd-math-5-long-4.c: New test.
+	* gcc.target/gcn/simd-math-5-long-8.c: New test.
+	* gcc.target/gcn/simd-math-5-long-run-16.c: New test.
+	* gcc.target/gcn/simd-math-5-long-run-32.c: New test.
+	* gcc.target/gcn/simd-math-5-long-run-4.c: New test.
+	* gcc.target/gcn/simd-math-5-long-run-8.c: New test.
+	* gcc.target/gcn/simd-math-5-long-run.c: New test.
+	* gcc.target/gcn/simd-math-5-long.c: New test.
+	* gcc.target/gcn/simd-math-5-run-16.c: New test.
+	* gcc.target/gcn/simd-math-5-run-32.c: New test.
+	* gcc.target/gcn/simd-math-5-run-4.c: New test.
+	* gcc.target/gcn/simd-math-5-run-8.c: New test.
+	* gcc.target/gcn/simd-math-5-run.c: New test.
+	* gcc.target/gcn/simd-math-5-short-16.c: New test.
+	* gcc.target/gcn/simd-math-5-short-32.c: New test.
+	* gcc.target/gcn/simd-math-5-short-4.c: New test.
+	* gcc.target/gcn/simd-math-5-short-8.c: New test.
+	* gcc.target/gcn/simd-math-5-short-run-16.c: New test.
+	* gcc.target/gcn/simd-math-5-short-run-32.c: New test.
+	* gcc.target/gcn/simd-math-5-short-run-4.c: New test.
+	* gcc.target/gcn/simd-math-5-short-run-8.c: New test.
+	* gcc.target/gcn/simd-math-5-short-run.c: New test.
+	* gcc.target/gcn/simd-math-5-short.c: New test.
+	* gcc.target/gcn/simd-math-5.c: New test.
+
+2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/vect-bic-bitmask-2.c: Remove -save-temps.
+	* gcc.dg/vect/vect-bic-bitmask-3.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-4.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-5.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-6.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-8.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-9.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-10.c: Likewise.
+	* gcc.dg/vect/vect-bic-bitmask-11.c: Likewise.
+
+2023-06-19  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110298
+	* gcc.dg/torture/pr110298.c: New testcase.
+
+2023-06-19  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* gcc.target/aarch64/simd/low-high-combine_1.c: New test.
+
+2023-06-19  Senthil Kumar Selvaraj  <saaadhu@gcc.gnu.org>
+
+	PR target/105523
+	* lib/target-supports.exp
+	(check_effective_target_keeps_null_pointer_checks): Add
+	avr.
+	* gcc.target/avr/pr105523.c: New test.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/unop/abs-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/abs-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: New test.
+	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: New test.
+	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h: New test.
+	* gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Add unops.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Add FP.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: New test.
+	* lib/target-supports.exp: Add riscv_vector_hw and riscv_zvfh_hw
+	target selectors.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ensure
+	that no sext insns are present.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c:
+	New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c:
+	New test.
+	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: New file.
+
+2023-06-19  Robin Dapp  <rdapp@ventanamicro.com>
+
+	* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Adapt for
+	(u)int8_t.
+	* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/shift-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vand-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vor-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Dito.
+	* gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Dito.
+
+2023-06-19  Senthil Kumar Selvaraj  <saaadhu@gcc.gnu.org>
+
+	PR target/110086
+	* gcc.target/avr/pr110086.c: New test.
+
+2023-06-19  Jiufu Guo  <guojiufu@linux.ibm.com>
+
+	* gcc.target/powerpc/const_anchors.c: New test.
+	* gcc.target/powerpc/try_const_anchors_ice.c: New test.
+
+2023-06-19  liuhongt  <hongtao.liu@intel.com>
+
+	* gcc.target/i386/avx512bw-vpackssdw-3.c: New test.
+	* gcc.target/i386/avx512bw-vpacksswb-3.c: New test.
+
+2023-06-18  Jan Hubicka  <jh@suse.cz>
+
+	* gcc.dg/lto/20091013-1_0.c: Disable stringop-overread warning.
+
+2023-06-18  Honza  <jh@ryzen3.suse.cz>
+
+	PR tree-optimization/109849
+	* g++.dg/ipa/devirt-45.C: Update template.
+
+2023-06-18  yulong  <shiyulong@iscas.ac.cn>
+
+	* gcc.target/riscv/rvv/base/tuple-28.c: New test.
+	* gcc.target/riscv/rvv/base/tuple-29.c: New test.
+	* gcc.target/riscv/rvv/base/tuple-30.c: New test.
+	* gcc.target/riscv/rvv/base/tuple-31.c: New test.
+	* gcc.target/riscv/rvv/base/tuple-32.c: New test.
+
+2023-06-17  Roger Sayle  <roger@nextmovesoftware.com>
+
+	* gcc.target/i386/sse2-v1ti-mov-2.c: New test case.
+
+2023-06-16  Pan Li  <pan2.li@intel.com>
+
+	PR target/110265
+	* gcc.target/riscv/rvv/base/pr110265-1.c: New test.
+	* gcc.target/riscv/rvv/base/pr110265-1.h: New test.
+	* gcc.target/riscv/rvv/base/pr110265-2.c: New test.
+	* gcc.target/riscv/rvv/base/pr110265-2.h: New test.
+	* gcc.target/riscv/rvv/base/pr110265-3.c: New test.
+
+2023-06-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/79173
+	* gcc.target/i386/pr79173-11.c: New test.
+	* gcc.dg/builtin-addc-1.c: New test.
+
+2023-06-16  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/110271
+	* gcc.c-torture/compile/pr110271.c: New test.
+
+2023-06-16  Roger Sayle  <roger@nextmovesoftware.com>
+	    Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/31985
+	* gcc.target/i386/pr31985.c: New test case.
+
+2023-06-16  Alex Coplan  <alex.coplan@arm.com>
+
+	* g++.dg/cpp0x/enum40.C: Adjust expected diagnostics.
+	* g++.dg/cpp0x/forw_enum6.C: Likewise.
+	* g++.dg/cpp0x/elab-enum-base.C: New test.
+
+2023-06-16  Simon Dardis  <simon.dardis@imgtec.com>
+
+	* gcc.target/mips/code-readable-attr-1.c: New test.
+	* gcc.target/mips/code-readable-attr-2.c: New test.
+	* gcc.target/mips/code-readable-attr-3.c: New test.
+	* gcc.target/mips/code-readable-attr-4.c: New test.
+	* gcc.target/mips/code-readable-attr-5.c: New test.
+
+2023-06-16  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/110269
+	* gcc.dg/tree-ssa/pr110269.c: New testcase.
+
+2023-06-16  David Malcolm  <dmalcolm@redhat.com>
+
+	PR c/107583
+	* c-c++-common/spellcheck-pr107583.c: New test.
+
 2023-06-15  Andrew Pinski  <apinski@marvell.com>
 
 	PR tree-optimization/110266
diff --git a/gcc/testsuite/c-c++-common/Wlogical-not-parentheses-2.c b/gcc/testsuite/c-c++-common/Wlogical-not-parentheses-2.c
index ba8dce8..2d93820 100644
--- a/gcc/testsuite/c-c++-common/Wlogical-not-parentheses-2.c
+++ b/gcc/testsuite/c-c++-common/Wlogical-not-parentheses-2.c
@@ -12,6 +12,8 @@ foo (int aaa, int bbb)
 /* { dg-begin-multiline-output "" }
    r += !aaa == bbb;
              ^~
+   { dg-end-multiline-output "" } */
+/* { dg-begin-multiline-output "" }
    r += !aaa == bbb;
         ^~~~
         (   )
diff --git a/gcc/testsuite/c-c++-common/asan/pr106558.c b/gcc/testsuite/c-c++-common/asan/pr106558.c
index d82b2dc..c8cefdf 100644
--- a/gcc/testsuite/c-c++-common/asan/pr106558.c
+++ b/gcc/testsuite/c-c++-common/asan/pr106558.c
@@ -8,7 +8,7 @@ int **c = &b;
 int d[1];
 int *e = &d[1];
 
-static int f(int *g) {
+static void f(int *g) {
   *b = e;
   *c = e;
   *b = 2;
diff --git a/gcc/testsuite/c-c++-common/cpp/line-2.c b/gcc/testsuite/c-c++-common/cpp/line-2.c
index 364ad0e..3ce2334 100644
--- a/gcc/testsuite/c-c++-common/cpp/line-2.c
+++ b/gcc/testsuite/c-c++-common/cpp/line-2.c
@@ -8,4 +8,4 @@ int line4;
 
 // { dg-regexp {In file included from <command-line>:\n[^\n]*/line-2.h:4:2: error: #error wrong\n} }
 
-// { dg-regexp {[^\n]*/line-2.c:3:11: error: macro "bill" passed 1 arguments, but takes just 0\n[^\n]*/line-2.h:3: note: macro "bill" defined here\n} }
+// { dg-regexp {[^\n]*/line-2.c:3:11: error: macro "bill" passed 1 arguments, but takes just 0\n[^\n]*/line-2.h:3:9: note: macro "bill" defined here\n} }
diff --git a/gcc/testsuite/c-c++-common/cpp/line-3.c b/gcc/testsuite/c-c++-common/cpp/line-3.c
index b254ae4..b067292 100644
--- a/gcc/testsuite/c-c++-common/cpp/line-3.c
+++ b/gcc/testsuite/c-c++-common/cpp/line-3.c
@@ -15,6 +15,6 @@ int line4;
 
 // { dg-regexp {In file included from <command-line>:\n[^\n]*/line-2.h:4:2: error: #error wrong\n} }
 
-// { dg-regexp {[^\n]*/line-3.c:3:11: error: macro "bill" passed 1 arguments, but takes just 0\n[^\n]*/line-2.h:3: note: macro "bill" defined here\n} }
+// { dg-regexp {[^\n]*/line-3.c:3:11: error: macro "bill" passed 1 arguments, but takes just 0\n[^\n]*/line-2.h:3:9: note: macro "bill" defined here\n} }
 
 // { dg-options "-fpreprocessed -fdirectives-only" }
diff --git a/gcc/testsuite/c-c++-common/cpp/macro-arg-count-1.c b/gcc/testsuite/c-c++-common/cpp/macro-arg-count-1.c
index 7773c47..103e88e 100644
--- a/gcc/testsuite/c-c++-common/cpp/macro-arg-count-1.c
+++ b/gcc/testsuite/c-c++-common/cpp/macro-arg-count-1.c
@@ -9,7 +9,7 @@ void test_1 ()
    MACRO_1(42);
              ^
      { dg-end-multiline-output "" } */
-  /* { dg-message "-: macro .MACRO_1. defined here" "" { target *-*-* } def_of_MACRO_1 }
+  /* { dg-message "macro .MACRO_1. defined here" "" { target *-*-* } def_of_MACRO_1 }
   /* { dg-begin-multiline-output "" }
  #define MACRO_1(X,Y)
  
@@ -33,7 +33,7 @@ void test_2 ()
    MACRO_2(1, 2, 3);
                   ^
      { dg-end-multiline-output "" } */
-  /* { dg-message "-: macro .MACRO_2. defined here" "" { target *-*-* } def_of_MACRO_2 }
+  /* { dg-message "macro .MACRO_2. defined here" "" { target *-*-* } def_of_MACRO_2 }
   /* { dg-begin-multiline-output "" }
  #define MACRO_2(X,Y)
  
diff --git a/gcc/testsuite/c-c++-common/cpp/macro-ranges.c b/gcc/testsuite/c-c++-common/cpp/macro-ranges.c
new file mode 100644
index 0000000..72b026f
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/cpp/macro-ranges.c
@@ -0,0 +1,52 @@
+/* { dg-do preprocess } */
+/* { dg-additional-options "-fdiagnostics-show-caret -Wunused-macros -Wbuiltin-macro-redefined" } */
+
+/* Verify that we output range information for diagnostics involving
+   macro definitions.  */
+
+#undef __TIME__ /* { dg-warning {undefining "__TIME__"} } */
+/* { dg-begin-multiline-output "" }
+ #undef __TIME__
+        ^~~~~~~~
+/* { dg-end-multiline-output "" } */
+
+#define XYZ 123 /* { dg-warning {macro "XYZ" is not used} } */
+/* { dg-begin-multiline-output "" }
+ #define XYZ 123
+         ^~~
+/* { dg-end-multiline-output "" } */
+
+#define MACRO initial_definition /* { dg-line def_line } */
+
+/* This locus is output first for the unused warning... */
+/* { dg-warning {macro "MACRO" is not used} "" { target *-*-* } def_line } */
+/* { dg-begin-multiline-output "" }
+ #define MACRO initial_definition
+         ^~~~~
+/* { dg-end-multiline-output "" } */
+
+/* ...then a second time for the redefinition warning.  */
+/* { dg-note {this is the location of the previous definition} "" { target *-*-* } def_line } */
+/* { dg-begin-multiline-output "" }
+ #define MACRO initial_definition
+         ^~~~~
+/* { dg-end-multiline-output "" } */
+
+#define MACRO /* { dg-warning {"MACRO" redefined} } */
+/* { dg-begin-multiline-output "" }
+ #define MACRO
+         ^~~~~
+{ dg-end-multiline-output "" } */
+
+#define MACRO2(x,y) x /* { dg-note {macro "MACRO2" defined here} } */
+/* { dg-begin-multiline-output "" }
+ #define MACRO2(x,y)
+         ^~~~~~
+{ dg-end-multiline-output "" } */
+
+MACRO2(MACRO, MACRO)
+MACRO2(MACRO) /* { dg-error {macro "MACRO2" requires 2 arguments, but only 1 given} } */
+/* { dg-begin-multiline-output "" }
+ MACRO2(MACRO)
+             ^
+{ dg-end-multiline-output "" } */
diff --git a/gcc/testsuite/c-c++-common/cpp/pr58844-1.c b/gcc/testsuite/c-c++-common/cpp/pr58844-1.c
index 2a2e277..3abf8a7 100644
--- a/gcc/testsuite/c-c++-common/cpp/pr58844-1.c
+++ b/gcc/testsuite/c-c++-common/cpp/pr58844-1.c
@@ -4,5 +4,5 @@
 
 #define A x######x
 int A = 1;
-#define A x######x	/* { dg-message "-:previous definition" } */
-#define A x##x		/* { dg-warning "-:redefined" } */
+#define A x######x	/* { dg-message "previous definition" } */
+#define A x##x		/* { dg-warning "redefined" } */
diff --git a/gcc/testsuite/c-c++-common/cpp/pr58844-2.c b/gcc/testsuite/c-c++-common/cpp/pr58844-2.c
index 52993b3..1e21915 100644
--- a/gcc/testsuite/c-c++-common/cpp/pr58844-2.c
+++ b/gcc/testsuite/c-c++-common/cpp/pr58844-2.c
@@ -4,5 +4,5 @@
 
 #define A x######x
 int A = 1;
-#define A x######x	/* { dg-message "-:previous definition" } */
-#define A x##x		/* { dg-warning "-:redefined" } */
+#define A x######x	/* { dg-message "previous definition" } */
+#define A x##x		/* { dg-warning "redefined" } */
diff --git a/gcc/testsuite/c-c++-common/cpp/warning-zero-location.c b/gcc/testsuite/c-c++-common/cpp/warning-zero-location.c
index 57544b6..2b9c9a9 100644
--- a/gcc/testsuite/c-c++-common/cpp/warning-zero-location.c
+++ b/gcc/testsuite/c-c++-common/cpp/warning-zero-location.c
@@ -3,6 +3,6 @@
    { dg-do compile }
  */
 
-#define _GNU_SOURCE 	/* { dg-warning "-:redefined" } */
+#define _GNU_SOURCE 	/* { dg-warning "redefined" } */
 
 /* { dg-message "" "#define _GNU_SOURCE" {target *-*-* } 0 } */
diff --git a/gcc/testsuite/c-c++-common/pragma-diag-14.c b/gcc/testsuite/c-c++-common/pragma-diag-14.c
index 618e7e1..45dc4a3 100644
--- a/gcc/testsuite/c-c++-common/pragma-diag-14.c
+++ b/gcc/testsuite/c-c++-common/pragma-diag-14.c
@@ -5,5 +5,5 @@
    location was not tracked properly with -E or -save-temps; check that it works
    now.  */
 
-#define X /* { dg-warning "-:-Wunused-macros" } */
+#define X /* { dg-warning "-Wunused-macros" } */
 #pragma GCC diagnostic ignored "-Wunused-macros"
diff --git a/gcc/testsuite/c-c++-common/pragma-diag-15.c b/gcc/testsuite/c-c++-common/pragma-diag-15.c
index 8ffff88..5cb8c35 100644
--- a/gcc/testsuite/c-c++-common/pragma-diag-15.c
+++ b/gcc/testsuite/c-c++-common/pragma-diag-15.c
@@ -9,5 +9,5 @@
    because the location of the macro definition is incorrectly set.  This is a
    separate issue, will resolve it in a later patch.  */
 
-#define X /* { dg-warning "-:-Wunused-macros" } */
+#define X /* { dg-warning "-Wunused-macros" } */
 #pragma GCC diagnostic ignored "-Wunused-macros"
diff --git a/gcc/testsuite/g++.dg/debug/pr110295.C b/gcc/testsuite/g++.dg/debug/pr110295.C
new file mode 100644
index 0000000..10cad55
--- /dev/null
+++ b/gcc/testsuite/g++.dg/debug/pr110295.C
@@ -0,0 +1,19 @@
+// { dg-do compile }
+// { dg-options "-g" }
+
+template <typename T>
+struct QCachedT
+{
+  void operator delete(void *, T *) {}
+};
+template<int a>
+void exercise()
+{
+  struct thing_t
+    : QCachedT<thing_t>
+  {
+  };
+  thing_t *list[1];
+  new thing_t; // { dg-warning "" }
+}
+int main() { exercise<1>(); }
diff --git a/gcc/testsuite/g++.dg/ipa/devirt-45.C b/gcc/testsuite/g++.dg/ipa/devirt-45.C
index ce415e7..c26be21 100644
--- a/gcc/testsuite/g++.dg/ipa/devirt-45.C
+++ b/gcc/testsuite/g++.dg/ipa/devirt-45.C
@@ -37,5 +37,5 @@ int main()
 }
 
 /* One invocation is A::foo () other is B::foo () even though the type is destroyed and rebuilt in test() */
-/* { dg-final { scan-ipa-dump-times "Discovered a virtual call to a known target\[^\\n\]*A::foo" 1 "inline"  } } */
+/* { dg-final { scan-ipa-dump-times "Discovered a virtual call to a known target\[^\\n\]*A::foo" 2 "inline"  } } */
 /* { dg-final { scan-ipa-dump-times "Discovered a virtual call to a known target\[^\\n\]*B::foo" 1 "inline"  } } */
diff --git a/gcc/testsuite/g++.dg/modules/macro-2_d.C b/gcc/testsuite/g++.dg/modules/macro-2_d.C
index 04b80fb..e78fc7c 100644
--- a/gcc/testsuite/g++.dg/modules/macro-2_d.C
+++ b/gcc/testsuite/g++.dg/modules/macro-2_d.C
@@ -8,7 +8,7 @@ import "macro-2_b.H";
 int FOO_OK = BAR_OK(1);
 
 int BAR_BAD;
-// { dg-regexp {[^\n]*macro-2_d.C:10:5: error: inconsistent imported macro definition 'BAR_BAD'\nIn module [^\n]*macro-2_a.H, imported at [^\n]*macro-2_d.C:5:\n[^\n]*macro-2_a.H:11: note: '#define BAR_BAD\(BAZ\) BINKY\(2\)'\nIn module [^\n]*macro-2_b.H, imported at [^\n]*macro-2_d.C:6:\n[^\n]*macro-2_b.H:21: note: '#define BAR_BAD\(BAZ\) BINKY\(3\)'\n} }
+// { dg-regexp {[^\n]*macro-2_d.C:10:5: error: inconsistent imported macro definition 'BAR_BAD'\nIn module [^\n]*macro-2_a.H, imported at [^\n]*macro-2_d.C:5:\n[^\n]*macro-2_a.H:11:9: note: '#define BAR_BAD\(BAZ\) BINKY\(2\)'\nIn module [^\n]*macro-2_b.H, imported at [^\n]*macro-2_d.C:6:\n[^\n]*macro-2_b.H:21:9: note: '#define BAR_BAD\(BAZ\) BINKY\(3\)'\n} }
 
 int FOO_BAD;
-// { dg-regexp {[^\n]*macro-2_d.C:13:5: error: inconsistent imported macro definition 'FOO_BAD'\nIn module [^\n]*macro-2_a.H, imported at [^\n]*macro-2_d.C:5:\n[^\n]*macro-2_a.H:10: note: '#define FOO_BAD foo'\nIn module [^\n]*macro-2_b.H, imported at [^\n]*macro-2_d.C:6:\n[^\n]*macro-2_b.H:20: note: '#define FOO_BAD foot'\n} }
+// { dg-regexp {[^\n]*macro-2_d.C:13:5: error: inconsistent imported macro definition 'FOO_BAD'\nIn module [^\n]*macro-2_a.H, imported at [^\n]*macro-2_d.C:5:\n[^\n]*macro-2_a.H:10:9: note: '#define FOO_BAD foo'\nIn module [^\n]*macro-2_b.H, imported at [^\n]*macro-2_d.C:6:\n[^\n]*macro-2_b.H:20:9: note: '#define FOO_BAD foot'\n} }
diff --git a/gcc/testsuite/g++.dg/modules/macro-4_d.C b/gcc/testsuite/g++.dg/modules/macro-4_d.C
index bff9494..d9c08ce 100644
--- a/gcc/testsuite/g++.dg/modules/macro-4_d.C
+++ b/gcc/testsuite/g++.dg/modules/macro-4_d.C
@@ -3,6 +3,6 @@
 import "macro-4_b.H";
 import "macro-4_a.H";
 
-// { dg-regexp {[^\n]*macro-4_d.C: warning: inconsistent imported macro definition 'TWO' \[-Winvalid-imported-macros\]\nIn module [^\n]*macro-4_b.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_b.H:[0-9]*: note: .#define TWO 2a.\nIn module [^\n]*macro-4_a.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_a.H:[0-9]*: note: .#define TWO 2.\n} }
+// { dg-regexp {[^\n]*macro-4_d.C: warning: inconsistent imported macro definition 'TWO' \[-Winvalid-imported-macros\]\nIn module [^\n]*macro-4_b.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_b.H:[0-9]*:[0-9]*: note: .#define TWO 2a.\nIn module [^\n]*macro-4_a.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_a.H:[0-9]*:[0-9]*: note: .#define TWO 2.\n} }
 
-// { dg-regexp {[^\n]*macro-4_d.C: warning: inconsistent imported macro definition 'THREE' \[-Winvalid-imported-macros\]\nIn module [^\n]*macro-4_b.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_b.H:[0-9]*: note: .#define THREE 3b.\nIn module [^\n]*macro-4_a.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_a.H:[0-9]*: note: .#define THREE 3.\n} }
+// { dg-regexp {[^\n]*macro-4_d.C: warning: inconsistent imported macro definition 'THREE' \[-Winvalid-imported-macros\]\nIn module [^\n]*macro-4_b.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_b.H:[0-9]*:[0-9]*: note: .#define THREE 3b.\nIn module [^\n]*macro-4_a.H, imported at [^\n]*macro-4_d.C:[0-9]*:\n[^\n]*macro-4_a.H:[0-9]*:[0-9]*: note: .#define THREE 3.\n} }
diff --git a/gcc/testsuite/g++.dg/modules/macro-4_e.C b/gcc/testsuite/g++.dg/modules/macro-4_e.C
index 38fa6c7..392387f 100644
--- a/gcc/testsuite/g++.dg/modules/macro-4_e.C
+++ b/gcc/testsuite/g++.dg/modules/macro-4_e.C
@@ -10,4 +10,4 @@ int stop;
 #error bah!
 #endif
 
-// { dg-regexp {[^\n]*macro-4_e.C: warning: inconsistent imported macro definition 'TWO' \[-Winvalid-imported-macros\]\nIn module [^\n]*macro-4_b.H, imported at [^\n]*macro-4_e.C:[0-9]*:\n[^\n]*macro-4_b.H:[0-9]*: note: .#define TWO 2a.\nIn module [^\n]*macro-4_a.H, imported at [^\n]*macro-4_e.C:[0-9]*:\n[^\n]*macro-4_a.H:[0-9]*: note: .#define TWO 2.\n} }
+// { dg-regexp {[^\n]*macro-4_e.C: warning: inconsistent imported macro definition 'TWO' \[-Winvalid-imported-macros\]\nIn module [^\n]*macro-4_b.H, imported at [^\n]*macro-4_e.C:[0-9]*:\n[^\n]*macro-4_b.H:[0-9]*:[0-9]*: note: .#define TWO 2a.\nIn module [^\n]*macro-4_a.H, imported at [^\n]*macro-4_e.C:[0-9]*:\n[^\n]*macro-4_a.H:[0-9]*:[0-9]*: note: .#define TWO 2.\n} }
diff --git a/gcc/testsuite/g++.dg/spellcheck-macro-ordering.C b/gcc/testsuite/g++.dg/spellcheck-macro-ordering.C
index bbd41f4..59e9f8a 100644
--- a/gcc/testsuite/g++.dg/spellcheck-macro-ordering.C
+++ b/gcc/testsuite/g++.dg/spellcheck-macro-ordering.C
@@ -13,4 +13,4 @@ class DocTargetDriver {
 };
 
 #define OVERRIDE override
-// { dg-message "-:it was later defined here" "" { target *-*-* } .-1 }
+// { dg-message "9:it was later defined here" "" { target *-*-* } .-1 }
diff --git a/gcc/testsuite/g++.target/i386/pr79173-1.C b/gcc/testsuite/g++.target/i386/pr79173-1.C
new file mode 100644
index 0000000..e6fc7cb
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr79173-1.C
@@ -0,0 +1,33 @@
+// PR middle-end/79173
+// { dg-do compile { target c++11 } }
+// { dg-options "-O2 -fno-stack-protector -masm=att" }
+// { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } }
+// { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+// { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+// { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+// { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } }
+
+template <typename T>
+inline constexpr T
+uaddc (T x, T y, T carry_in, T &carry_out) noexcept
+{
+  [[gnu::assume (carry_in <= 1)]];
+  x += y;
+  carry_out = x < y;
+  x += carry_in;
+  carry_out += x < carry_in;
+  return x;
+}
+
+void
+foo (unsigned long *p, unsigned long *q)
+{
+  unsigned long c;
+  p[0] = uaddc (p[0], q[0], 0UL, c);
+  p[1] = uaddc (p[1], q[1], c, c);
+  p[2] = uaddc (p[2], q[2], c, c);
+  p[3] = uaddc (p[3], q[3], c, c);
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110271.c b/gcc/testsuite/gcc.c-torture/compile/pr110271.c
new file mode 100644
index 0000000..0cb91be
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr110271.c
@@ -0,0 +1,24 @@
+/* PR tree-optimization/110271 */
+
+unsigned a, b, c, d, e;
+
+void
+foo (unsigned *x, int y, unsigned int *z)
+{
+  for (int i = 0; i < y; i++)
+    {
+      b += d;
+      a += b < d;
+      a += c = (__PTRDIFF_TYPE__) x > 3;
+      d = z[1] + (a < c);
+      a += e;
+      d += a < e;
+    }
+}
+
+void
+bar (unsigned int *z)
+{
+  unsigned *x = x;
+  foo (x, 9, z);
+}
diff --git a/gcc/testsuite/gcc.dg/analyzer/malloc-macro-inline-events.c b/gcc/testsuite/gcc.dg/analyzer/malloc-macro-inline-events.c
index f08aee6..9134bb4 100644
--- a/gcc/testsuite/gcc.dg/analyzer/malloc-macro-inline-events.c
+++ b/gcc/testsuite/gcc.dg/analyzer/malloc-macro-inline-events.c
@@ -12,11 +12,6 @@ int test (void *ptr)
   WRAPPED_FREE (ptr); /* { dg-message "in expansion of macro 'WRAPPED_FREE'" } */
   WRAPPED_FREE (ptr); /* { dg-message "in expansion of macro 'WRAPPED_FREE'" } */
 
-  /* Erase the spans indicating the header file
-     (to avoid embedding path assumptions).  */
-  /* { dg-regexp "\[^|\]+/malloc-macro.h:\[0-9\]+:\[0-9\]+:" } */
-  /* { dg-regexp "\[^|\]+/malloc-macro.h:\[0-9\]+:\[0-9\]+:" } */
-
   /* { dg-begin-multiline-output "" }
    NN | #define WRAPPED_FREE(PTR) free(PTR)
       |                           ^~~~~~~~~
diff --git a/gcc/testsuite/gcc.dg/builtin-addc-1.c b/gcc/testsuite/gcc.dg/builtin-addc-1.c
new file mode 100644
index 0000000..c875d8f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/builtin-addc-1.c
@@ -0,0 +1,101 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -g" } */
+
+int
+main ()
+{
+  unsigned int c;
+  unsigned long cl;
+  unsigned long long cll;
+  if (__builtin_addc (1, 42, 0, &c) != 43 || c != 0)
+    __builtin_abort ();
+  if (__builtin_addc (1, 42, 15, &c) != 58 || c != 0)
+    __builtin_abort ();
+  if (__builtin_addc (-2U, -3U, -4U, &c) != -9U || c != 1)
+    __builtin_abort ();
+  if (__builtin_addc (-2U, 1, 0, &c) != -1U || c != 0)
+    __builtin_abort ();
+  if (__builtin_addc (-2U, 1, 1, &c) != 0 || c != 1)
+    __builtin_abort ();
+  if (__builtin_addc (-2U, 2, 0, &c) != 0 || c != 1)
+    __builtin_abort ();
+  if (__builtin_addc (-2U, 0, 2, &c) != 0 || c != 1)
+    __builtin_abort ();
+  if (__builtin_addcl (1L, 42L, 0L, &cl) != 43 || cl != 0L)
+    __builtin_abort ();
+  if (__builtin_addcl (1L, 42L, 15L, &cl) != 58 || cl != 0L)
+    __builtin_abort ();
+  if (__builtin_addcl (-2UL, -3UL, -4UL, &cl) != -9UL || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_addcl (-2UL, 1L, 0L, &cl) != -1UL || cl != 0L)
+    __builtin_abort ();
+  if (__builtin_addcl (-2UL, 1L, 1L, &cl) != 0 || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_addcl (-2UL, 2L, 0L, &cl) != 0 || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_addcl (-2UL, 0L, 2L, &cl) != 0 || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_addcll (1LL, 42LL, 0LL, &cll) != 43 || cll != 0LL)
+    __builtin_abort ();
+  if (__builtin_addcll (1LL, 42LL, 15LL, &cll) != 58 || cll != 0LL)
+    __builtin_abort ();
+  if (__builtin_addcll (-2ULL, -3ULL, -4ULL, &cll) != -9ULL || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_addcll (-2ULL, 1LL, 0LL, &cll) != -1ULL || cll != 0LL)
+    __builtin_abort ();
+  if (__builtin_addcll (-2ULL, 1LL, 1LL, &cll) != 0 || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_addcll (-2ULL, 2LL, 0LL, &cll) != 0 || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_addcll (-2ULL, 0LL, 2LL, &cll) != 0 || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_subc (42, 42, 0, &c) != 0 || c != 0)
+    __builtin_abort ();
+  if (__builtin_subc (42, 42, 1, &c) != -1U || c != 1)
+    __builtin_abort ();
+  if (__builtin_subc (1, -3U, -4U, &c) != 8 || c != 1)
+    __builtin_abort ();
+  if (__builtin_subc (-2U, 1, 0, &c) != -3U || c != 0)
+    __builtin_abort ();
+  if (__builtin_subc (-2U, -1U, 0, &c) != -1U || c != 1)
+    __builtin_abort ();
+  if (__builtin_subc (-2U, -2U, 0, &c) != 0 || c != 0)
+    __builtin_abort ();
+  if (__builtin_subc (-2U, -2U, 1, &c) != -1U || c != 1)
+    __builtin_abort ();
+  if (__builtin_subc (-2U, 1, -2U, &c) != -1U || c != 1)
+    __builtin_abort ();
+  if (__builtin_subcl (42L, 42L, 0L, &cl) != 0L || cl != 0L)
+    __builtin_abort ();
+  if (__builtin_subcl (42L, 42L, 1L, &cl) != -1UL || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_subcl (1L, -3UL, -4UL, &cl) != 8L || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_subcl (-2UL, 1L, 0L, &cl) != -3UL || cl != 0L)
+    __builtin_abort ();
+  if (__builtin_subcl (-2UL, -1UL, 0L, &cl) != -1UL || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_subcl (-2UL, -2UL, 0L, &cl) != 0L || cl != 0L)
+    __builtin_abort ();
+  if (__builtin_subcl (-2UL, -2UL, 1L, &cl) != -1UL || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_subcl (-2UL, 1L, -2UL, &cl) != -1UL || cl != 1L)
+    __builtin_abort ();
+  if (__builtin_subcll (42LL, 42LL, 0LL, &cll) != 0LL || cll != 0LL)
+    __builtin_abort ();
+  if (__builtin_subcll (42LL, 42LL, 1LL, &cll) != -1ULL || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_subcll (1LL, -3ULL, -4ULL, &cll) != 8LL || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_subcll (-2ULL, 1LL, 0LL, &cll) != -3ULL || cll != 0LL)
+    __builtin_abort ();
+  if (__builtin_subcll (-2ULL, -1ULL, 0LL, &cll) != -1ULL || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_subcll (-2ULL, -2ULL, 0LL, &cll) != 0LL || cll != 0LL)
+    __builtin_abort ();
+  if (__builtin_subcll (-2ULL, -2ULL, 1LL, &cll) != -1ULL || cll != 1LL)
+    __builtin_abort ();
+  if (__builtin_subcll (-2ULL, 1LL, -2ULL, &cll) != -1ULL || cll != 1LL)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/builtin-redefine.c b/gcc/testsuite/gcc.dg/builtin-redefine.c
index 882b221..8090015 100644
--- a/gcc/testsuite/gcc.dg/builtin-redefine.c
+++ b/gcc/testsuite/gcc.dg/builtin-redefine.c
@@ -27,8 +27,8 @@
 #define __TIME__ "X"         /* Define while undefined.  */
 #define __TIME__ "X"         /* Re-define while defined.  */ /* { dg-line time_prev } */
 
-#define __TIME__ "Y"         /* { dg-warning "-:\"__TIME__\" redefined" } */
-/* { dg-message "-:previous definition" "" { target *-*-* } time_prev } */
+#define __TIME__ "Y"         /* { dg-warning "\"__TIME__\" redefined" } */
+/* { dg-message "previous definition" "" { target *-*-* } time_prev } */
 
 #undef __TIME__              /* Undefine while defined.  */
 
@@ -38,8 +38,8 @@
 #define __DATE__ "X"         /* Define while undefined.  */
 #define __DATE__ "X"         /* Re-define while defined.  */ /* { dg-line date_prev } */
 
-#define __DATE__ "Y"         /* { dg-warning "-:\"__DATE__\" redefined" } */
-/* { dg-message "-:previous definition" "" { target *-*-* } date_prev } */
+#define __DATE__ "Y"         /* { dg-warning "\"__DATE__\" redefined" } */
+/* { dg-message "previous definition" "" { target *-*-* } date_prev } */
 
 #undef __DATE__              /* Undefine while defined.  */
 
@@ -47,8 +47,8 @@
 #define __TIMESTAMP__ "X"    /* Define while already defined.  */
 #define __TIMESTAMP__ "X"    /* Re-define while defined.  */ /* { dg-line timestamp_prev } */
 
-#define __TIMESTAMP__ "Y"    /* { dg-warning "-:\"__TIMESTAMP__\" redefined" } */
-/* { dg-message "-:previous definition" "" { target *-*-* } timestamp_prev } */
+#define __TIMESTAMP__ "Y"    /* { dg-warning "\"__TIMESTAMP__\" redefined" } */
+/* { dg-message "previous definition" "" { target *-*-* } timestamp_prev } */
 
 #undef __TIMESTAMP__         /* Undefine while defined.  */
 
@@ -71,9 +71,9 @@
 /* { dg-bogus "Expected built-in is not defined" "" { target *-*-* } .-1 } */
 #endif
 
-#define __LINE__ 0           /* { dg-warning "-:\"__LINE__\" redef" } */
-#define __INCLUDE_LEVEL__ 0  /* { dg-warning "-:\"__INCLUDE_LEVEL__\" redef" } */
-#define __COUNTER__ 0        /* { dg-warning "-:\"__COUNTER__\" redef" } */
+#define __LINE__ 0           /* { dg-warning "\"__LINE__\" redef" } */
+#define __INCLUDE_LEVEL__ 0  /* { dg-warning "\"__INCLUDE_LEVEL__\" redef" } */
+#define __COUNTER__ 0        /* { dg-warning "\"__COUNTER__\" redef" } */
 
 
 int unused;  /* Silence `ISO C forbids an empty translation unit' warning.  */
diff --git a/gcc/testsuite/gcc.dg/cpp/Wunused.c b/gcc/testsuite/gcc.dg/cpp/Wunused.c
index d6f7628..ac363ad 100644
--- a/gcc/testsuite/gcc.dg/cpp/Wunused.c
+++ b/gcc/testsuite/gcc.dg/cpp/Wunused.c
@@ -15,9 +15,9 @@
 #define used3			/* { dg-bogus "used" } */
 #define used4 used4		/* { dg-bogus "used" } */
 
-#define unused5			/* { dg-warning "-:used" } */
-#define unused6			/* { dg-warning "-:used" } */
-#define unused7()		/* { dg-warning "-:used" } */
+#define unused5			/* { dg-warning "used" } */
+#define unused6			/* { dg-warning "used" } */
+#define unused7()		/* { dg-warning "used" } */
 
 #if defined used1
 #endif
diff --git a/gcc/testsuite/gcc.dg/cpp/redef2.c b/gcc/testsuite/gcc.dg/cpp/redef2.c
index 439d33a..1dbc100 100644
--- a/gcc/testsuite/gcc.dg/cpp/redef2.c
+++ b/gcc/testsuite/gcc.dg/cpp/redef2.c
@@ -17,15 +17,15 @@
 #define foo(x) x
 #define foo(x)x		/* { dg-bogus "redefined" "redefined foo" } */
 
-/* { dg-warning "-:redefined" "redef mac"     { target *-*-* } 7  }
-   { dg-warning "-:redefined" "redef mac"     { target *-*-* } 8  }
-   { dg-warning "-:redefined" "redef mac"     { target *-*-* } 9  }
-   { dg-warning "-:redefined" "redef ro"      { target *-*-* } 12 }
-   { dg-warning "-:redefined" "redef va"      { target *-*-* } 15 }
+/* { dg-warning "redefined" "redef mac"     { target *-*-* } 7  }
+   { dg-warning "redefined" "redef mac"     { target *-*-* } 8  }
+   { dg-warning "redefined" "redef mac"     { target *-*-* } 9  }
+   { dg-warning "redefined" "redef ro"      { target *-*-* } 12 }
+   { dg-warning "redefined" "redef va"      { target *-*-* } 15 }
 
-   { dg-message "-:previous"  "prev def mac"  { target *-*-* } 6  }
-   { dg-message "-:previous"  "prev def mac"  { target *-*-* } 7  }
-   { dg-message "-:previous"  "prev def mac"  { target *-*-* } 8  }
-   { dg-message "-:previous"  "prev def ro"   { target *-*-* } 11 }
-   { dg-message "-:previous"  "prev def va"   { target *-*-* } 14 }
+   { dg-message "previous"  "prev def mac"  { target *-*-* } 6  }
+   { dg-message "previous"  "prev def mac"  { target *-*-* } 7  }
+   { dg-message "previous"  "prev def mac"  { target *-*-* } 8  }
+   { dg-message "previous"  "prev def ro"   { target *-*-* } 11 }
+   { dg-message "previous"  "prev def va"   { target *-*-* } 14 }
 */
diff --git a/gcc/testsuite/gcc.dg/cpp/redef3.c b/gcc/testsuite/gcc.dg/cpp/redef3.c
index 4e4ef12..1c541a4 100644
--- a/gcc/testsuite/gcc.dg/cpp/redef3.c
+++ b/gcc/testsuite/gcc.dg/cpp/redef3.c
@@ -11,11 +11,11 @@
 #define D 1 2
 #define E
 
-/* { dg-warning "-:redefined" "redef A"      { target *-*-* } 7  }
-   { dg-warning "-:redefined" "redef B"      { target *-*-* } 9  }
-   { dg-warning "-:redefined" "redef D"      { target *-*-* } 11 }
-   { dg-warning "-:redefined" "redef E"      { target *-*-* } 12 }
-   { dg-message "-:previous"  "prev def A"   { target *-*-* } 6  }
-   { dg-message "-:previous"  "prev def B"   { target *-*-* } 8  }
-   { dg-message "-:previous"  "prev def D/E" { target *-*-* } 0  }
+/* { dg-warning "redefined" "redef A"      { target *-*-* } 7  }
+   { dg-warning "redefined" "redef B"      { target *-*-* } 9  }
+   { dg-warning "redefined" "redef D"      { target *-*-* } 11 }
+   { dg-warning "redefined" "redef E"      { target *-*-* } 12 }
+   { dg-message "previous"  "prev def A"   { target *-*-* } 6  }
+   { dg-message "previous"  "prev def B"   { target *-*-* } 8  }
+   { dg-message "previous"  "prev def D/E" { target *-*-* } 0  }
 */
diff --git a/gcc/testsuite/gcc.dg/cpp/redef4.c b/gcc/testsuite/gcc.dg/cpp/redef4.c
index aa6729b..b34635b 100644
--- a/gcc/testsuite/gcc.dg/cpp/redef4.c
+++ b/gcc/testsuite/gcc.dg/cpp/redef4.c
@@ -4,41 +4,41 @@
 /* { dg-do preprocess } */
 /* { dg-options "" } */
 
-#define str(x) #x /* { dg-message "-:previous definition" } */
-#define str(x) %: x /* { dg-warning "-:redefined" } */
+#define str(x) #x /* { dg-message "previous definition" } */
+#define str(x) %: x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) #x /* { dg-message "-:previous definition" } */
-#define str(x) # x /* { dg-warning "-:redefined" } */
+#define str(x) #x /* { dg-message "previous definition" } */
+#define str(x) # x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) #x /* { dg-message "-:previous definition" } */
-#define str(x) %: x /* { dg-warning "-:redefined" } */
+#define str(x) #x /* { dg-message "previous definition" } */
+#define str(x) %: x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) %:x /* { dg-message "-:previous definition" } */
-#define str(x) #x /* { dg-warning "-:redefined" } */
+#define str(x) %:x /* { dg-message "previous definition" } */
+#define str(x) #x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) %:x /* { dg-message "-:previous definition" } */
-#define str(x) %: x /* { dg-warning "-:redefined" } */
+#define str(x) %:x /* { dg-message "previous definition" } */
+#define str(x) %: x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) %:x /* { dg-message "-:previous definition" } */
-#define str(x) # x /* { dg-warning "-:redefined" } */
+#define str(x) %:x /* { dg-message "previous definition" } */
+#define str(x) # x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) %:x /* { dg-message "-:previous definition" } */
-#define str(x) %: x /* { dg-warning "-:redefined" } */
+#define str(x) %:x /* { dg-message "previous definition" } */
+#define str(x) %: x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) # x /* { dg-message "-:previous definition" } */
-#define str(x) #x /* { dg-warning "-:redefined" } */
+#define str(x) # x /* { dg-message "previous definition" } */
+#define str(x) #x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) # x /* { dg-message "-:previous definition" } */
-#define str(x) %: x /* { dg-warning "-:redefined" } */
+#define str(x) # x /* { dg-message "previous definition" } */
+#define str(x) %: x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) # x /* { dg-message "-:previous definition" } */
-#define str(x) %: x /* { dg-warning "-:redefined" } */
+#define str(x) # x /* { dg-message "previous definition" } */
+#define str(x) %: x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) %: x /* { dg-message "-:previous definition" } */
-#define str(x) #x /* { dg-warning "-:redefined" } */
+#define str(x) %: x /* { dg-message "previous definition" } */
+#define str(x) #x /* { dg-warning "redefined" } */
 #undef str
-#define str(x) %: x /* { dg-message "-:previous definition" } */
-#define str(x) # x /* { dg-warning "-:redefined" } */
+#define str(x) %: x /* { dg-message "previous definition" } */
+#define str(x) # x /* { dg-warning "redefined" } */
 #undef str
 
 #define str(x) #x
@@ -54,173 +54,173 @@
 #define str(x) %: x
 #undef str
 
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a#x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a#x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%:x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a%:x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a# x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a# x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%: x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a%: x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%: x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a%: x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%: x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a%: x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%: x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a%: x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%: x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a%: x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a%: x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a%: x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a #x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a #x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %:x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a %:x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a # x /* { dg-message "-:previous definition" } */
-#define astr(x) a %: x /* { dg-warning "-:redefined" } */
+#define astr(x) a # x /* { dg-message "previous definition" } */
+#define astr(x) a %: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a#x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a#x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a# x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a# x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a%: x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a%: x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a #x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a #x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a %:x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a %:x /* { dg-warning "redefined" } */
 #undef astr
-#define astr(x) a %: x /* { dg-message "-:previous definition" } */
-#define astr(x) a # x /* { dg-warning "-:redefined" } */
+#define astr(x) a %: x /* { dg-message "previous definition" } */
+#define astr(x) a # x /* { dg-warning "redefined" } */
 #undef astr
 
 #define astr(x) a#x
@@ -248,173 +248,173 @@
 #define astr(x) a %: x
 #undef astr
 
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x##y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x## y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x%:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x%:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ##y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ##y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%:y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%:y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x ## y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x ## y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x## y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x%:%: y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x%:%: y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ##y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x ##y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x %:%:y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x %:%:y /* { dg-warning "redefined" } */
 #undef cat
-#define cat(x,y) x %:%: y /* { dg-message "-:previous definition" } */
-#define cat(x,y) x ## y /* { dg-warning "-:redefined" } */
+#define cat(x,y) x %:%: y /* { dg-message "previous definition" } */
+#define cat(x,y) x ## y /* { dg-warning "redefined" } */
 #undef cat
 
 #define cat(x,y) x##y
@@ -442,28 +442,28 @@
 #define cat(x,y) x %:%: y
 #undef cat
 
-#define cat3(x,y,z) x##y##z /* { dg-message "-:previous definition" } */
-#define cat3(x,y,z) x##y####z /* { dg-warning "-:redefined" } */
+#define cat3(x,y,z) x##y##z /* { dg-message "previous definition" } */
+#define cat3(x,y,z) x##y####z /* { dg-warning "redefined" } */
 #undef cat3
 
-#define cat3(x,y,z) x##y####z /* { dg-message "-:previous definition" } */
-#define cat3(x,y,z) x####y##z /* { dg-warning "-:redefined" } */
+#define cat3(x,y,z) x##y####z /* { dg-message "previous definition" } */
+#define cat3(x,y,z) x####y##z /* { dg-warning "redefined" } */
 #undef cat3
 
-#define cat3(x,y,z) x##y####z /* { dg-message "-:previous definition" } */
-#define cat3(x,y,z) x##y## ##z /* { dg-warning "-:redefined" } */
+#define cat3(x,y,z) x##y####z /* { dg-message "previous definition" } */
+#define cat3(x,y,z) x##y## ##z /* { dg-warning "redefined" } */
 #undef cat3
 
-#define cat3(x,y,z) x##y####z /* { dg-message "-:previous definition" } */
-#define cat3(x,y,z) x##y##%:%:z /* { dg-warning "-:redefined" } */
+#define cat3(x,y,z) x##y####z /* { dg-message "previous definition" } */
+#define cat3(x,y,z) x##y##%:%:z /* { dg-warning "redefined" } */
 #undef cat3
 
-#define cat3(x,y,z) x##y######## ####z /* { dg-message "-:previous definition" } */
-#define cat3(x,y,z) x##y############z /* { dg-warning "-:redefined" } */
+#define cat3(x,y,z) x##y######## ####z /* { dg-message "previous definition" } */
+#define cat3(x,y,z) x##y############z /* { dg-warning "redefined" } */
 #undef cat3
 
-#define cat3(x,y,z) x##y############z /* { dg-message "-:previous definition" } */
-#define cat3(x,y,z) x##y########%:%:##z /* { dg-warning "-:redefined" } */
+#define cat3(x,y,z) x##y############z /* { dg-message "previous definition" } */
+#define cat3(x,y,z) x##y########%:%:##z /* { dg-warning "redefined" } */
 #undef cat3
 
 #define cat3(x,y,z) x##y##z
diff --git a/gcc/testsuite/gcc.dg/cpp/ucnid-11-utf8.c b/gcc/testsuite/gcc.dg/cpp/ucnid-11-utf8.c
index 56b88f8b..701765d 100644
--- a/gcc/testsuite/gcc.dg/cpp/ucnid-11-utf8.c
+++ b/gcc/testsuite/gcc.dg/cpp/ucnid-11-utf8.c
@@ -4,23 +4,23 @@
 /* { dg-options "-std=c99 -pedantic-errors" } */
 
 /* Different spelling of UCN in expansion.  */
-#define m1 \u00c1 /* { dg-message "-:previous definition" } */
-#define m1 Á /* { dg-error "-:redefined" } */
+#define m1 \u00c1 /* { dg-message "previous definition" } */
+#define m1 Á /* { dg-error "redefined" } */
 
 #define m1ok Á
 #define m1ok Á
 
 /* Different spelling of UCN in argument name.  */
-#define m2(\u00c1) /* { dg-message "-:previous definition" } */
-#define m2(Á) /* { dg-error "-:redefined" } */
+#define m2(\u00c1) /* { dg-message "previous definition" } */
+#define m2(Á) /* { dg-error "redefined" } */
 
 #define m2ok(Á)
 #define m2ok(Á)
 
 /* Same spelling in argument name but different spelling when used in
    expansion.  */
-#define m3(\u00c1) \u00c1 /* { dg-message "-:previous definition" } */
-#define m3(\u00c1) Á /* { dg-error "-:redefined" } */
+#define m3(\u00c1) \u00c1 /* { dg-message "previous definition" } */
+#define m3(\u00c1) Á /* { dg-error "redefined" } */
 
 #define m3ok(\u00c1) Á
 #define m3ok(\u00c1) Á
diff --git a/gcc/testsuite/gcc.dg/cpp/ucnid-11.c b/gcc/testsuite/gcc.dg/cpp/ucnid-11.c
index b6956f5..a44a3ea 100644
--- a/gcc/testsuite/gcc.dg/cpp/ucnid-11.c
+++ b/gcc/testsuite/gcc.dg/cpp/ucnid-11.c
@@ -4,23 +4,23 @@
 /* { dg-options "-std=c99 -pedantic-errors" } */
 
 /* Different spelling of UCN in expansion.  */
-#define m1 \u00c1 /* { dg-message "-:previous definition" } */
-#define m1 \u00C1 /* { dg-error "-:redefined" } */
+#define m1 \u00c1 /* { dg-message "previous definition" } */
+#define m1 \u00C1 /* { dg-error "redefined" } */
 
 #define m1ok \u00c1
 #define m1ok \u00c1
 
 /* Different spelling of UCN in argument name.  */
-#define m2(\u00c1) /* { dg-message "-:previous definition" } */
-#define m2(\u00C1) /* { dg-error "-:redefined" } */
+#define m2(\u00c1) /* { dg-message "previous definition" } */
+#define m2(\u00C1) /* { dg-error "redefined" } */
 
 #define m2ok(\u00c1)
 #define m2ok(\u00c1)
 
 /* Same spelling in argument name but different spelling when used in
    expansion.  */
-#define m3(\u00c1) \u00c1 /* { dg-message "-:previous definition" } */
-#define m3(\u00c1) \u00C1 /* { dg-error "-:redefined" } */
+#define m3(\u00c1) \u00c1 /* { dg-message "previous definition" } */
+#define m3(\u00c1) \u00C1 /* { dg-error "redefined" } */
 
 #define m3ok(\u00c1) \u00C1
 #define m3ok(\u00c1) \u00C1
diff --git a/gcc/testsuite/gcc.dg/cpp/undef2.c b/gcc/testsuite/gcc.dg/cpp/undef2.c
index 189a72d..f9b047b 100644
--- a/gcc/testsuite/gcc.dg/cpp/undef2.c
+++ b/gcc/testsuite/gcc.dg/cpp/undef2.c
@@ -3,9 +3,9 @@
 
 /* { dg-do preprocess } */
 
-#undef __DATE__		/* { dg-warning "-:undefining \"__DATE__\"" } */
-#undef __TIME__		/* { dg-warning "-:undefining \"__TIME__\"" } */
-#undef __FILE__		/* { dg-warning "-:undefining \"__FILE__\"" } */
+#undef __DATE__		/* { dg-warning "undefining \"__DATE__\"" } */
+#undef __TIME__		/* { dg-warning "undefining \"__TIME__\"" } */
+#undef __FILE__		/* { dg-warning "undefining \"__FILE__\"" } */
 #undef __LINE__		/* { dg-warning "undefining \"__LINE__\"" } */
 #undef __STDC__		/* { dg-warning "undefining \"__STDC__\"" } */
 
diff --git a/gcc/testsuite/gcc.dg/cpp/warn-redefined-2.c b/gcc/testsuite/gcc.dg/cpp/warn-redefined-2.c
index ea5ad81..3e2e57a 100644
--- a/gcc/testsuite/gcc.dg/cpp/warn-redefined-2.c
+++ b/gcc/testsuite/gcc.dg/cpp/warn-redefined-2.c
@@ -6,13 +6,13 @@
 // { dg-bogus "__TIME__ builtin is not defined" "no-time" { target *-*-* } .-1 }
 #endif
 
-#define __TIME__ "X"  // { dg-error "-:\"__TIME__\" redefined .-Werror=builtin-macro-redefined." }
+#define __TIME__ "X"  // { dg-error "\"__TIME__\" redefined .-Werror=builtin-macro-redefined." }
 
 #define __TIME__ "Y"  // { dg-bogus "-Wbuiltin-macro-redefined" }
-                      // { dg-warning "-:\"__TIME__\" redefined" "not-builtin-1" { target *-*-* } .-1 }
-                      // { dg-message "-:previous definition" "previous-1" { target *-*-* } 9 }
+                      // { dg-warning "\"__TIME__\" redefined" "not-builtin-1" { target *-*-* } .-1 }
+                      // { dg-message "previous definition" "previous-1" { target *-*-* } 9 }
 
 #define X "X"
 #define X "Y"         // { dg-bogus "-Wbuiltin-macro-redefined" }
-                      // { dg-warning "-:\"X\" redefined" "not-builtin-2" { target *-*-* } .-1 }
-                      // { dg-message "-:previous definition" "previous-2" { target *-*-* } 15 }
+                      // { dg-warning "\"X\" redefined" "not-builtin-2" { target *-*-* } .-1 }
+                      // { dg-message "previous definition" "previous-2" { target *-*-* } 15 }
diff --git a/gcc/testsuite/gcc.dg/cpp/warn-redefined.c b/gcc/testsuite/gcc.dg/cpp/warn-redefined.c
index e044668..c562d07 100644
--- a/gcc/testsuite/gcc.dg/cpp/warn-redefined.c
+++ b/gcc/testsuite/gcc.dg/cpp/warn-redefined.c
@@ -6,13 +6,13 @@
 // { dg-bogus "__TIME__ builtin is not defined" "no-time" { target *-*-* } .-1 }
 #endif
 
-#define __TIME__ "X"  // { dg-warning "-:\"__TIME__\" redefined .-Wbuiltin-macro-redefined." }
+#define __TIME__ "X"  // { dg-warning "\"__TIME__\" redefined .-Wbuiltin-macro-redefined." }
 
 #define __TIME__ "Y"  // { dg-bogus "-Wbuiltin-macro-redefined" }
-                      // { dg-warning "-:\"__TIME__\" redefined" "not-builtin-1" { target *-*-* } .-1 }
-                      // { dg-message "-:previous definition" "previous-1" { target *-*-* } 9 }
+                      // { dg-warning "\"__TIME__\" redefined" "not-builtin-1" { target *-*-* } .-1 }
+                      // { dg-message "previous definition" "previous-1" { target *-*-* } 9 }
 
 #define X "X"
 #define X "Y"         // { dg-bogus "-Wbuiltin-macro-redefined" }
-                      // { dg-warning "-:\"X\" redefined" "not-builtin-2" { target *-*-* } .-1 }
-                      // { dg-message "-:previous definition" "previous-2" { target *-*-* } 15 }
+                      // { dg-warning "\"X\" redefined" "not-builtin-2" { target *-*-* } .-1 }
+                      // { dg-message "previous definition" "previous-2" { target *-*-* } 15 }
diff --git a/gcc/testsuite/gcc.dg/cpp/warn-unused-macros-2.c b/gcc/testsuite/gcc.dg/cpp/warn-unused-macros-2.c
index f82d67f..7c3efe0 100644
--- a/gcc/testsuite/gcc.dg/cpp/warn-unused-macros-2.c
+++ b/gcc/testsuite/gcc.dg/cpp/warn-unused-macros-2.c
@@ -1,4 +1,4 @@
 // { dg-do preprocess }
 // { dg-options "-std=gnu99 -fdiagnostics-show-option -Werror=unused-macros" }
 /* { dg-message "some warnings being treated as errors" "" {target "*-*-*"} 0 } */
-#define X X  // { dg-error "-:macro \"X\" is not used .-Werror=unused-macros." }
+#define X X  // { dg-error "9:macro \"X\" is not used .-Werror=unused-macros." }
diff --git a/gcc/testsuite/gcc.dg/cpp/warn-unused-macros.c b/gcc/testsuite/gcc.dg/cpp/warn-unused-macros.c
index b18f506..74df239 100644
--- a/gcc/testsuite/gcc.dg/cpp/warn-unused-macros.c
+++ b/gcc/testsuite/gcc.dg/cpp/warn-unused-macros.c
@@ -1,4 +1,4 @@
 // { dg-do preprocess }
 // { dg-options "-std=gnu99 -fdiagnostics-show-option -Wunused-macros" }
 
-#define X X  // { dg-warning "-:macro \"X\" is not used .-Wunused-macros." }
+#define X X  // { dg-warning "9:macro \"X\" is not used .-Wunused-macros." }
diff --git a/gcc/testsuite/gcc.dg/ipa/pr110276.c b/gcc/testsuite/gcc.dg/ipa/pr110276.c
new file mode 100644
index 0000000..5a1e2f3
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ipa/pr110276.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef long (*EFI_PCI_IO_PROTOCOL_CONFIG)();
+typedef struct {
+  EFI_PCI_IO_PROTOCOL_CONFIG Read;
+} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;
+typedef struct {
+  EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;
+} EFI_PCI_IO_PROTOCOL;
+int init_regs_0;
+static void __attribute__((constructor)) init(EFI_PCI_IO_PROTOCOL *pci_io) {
+  if (init_regs_0)
+    pci_io->Pci.Read();
+}
diff --git a/gcc/testsuite/gcc.dg/lto/20091013-1_0.c b/gcc/testsuite/gcc.dg/lto/20091013-1_0.c
index afceb24..7737e25 100644
--- a/gcc/testsuite/gcc.dg/lto/20091013-1_0.c
+++ b/gcc/testsuite/gcc.dg/lto/20091013-1_0.c
@@ -2,7 +2,7 @@
 /* { dg-require-effective-target fpic } */
 /* { dg-require-effective-target ptr_eq_long } */
 /* { dg-lto-options {{-fPIC -r -nostdlib -flto} {-fPIC -r -nostdlib -O2 -flto}} } */
-/* { dg-extra-ld-options "-flinker-output=nolto-rel" } */
+/* { dg-extra-ld-options "-flinker-output=nolto-rel -Wno-stringop-overread" } */
 
 void * HeapAlloc(void*,unsigned int,unsigned long);
 
diff --git a/gcc/testsuite/gcc.dg/missing-header-fixit-5.c b/gcc/testsuite/gcc.dg/missing-header-fixit-5.c
index 916033c..bf44feb 100644
--- a/gcc/testsuite/gcc.dg/missing-header-fixit-5.c
+++ b/gcc/testsuite/gcc.dg/missing-header-fixit-5.c
@@ -12,14 +12,18 @@ foo (char *m, int i)
   /* { dg-begin-multiline-output "" }
    11 |   if (isdigit (m[0]))
       |       ^~~~~~~
+     { dg-end-multiline-output "" } */
+  /* { dg-begin-multiline-output "" }
   +++ |+#include <ctype.h>
     1 | 
      { dg-end-multiline-output "" } */
     {
       return abs (i); /* { dg-warning "implicit declaration of function" } */
   /* { dg-begin-multiline-output "" }
-   19 |       return abs (i);
+   21 |       return abs (i);
       |              ^~~
+     { dg-end-multiline-output "" } */
+  /* { dg-begin-multiline-output "" }
   +++ |+#include <stdlib.h>
     1 | 
      { dg-end-multiline-output "" } */
@@ -27,8 +31,10 @@ foo (char *m, int i)
   else
     putchar (m[0]); /* { dg-warning "implicit declaration of function" } */
   /* { dg-begin-multiline-output "" }
-   28 |     putchar (m[0]);
+   32 |     putchar (m[0]);
       |     ^~~~~~~
+     { dg-end-multiline-output "" } */
+  /* { dg-begin-multiline-output "" }
   +++ |+#include <stdio.h>
     1 | 
      { dg-end-multiline-output "" } */
diff --git a/gcc/testsuite/gcc.dg/torture/pr110298.c b/gcc/testsuite/gcc.dg/torture/pr110298.c
new file mode 100644
index 0000000..139f5c7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr110298.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+
+int a, b, c, d, e;
+int f() {
+  c = 0;
+  for (; c >= 0; c--) {
+    d = 0;
+    for (; d <= 0; d++) {
+      e = 0;
+      for (; d + c + e >= 0; e--)
+        ;
+      a = 1;
+      b = 0;
+      for (; a; ++b)
+        a *= 2;
+      for (; b + d >= 0;)
+        return 0;
+    }
+  }
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phiprop-1.c b/gcc/testsuite/gcc.dg/tree-ssa/phiprop-1.c
new file mode 100644
index 0000000..b448e83
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/phiprop-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -fdump-tree-phiprop1-details -fdump-tree-release_ssa" } */
+int max(int a, int b)
+{
+        int *ptr;
+        if (a > b)
+          ptr = &a;
+        else
+          ptr = &b;
+        return *ptr;
+}
+
+/* { dg-final { scan-tree-dump-times "Inserting PHI for result of load" 1 "phiprop1"} } */
+/* { dg-final { scan-tree-dump-times "MAX_EXPR" 1 "release_ssa"} } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr21463.c b/gcc/testsuite/gcc.dg/tree-ssa/pr21463.c
index ed0829a..c6f1226 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr21463.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr21463.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -fdump-tree-phiprop-details" } */
+/* { dg-options "-O -fdump-tree-phiprop1-details" } */
 
 struct f
 {
@@ -16,4 +16,4 @@ int g(int i, int c, struct f *ff, int g)
   return *t;
 }
 
-/* { dg-final { scan-tree-dump-times "Inserting PHI for result of load" 1 "phiprop" } } */
+/* { dg-final { scan-tree-dump-times "Inserting PHI for result of load" 1 "phiprop1" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c b/gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c
index d8fe51c..1c54679 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/predcom-2.c
@@ -1,5 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -funroll-loops --param max-unroll-times=8 -fpredictive-commoning -fdump-tree-pcom-details -fno-tree-pre" } */
+/* { dg-additional-options "-fno-tree-vectorize" { target amdgcn-*-* } } */
 
 void abort (void);
 
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-47.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-47.c
new file mode 100644
index 0000000..659f1d0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-47.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-dse1-details" } */
+
+int a;
+int b[3];
+void test()
+{
+  if (a > 0)
+    {
+      b[0] = 0;
+      b[1] = 1;
+      b[2] = 2;
+      __builtin_unreachable ();
+    }
+}
+
+/* { dg-final { scan-tree-dump-times "Deleted dead store" 3 "dse1" } } */
diff --git a/gcc/testsuite/gcc.dg/unroll-8.c b/gcc/testsuite/gcc.dg/unroll-8.c
index dfcfe2e..c4f6ac9 100644
--- a/gcc/testsuite/gcc.dg/unroll-8.c
+++ b/gcc/testsuite/gcc.dg/unroll-8.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -fdump-rtl-loop2_unroll -funroll-loops" } */
+/* { dg-additional-options "-fno-tree-vectorize" { target amdgcn-*-* } } */
+
 struct a {int a[7];};
 int t(struct a *a, int n)
 {
diff --git a/gcc/testsuite/gcc.dg/vect/slp-26.c b/gcc/testsuite/gcc.dg/vect/slp-26.c
index 01f4e4e..f8b49ff 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-26.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-26.c
@@ -46,7 +46,7 @@ int main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! mips_msa } } } } */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { mips_msa } } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! mips_msa } } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { mips_msa } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target { ! { mips_msa || amdgcn-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { mips_msa || amdgcn-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { ! { mips_msa || amdgcn-*-* } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { mips_msa || amdgcn-*-* } } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-10.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-10.c
index e9ec960..e681043 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-10.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-10.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-11.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-11.c
index 06c103d..f83078b 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-11.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-11.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-2.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-2.c
index 059bfb3..e33a824 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-2.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-2.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-3.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-3.c
index 059bfb3..e33a824 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-3.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-3.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-4.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-4.c
index 91b82fb..8895d5c 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-4.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-4.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-5.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-5.c
index 59f339f..77d4deb 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-5.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-5.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-6.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-6.c
index 84df837..7930346 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-6.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-6.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-8.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-8.c
index b3e0b5b..1af7104 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-8.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-8.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-9.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-9.c
index 5fcde11..f0a7560 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-9.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-9.c
@@ -1,6 +1,6 @@
 /* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */
 /* { dg-do run } */
-/* { dg-additional-options "-O3 -save-temps -fdump-tree-dce -w" } */
+/* { dg-additional-options "-O3 -fdump-tree-dce -w" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/addp-same-low_1.c b/gcc/testsuite/gcc.target/aarch64/simd/addp-same-low_1.c
new file mode 100644
index 0000000..42d8db7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/addp-same-low_1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#include <arm_neon.h>
+
+
+/*
+** foo:
+**	addp	v0\.4s, v0\.4s, v0\.4s
+**	ret
+*/
+
+int32x2_t
+foo (int32x4_t a)
+{
+  return vpadd_s32 (vget_low_s32(a), vget_high_s32(a));
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/simd/low-high-combine_1.c b/gcc/testsuite/gcc.target/aarch64/simd/low-high-combine_1.c
new file mode 100644
index 0000000..0b502d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/low-high-combine_1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#include <arm_neon.h>
+
+/*
+** foo_le:	{ target aarch64_little_endian }
+**	ret
+*/
+
+int32x4_t
+foo_le (int32x4_t a)
+{
+  return vcombine_s32 (vget_low_s32 (a), vget_high_s32 (a));
+}
+
+/*
+** foo_be:	{ target aarch64_big_endian }
+**	ret
+*/
+
+int32x4_t
+foo_be (int32x4_t a)
+{
+  return vcombine_s32 (vget_high_s32 (a), vget_low_s32 (a));
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/gather_earlyclobber.c b/gcc/testsuite/gcc.target/aarch64/sve/gather_earlyclobber.c
new file mode 100644
index 0000000..db4a1db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/gather_earlyclobber.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+/*
+** food:
+**	ld1d	(?:z[1-9][0-9]*)\.d, p0/z, \[x0, z0\.d\]
+**	...
+**	ret
+*/
+
+svuint64_t
+food (svbool_t p, uint64_t *in, svint64_t offsets, svuint64_t a)
+{
+  return svadd_u64_x (p, a, svld1_gather_offset(p, in, offsets));
+}
+
+/*
+** foodb:
+**	ld1d	(?:z[1-9][0-9]*)\.d, p0/z, \[z0\.d\]
+**	...
+**	ret
+*/
+
+svuint64_t
+foodb (svbool_t p, svuint64_t bases, svuint64_t a)
+{
+  return svadd_u64_x (p, a, svld1_gather_u64 (p, bases));
+}
+
+/*
+** foodff:
+**	ldff1d	(?:z[1-9][0-9]*)\.d, p0/z, \[z0\.d\]
+**	...
+**	ret
+*/
+
+svuint64_t
+foodff (svbool_t p, svuint64_t bases, svuint64_t a)
+{
+  return svadd_u64_x (p, a, svldff1_gather_u64 (p, bases));
+}
+
+/*
+** foow:
+**	ld1w	(?:z[1-9][0-9]*)\.s, p0/z, \[z0\.s\]
+**	...
+**	ret
+*/
+
+svuint32_t
+foow (svbool_t p, svuint32_t bases, svuint32_t a)
+{
+  return svadd_u32_x (p, a, svld1_gather_u32 (p, bases));
+}
+
+/*
+** foowff:
+**	ldff1w	(?:z[1-9][0-9]*)\.s, p0/z, \[z0\.s\]
+**	...
+**	ret
+*/
+
+svuint32_t
+foowff (svbool_t p, svuint32_t bases, svuint32_t a)
+{
+  return svadd_u32_x (p, a, svldff1_gather_u32 (p, bases));
+}
+
+/*
+** fooubd:
+**	ld1b	(?:z[1-9][0-9]*)\.d, p0/z, \[x0, z0\.d\]
+**	...
+**	ret
+*/
+
+svuint64_t
+fooubd (svbool_t p, uint8_t *base, svuint64_t offsets, svuint64_t a)
+{
+  return svadd_u64_x (p, a, svld1ub_gather_offset_u64 (p, base, offsets));
+}
+
+/*
+** foosbd:
+**	ld1sb	(?:z[1-9][0-9]*)\.d, p0/z, \[x0, z0\.d\]
+**	...
+**	ret
+*/
+svint64_t
+foosbd (svbool_t p, int8_t *base, svint64_t offsets, svint64_t a)
+{
+  return svadd_s64_x (p, a, svld1sb_gather_offset_s64 (p, base, offsets));
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c
index 4509fff..6deca32 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c
@@ -31,11 +31,13 @@ callee_pred (__SVBool_t p0, __SVBool_t p1, __SVBool_t p2, __SVBool_t p3,
 /*
 ** caller_pred:
 **	...
+**	mov	x0, sp
 **	ptrue	(p[0-9]+)\.b, vl5
-**	str	\1, \[x0\]
+**	str	\1, \[(?:x0|sp)\]
 **	...
+**	mov	x1, sp
 **	ptrue	(p[0-9]+)\.h, vl6
-**	str	\2, \[x1\]
+**	str	\2, \[(?:x1|sp)\]
 **	ptrue	p3\.d, vl4
 **	ptrue	p2\.s, vl3
 **	ptrue	p1\.h, vl2
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c
index 29e80dc..3ad4454 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_2.c
@@ -64,7 +64,7 @@ caller_int (int8_t *x0, int16_t *x1, int32_t *x2, int64_t *x3)
 /* { dg-final { scan-assembler {\tmov\tz6\.s, #6\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz7\.d, #7\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx4, sp\n} } } */
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.b), #8\n.*\tst1b\t\1, p[0-7], \[x4\]\n} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.b), #8\n.*\tst1b\t\1, p[0-7], \[(?:x4|sp)\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c
index 611f3d0..56896c9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_3.c
@@ -64,7 +64,7 @@ caller_uint (uint8_t *x0, uint16_t *x1, uint32_t *x2, uint64_t *x3)
 /* { dg-final { scan-assembler {\tmov\tz6\.s, #6\n} } } */
 /* { dg-final { scan-assembler {\tmov\tz7\.d, #7\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx4, sp\n} } } */
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.b), #8\n.*\tst1b\t\1, p[0-7], \[x4\]\n} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.b), #8\n.*\tst1b\t\1, p[0-7], \[(?:x4|sp)\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c
index c40d63e..7213c86 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_4.c
@@ -64,7 +64,7 @@ caller_float (float16_t *x0, float16_t *x1, float32_t *x2, float64_t *x3)
 /* { dg-final { scan-assembler {\tfmov\tz6\.s, #6\.0} } } */
 /* { dg-final { scan-assembler {\tfmov\tz7\.d, #7\.0} } } */
 /* { dg-final { scan-assembler {\tmov\tx4, sp\n} } } */
-/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.h), #8\.0.*\tst1h\t\1, p[0-7], \[x4\]\n} } } */
+/* { dg-final { scan-assembler {\tfmov\t(z[0-9]+\.h), #8\.0.*\tst1h\t\1, p[0-7], \[(?:x4|sp)\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
index 4002e04..e5998ae 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
index 6faf8a3..707b7be 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
index 7abd279..19e422f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3w\t{z4\.s - z6\.s}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1w\tz7\.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+\.s) - z[0-9]+\.s}.*\tst1w\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+\.s)}.*\tst1w\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+\.s) - z[0-9]+\.s}.*\tst1w\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+\.s)}.*\tst1w\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
index eea7965..1c072c0 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3d\t{z4\.d - z6\.d}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1d\tz7\.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+\.d) - z[0-9]+\.d}.*\tst1d\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+\.d)}.*\tst1d\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+\.d) - z[0-9]+\.d}.*\tst1d\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+\.d)}.*\tst1d\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
index 59b17a4..3b486f9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
index 8988f9c..3b3d72c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3w\t{z4\.s - z6\.s}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1w\tz7\.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+\.s) - z[0-9]+\.s}.*\tst1w\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+\.s)}.*\tst1w\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+\.s) - z[0-9]+\.s}.*\tst1w\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+\.s)}.*\tst1w\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
index 4719b41..5634658 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3d\t{z4\.d - z6\.d}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1d\tz7\.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+\.d) - z[0-9]+\.d}.*\tst1d\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+\.d)}.*\tst1d\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+\.d) - z[0-9]+\.d}.*\tst1d\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+\.d)}.*\tst1d\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
index 995f3e7..12fc2db 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3b\t{z4\.b - z6\.b}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1b\tz7\.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+\.b) - z[0-9]+\.b}.*\tst1b\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+\.b)}.*\tst1b\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+\.b) - z[0-9]+\.b}.*\tst1b\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+\.b)}.*\tst1b\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
index 0b84622..b18a825 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+\.h) - z[0-9]+\.h}.*\tst1h\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+\.h)}.*\tst1h\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
index a5892f7..b69efca 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3w\t{z4\.s - z6\.s}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1w\tz7\.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+\.s) - z[0-9]+\.s}.*\tst1w\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+\.s)}.*\tst1w\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+\.s) - z[0-9]+\.s}.*\tst1w\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+\.s)}.*\tst1w\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
index 67438e8..b06d3a8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3d\t{z4\.d - z6\.d}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1d\tz7\.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+\.d) - z[0-9]+\.d}.*\tst1d\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+\.d)}.*\tst1d\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+\.d) - z[0-9]+\.d}.*\tst1d\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+\.d)}.*\tst1d\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
index 61d694c..a744278 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c
@@ -55,8 +55,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3b\t{z4\.b - z6\.b}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1b\tz7\.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+\.b) - z[0-9]+\.b}.*\tst1b\t\1, p[0-7], \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+\.b)}.*\tst1b\t\1, p[0-7], \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+\.b) - z[0-9]+\.b}.*\tst1b\t\1, p[0-7], \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+\.b)}.*\tst1b\t\1, p[0-7], \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_bf16.c
index 94d84df..4213caa 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_bf16.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f16.c
index 6271365..57095a8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f16.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f32.c
index ef89de2..ca8a974 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f32.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3w\t{z4\.s - z6\.s}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1w\tz7\.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+)\.s - z[0-9]+\.s}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+)\.s}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+)\.s - z[0-9]+\.s}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+)\.s}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f64.c
index 4eddf2d..84a66c6 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_f64.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3d\t{z4\.d - z6\.d}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1d\tz7\.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+)\.d - z[0-9]+\.d}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+)\.d}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+)\.d - z[0-9]+\.d}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+)\.d}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s16.c
index a4b6af0..1b47451 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s16.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s32.c
index 60b58d6..71436bc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s32.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3w\t{z4\.s - z6\.s}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1w\tz7\.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+)\.s - z[0-9]+\.s}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+)\.s}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+)\.s - z[0-9]+\.s}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+)\.s}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s64.c
index b6126aa..c83639f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s64.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3d\t{z4\.d - z6\.d}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1d\tz7\.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+)\.d - z[0-9]+\.d}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+)\.d}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+)\.d - z[0-9]+\.d}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+)\.d}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s8.c
index 5c16c3c..f7e8eac 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_s8.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3b\t{z4\.b - z6\.b}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1b\tz7\.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+)\.b - z[0-9]+\.b}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+)\.b}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+)\.b - z[0-9]+\.b}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+)\.b}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u16.c
index 2b9a900..b0c77d9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u16.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3h\t{z4\.h - z6\.h}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1h\tz7\.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{(z[0-9]+)\.h - z[0-9]+\.h}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+\.h - (z[0-9]+)\.h}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u32.c
index 2902f59..dd4952d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u32.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3w\t{z4\.s - z6\.s}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1w\tz7\.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+)\.s - z[0-9]+\.s}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+)\.s}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{(z[0-9]+)\.s - z[0-9]+\.s}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+\.s - (z[0-9]+)\.s}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u64.c
index 85b3cfd..d5ec0d7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u64.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3d\t{z4\.d - z6\.d}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1d\tz7\.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+)\.d - z[0-9]+\.d}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+)\.d}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{(z[0-9]+)\.d - z[0-9]+\.d}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+\.d - (z[0-9]+)\.d}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u8.c
index f56acb6..8143188 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_le_u8.c
@@ -50,8 +50,8 @@ caller (void *x0)
 /* { dg-final { scan-assembler {\tld3b\t{z4\.b - z6\.b}, p[0-7]/z, \[x0, #-3, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tld1b\tz7\.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tmov\tx1, sp\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+)\.b - z[0-9]+\.b}.*\tstr\t\1, \[x1\]\n} } } */
-/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+)\.b}.*\tstr\t\1, \[x1, #1, mul vl\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{(z[0-9]+)\.b - z[0-9]+\.b}.*\tstr\t\1, \[(?:x1|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+\.b - (z[0-9]+)\.b}.*\tstr\t\1, \[(?:x1|sp), #1, mul vl\]\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp0\.b, vl1\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp1\.h, vl2\n} } } */
 /* { dg-final { scan-assembler {\tptrue\tp2\.s, vl3\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_bf16.c
index 84d2c40..5f741ae 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_bf16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f16.c
index dd4ccc3..6904268 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f32.c
index 26ea2a3..313caa9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f64.c
index 62aded5..69a49d4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_f64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s16.c
index 204ef9a..c747d60 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s32.c
index 9ae4567..f3bdf94 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s64.c
index 0b8a2e2..013691c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s8.c
index 0afbe71..d4d593c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_s8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u16.c
index f010f5e..04f16d5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u32.c
index 60d903a..73b0306 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u64.c
index 948f426..9edbfeb 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u8.c
index 8049ec0..d2bef6a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_be_u8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mbig-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_bf16.c
index 3dc9e42..ac6045d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_bf16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f16.c
index 80a2e3a..450021d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f32.c
index 40ff421..0ece06b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f64.c
index ee219cc..b93e3bf 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_f64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s16.c
index ade75cb..8563710 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s32.c
index a6c06e2..b165b76 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s64.c
index 219c71d..00dd966 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s8.c
index c48d391..51d0fb16 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_s8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u16.c
index 6c635fd..fd1f55f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u32.c
index c31d454..dcbfab8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u64.c
index 969b258..be9b2ff 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u8.c
index d1860478..c41e4f9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_6_le_u8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -g" } */
+/* { dg-options "-O -mlittle-endian -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #pragma GCC aarch64 "arm_sve.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_8.c
index 93ace26..c03b165 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_8.c
@@ -25,4 +25,5 @@ caller (int8_t *x0, svbool_t p0, svint32x4_t z0, svint32x4_t z4)
   callee (x0, 1, 2, 3, z0, z4, svdup_s8 (42), 5, p0, 6, 7);
 }
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.b), #42\n.*\tst1b\t\1, p[0-7], \[x4\]\n} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.b), #42\n.*\tst1b\t\1, p[0-7], \[(?:x4|sp)\]\n} } } */
+/* { dg-final { scan-assembler {\tmov\tx4, sp.*\tst1b\tz[0-9]+\.b, p[0-7], \[(?:x4|sp)\]\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c
index 721e106..dcd278b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c
index 9b91620..50e77f9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c
index b979f43..e7b092a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c
index 6f2235f..c3389a8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_f64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c
index 523d3be..3c644e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c
index afde5a7..652d609 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c
index d119d0a..72ea6a3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c
index ce6d663..02f4bec 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_s8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c
index 50ae7ba..b60d448 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c
index d726c72..5f01464 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u32.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c
index ef1265c..986739f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u64.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c
index e6a82fe..533cba67 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_2_u8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fno-stack-clash-protection -g" } */
+/* { dg-options "-O2 -fno-stack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 /* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */
 
 #include <arm_sve.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_nosc.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_nosc.c
index cea69cc..986cba4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_nosc.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_nosc.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target aarch64_sve_hw } } */
-/* { dg-options "-O0 -g" } */
+/* { dg-options "-O0 -fno-cprop-registers -fdisable-rtl-combine -g" } */
 
 #include <arm_sve.h>
 #include <stdarg.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_sc.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_sc.c
index b939aa5..b8c80fb 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_sc.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/varargs_3_sc.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target aarch64_sve_hw } } */
-/* { dg-options "-O0 -fstack-clash-protection -g" } */
+/* { dg-options "-O0 -fstack-clash-protection -fno-cprop-registers -fdisable-rtl-combine -g" } */
 
 #include <arm_sve.h>
 #include <stdarg.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/gather_earlyclobber.c b/gcc/testsuite/gcc.target/aarch64/sve2/gather_earlyclobber.c
new file mode 100644
index 0000000..a6003cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/gather_earlyclobber.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include <arm_sve.h>
+
+/*
+** foownt:
+**	ldnt1w	(?:z[1-9][0-9]*)\.s, p0/z, \[z0\.s\]
+**	...
+**	ret
+*/
+
+svuint32_t
+foownt (svbool_t p, svuint32_t bases, svuint32_t a)
+{
+  return svadd_u32_x (p, a, svldnt1_gather_u32 (p, bases));
+}
+
+/*
+** foodbnt:
+**	ldnt1d	(?:z[1-9][0-9]*)\.d, p0/z, \[z0\.d\]
+**	...
+**	ret
+*/
+
+svuint64_t
+foodbnt (svbool_t p, svuint64_t bases, svuint64_t a)
+{
+  return svadd_u64_x (p, a, svldnt1_gather_u64 (p, bases));
+}
+
diff --git a/gcc/testsuite/gcc.target/avr/pr105523.c b/gcc/testsuite/gcc.target/avr/pr105523.c
new file mode 100644
index 0000000..fbbf7bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr105523.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -Wall" } */
+
+/* Verify no "array subscript 0 is outside array bounds of" is generated
+   for accessing memory addresses in the 0-4096 range. */
+
+typedef __UINT8_TYPE__ uint8_t;
+
+#define SREG (*(volatile uint8_t*) (0x3F + __AVR_SFR_OFFSET__ ))
+
+void bar (void)
+{
+    SREG = 0;
+}
diff --git a/gcc/testsuite/gcc.target/avr/pr110086.c b/gcc/testsuite/gcc.target/avr/pr110086.c
new file mode 100644
index 0000000..6b97620
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr110086.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+void __attribute__((optimize("O0"))) foo() {
+}
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c
new file mode 100644
index 0000000..20fa12f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c
@@ -0,0 +1,13 @@
+#define STYPE v16si
+#define UTYPE v16usi
+#define N 16
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv16si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv16si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c
new file mode 100644
index 0000000..3baffe9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c
@@ -0,0 +1,13 @@
+#define STYPE v2si
+#define UTYPE v2usi
+#define N 2
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv2si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv2si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv2si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv2si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv2si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv2si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c
new file mode 100644
index 0000000..eab4815
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c
@@ -0,0 +1,13 @@
+#define STYPE v32si
+#define UTYPE v32usi
+#define N 32
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv32si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv32si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c
new file mode 100644
index 0000000..370ca63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c
@@ -0,0 +1,13 @@
+#define STYPE v4si
+#define UTYPE v4usi
+#define N 4
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv4si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv4si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c
new file mode 100644
index 0000000..833608e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c
@@ -0,0 +1,13 @@
+#define STYPE v8si
+#define UTYPE v8usi
+#define N 8
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv8si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv8si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c
new file mode 100644
index 0000000..f156d49
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c
@@ -0,0 +1,11 @@
+#define STYPE v16qi
+#define UTYPE v16uqi
+#define N 16
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv16qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv16qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv16qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv16qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16qi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c
new file mode 100644
index 0000000..be4b905
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c
@@ -0,0 +1,11 @@
+#define STYPE v2qi
+#define UTYPE v2uqi
+#define N 2
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv2qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv2qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv2qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv2qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv2qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv2qi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c
new file mode 100644
index 0000000..b0cadec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c
@@ -0,0 +1,11 @@
+#define STYPE v32qi
+#define UTYPE v32uqi
+#define N 32
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv32qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv32qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv32qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv32qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32qi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c
new file mode 100644
index 0000000..4dc7c78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c
@@ -0,0 +1,11 @@
+#define STYPE v4qi
+#define UTYPE v4uqi
+#define N 4
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv4qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv4qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv4qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv4qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4qi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c
new file mode 100644
index 0000000..ea3753a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c
@@ -0,0 +1,11 @@
+#define STYPE v8qi
+#define UTYPE v8uqi
+#define N 8
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv8qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv8qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv8qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv8qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8qi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c
new file mode 100644
index 0000000..159b980
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-char-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c
new file mode 100644
index 0000000..6e730d0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-char-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c
new file mode 100644
index 0000000..8e4932b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-char-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c
new file mode 100644
index 0000000..d07a431
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-char-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c
new file mode 100644
index 0000000..64f789a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-char-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c
new file mode 100644
index 0000000..4e2d4c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-char.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c
new file mode 100644
index 0000000..478d09e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c
@@ -0,0 +1,10 @@
+#define STYPE v64qi
+#define UTYPE v64uqi
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv64qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64qi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c
new file mode 100644
index 0000000..530f29e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c
@@ -0,0 +1,11 @@
+#define STYPE v16di
+#define UTYPE v16udi
+#define N 16
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv16di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv16di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv16di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv16di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16di3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c
new file mode 100644
index 0000000..1c3e833
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c
@@ -0,0 +1,11 @@
+#define STYPE v2di
+#define UTYPE v2udi
+#define N 2
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv2di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv2di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv2di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv2di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv2di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv2di3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c
new file mode 100644
index 0000000..c8556a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c
@@ -0,0 +1,11 @@
+#define STYPE v32di
+#define UTYPE v32udi
+#define N 32
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv32di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv32di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv32di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv32di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32di3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c
new file mode 100644
index 0000000..514396c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c
@@ -0,0 +1,11 @@
+#define STYPE v4di
+#define UTYPE v4udi
+#define N 4
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv4di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv4di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv4di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv4di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4di3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c
new file mode 100644
index 0000000..428e3a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c
@@ -0,0 +1,11 @@
+#define STYPE v8di
+#define UTYPE v8udi
+#define N 8
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv8di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv8di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv8di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv8di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8di3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c
new file mode 100644
index 0000000..7ce9c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-long-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c
new file mode 100644
index 0000000..20996a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-long-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c
new file mode 100644
index 0000000..1ca25ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-long-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c
new file mode 100644
index 0000000..b31769a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-long-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c
new file mode 100644
index 0000000..930256a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-long-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c
new file mode 100644
index 0000000..363e425
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-long.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c
new file mode 100644
index 0000000..321297b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c
@@ -0,0 +1,10 @@
+#define STYPE v64di
+#define UTYPE v64udi
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64di3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c
new file mode 100644
index 0000000..ae8cdbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c
new file mode 100644
index 0000000..7d80382
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c
new file mode 100644
index 0000000..127fd36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c
new file mode 100644
index 0000000..e1d5b5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c
@@ -0,0 +1,3 @@
+/* { dg-do run } */
+#include "simd-math-3-4.c"
+
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c
new file mode 100644
index 0000000..ec98b60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c
new file mode 100644
index 0000000..aca508c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c
new file mode 100644
index 0000000..80f0414
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c
@@ -0,0 +1,11 @@
+#define STYPE v16hi
+#define UTYPE v16uhi
+#define N 16
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv16hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv16hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv16hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv16hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16hi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c
new file mode 100644
index 0000000..37e5008
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c
@@ -0,0 +1,11 @@
+#define STYPE v2hi
+#define UTYPE v2uhi
+#define N 2
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv2hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv2hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv2hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv2hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv2hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv2hi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c
new file mode 100644
index 0000000..79aada0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c
@@ -0,0 +1,11 @@
+#define STYPE v32hi
+#define UTYPE v32uhi
+#define N 32
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv32hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv32hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv32hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv32hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32hi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c
new file mode 100644
index 0000000..014acac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c
@@ -0,0 +1,11 @@
+#define STYPE v4hi
+#define UTYPE v4uhi
+#define N 4
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv4hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv4hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv4hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv4hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4hi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c
new file mode 100644
index 0000000..308b72b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c
@@ -0,0 +1,11 @@
+#define STYPE v8hi
+#define UTYPE v8uhi
+#define N 8
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv8hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv8hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv8hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv8hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8hi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c
new file mode 100644
index 0000000..8ca866c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-short-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c
new file mode 100644
index 0000000..6c6d8b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-short-2.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c
new file mode 100644
index 0000000..8c30ebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-short-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c
new file mode 100644
index 0000000..e70697e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-short-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c
new file mode 100644
index 0000000..9cb9a6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-short-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c
new file mode 100644
index 0000000..08f7267
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-3-short.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c
new file mode 100644
index 0000000..1ade288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c
@@ -0,0 +1,10 @@
+#define STYPE v64hi
+#define UTYPE v64uhi
+#include "simd-math-3.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64hi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3.c b/gcc/testsuite/gcc.target/gcn/simd-math-3.c
new file mode 100644
index 0000000..def8385
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-3.c
@@ -0,0 +1,186 @@
+/* Test that signed and unsigned division and modulus use the correct
+   vector routines and give the correct results.  */
+
+/* Setting it this way ensures the run tests use the same flag as the
+   compile tests.  */
+#pragma GCC optimize("O2")
+
+typedef signed char v2qi __attribute__ ((vector_size (2)));
+typedef signed char v4qi __attribute__ ((vector_size (4)));
+typedef signed char v8qi __attribute__ ((vector_size (8)));
+typedef signed char v16qi __attribute__ ((vector_size (16)));
+typedef signed char v32qi __attribute__ ((vector_size (32)));
+typedef signed char v64qi __attribute__ ((vector_size (64)));
+
+typedef unsigned char v2uqi __attribute__ ((vector_size (2)));
+typedef unsigned char v4uqi __attribute__ ((vector_size (4)));
+typedef unsigned char v8uqi __attribute__ ((vector_size (8)));
+typedef unsigned char v16uqi __attribute__ ((vector_size (16)));
+typedef unsigned char v32uqi __attribute__ ((vector_size (32)));
+typedef unsigned char v64uqi __attribute__ ((vector_size (64)));
+
+typedef short v2hi __attribute__ ((vector_size (4)));
+typedef short v4hi __attribute__ ((vector_size (8)));
+typedef short v8hi __attribute__ ((vector_size (16)));
+typedef short v16hi __attribute__ ((vector_size (32)));
+typedef short v32hi __attribute__ ((vector_size (64)));
+typedef short v64hi __attribute__ ((vector_size (128)));
+
+typedef unsigned short v2uhi __attribute__ ((vector_size (4)));
+typedef unsigned short v4uhi __attribute__ ((vector_size (8)));
+typedef unsigned short v8uhi __attribute__ ((vector_size (16)));
+typedef unsigned short v16uhi __attribute__ ((vector_size (32)));
+typedef unsigned short v32uhi __attribute__ ((vector_size (64)));
+typedef unsigned short v64uhi __attribute__ ((vector_size (128)));
+
+typedef int v2si __attribute__ ((vector_size (8)));
+typedef int v4si __attribute__ ((vector_size (16)));
+typedef int v8si __attribute__ ((vector_size (32)));
+typedef int v16si __attribute__ ((vector_size (64)));
+typedef int v32si __attribute__ ((vector_size (128)));
+typedef int v64si __attribute__ ((vector_size (256)));
+
+typedef unsigned int v2usi __attribute__ ((vector_size (8)));
+typedef unsigned int v4usi __attribute__ ((vector_size (16)));
+typedef unsigned int v8usi __attribute__ ((vector_size (32)));
+typedef unsigned int v16usi __attribute__ ((vector_size (64)));
+typedef unsigned int v32usi __attribute__ ((vector_size (128)));
+typedef unsigned int v64usi __attribute__ ((vector_size (256)));
+
+typedef long v2di __attribute__ ((vector_size (16)));
+typedef long v4di __attribute__ ((vector_size (32)));
+typedef long v8di __attribute__ ((vector_size (64)));
+typedef long v16di __attribute__ ((vector_size (128)));
+typedef long v32di __attribute__ ((vector_size (256)));
+typedef long v64di __attribute__ ((vector_size (512)));
+
+typedef unsigned long v2udi __attribute__ ((vector_size (16)));
+typedef unsigned long v4udi __attribute__ ((vector_size (32)));
+typedef unsigned long v8udi __attribute__ ((vector_size (64)));
+typedef unsigned long v16udi __attribute__ ((vector_size (128)));
+typedef unsigned long v32udi __attribute__ ((vector_size (256)));
+typedef unsigned long v64udi __attribute__ ((vector_size (512)));
+
+#ifndef STYPE
+#define STYPE v64si
+#define UTYPE v64usi
+#endif
+#ifndef N
+#define N 64
+#endif
+
+STYPE a;
+STYPE b;
+UTYPE ua;
+UTYPE ub;
+
+int main()
+{
+  int i;
+  STYPE squot, srem;
+  UTYPE usquot, usrem;
+  STYPE vquot, vrem;
+  UTYPE uvquot, uvrem;
+  STYPE vquot2, vrem2;
+  UTYPE uvquot2, uvrem2;
+  STYPE refquot, refrem;
+  UTYPE urefquot, urefrem;
+
+  for (i = 0; i < N; i++)
+    {
+      a[i] = i * (i >> 2) + (i >> 1);
+      ua[i] = a[i];
+      b[i] = i;
+      ub[i] = i;
+    }
+
+  for (i = 0; i < N; i++)
+    {
+      /* Calculate reference values using regular scalar div and mod.  */
+      refquot[i] = a[i] / b[i];
+      __asm__ ("" ::: "memory");
+      refrem[i] = a[i] % b[i];
+      urefquot[i] = ua[i] / ub[i];
+      __asm__ ("" ::: "memory");
+      urefrem[i] = ua[i] % ub[i];
+    }
+
+  __asm__ ("" ::: "memory");
+  /* Scalar with divmod.  */
+  for (i = 0; i < N; i++)
+    {
+      squot[i] = a[i] / b[i];
+      srem[i] = a[i] % b[i];
+      usquot[i] = ua[i] / ub[i];
+      usrem[i] = ua[i] % ub[i];
+    }
+
+  __asm__ ("" ::: "memory");
+  /* Vectorized with divmod.  */
+  vquot = a / b;
+  vrem = a % b;
+  uvquot = ua / ub;
+  uvrem = ua % ub;
+
+  __asm__ ("" ::: "memory");
+  /* Vectorized with separte div and mod.  */
+  vquot2 = a / b;
+  __asm__ ("" ::: "memory");
+  vrem2 = a % b;
+  uvquot2 = ua / ub;
+  __asm__ ("" ::: "memory");
+  uvrem2 = ua % ub;
+
+#ifdef DEBUG
+#define DUMP(VAR) \
+  __builtin_printf ("%8s: ", #VAR); \
+  for (i = 0; i < N; i++) \
+    __builtin_printf ("%d ", (int)VAR[i]); \
+  __builtin_printf ("\n");
+  DUMP (refquot)
+  DUMP (squot)
+  DUMP (vquot)
+  DUMP (vquot2)
+  __builtin_printf ("\n");
+  DUMP (urefquot)
+  DUMP (usquot)
+  DUMP (uvquot)
+  DUMP (uvquot2)
+  __builtin_printf ("\n");
+  DUMP (refrem)
+  DUMP (srem)
+  DUMP (vrem)
+  DUMP (vrem2)
+  __builtin_printf ("\n");
+  DUMP (urefrem)
+  DUMP (usrem)
+  DUMP (uvrem)
+  DUMP (uvrem2)
+  __builtin_printf ("\n");
+#endif
+
+  for (i = 0; i < N; i++)
+    if (squot[i] != refquot[i]
+	|| vquot[i] != refquot[i]
+	|| vquot2[i] != refquot[i]
+	|| usquot[i] != urefquot[i]
+	|| uvquot[i] != urefquot[i]
+	|| uvquot2[i] != urefquot[i]
+	|| srem[i] != refrem[i]
+	|| vrem[i] != refrem[i]
+	|| vrem2[i] != refrem[i]
+	|| usrem[i] != urefrem[i]
+	|| uvrem[i] != urefrem[i]
+	|| uvrem2[i] != urefrem[i])
+      __builtin_abort ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {__divmodv64si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__modv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 1 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c
new file mode 100644
index 0000000..b328a3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-4-char.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c
new file mode 100644
index 0000000..df24bd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c
@@ -0,0 +1,9 @@
+#define TYPE v64qi
+#include "simd-math-4.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64qi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64qi4@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divv64qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64qi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c
new file mode 100644
index 0000000..34cbc46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-4-long.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c
new file mode 100644
index 0000000..768a0df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c
@@ -0,0 +1,9 @@
+#define TYPE v64di
+#include "simd-math-4.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64di4@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64di3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64di3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c
new file mode 100644
index 0000000..3b98c0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c
new file mode 100644
index 0000000..4cbeb97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-4-short.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c
new file mode 100644
index 0000000..f010942
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c
@@ -0,0 +1,9 @@
+#define TYPE v64hi
+#include "simd-math-4.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64hi4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64hi4@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64hi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-4.c
new file mode 100644
index 0000000..833dfe2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-4.c
@@ -0,0 +1,99 @@
+/* Test that signed division and modulus give the correct result with
+   different variations of signedness.  */
+
+/* Setting it this way ensures the run tests use the same flag as the
+   compile tests.  */
+#pragma GCC optimize("O2")
+
+typedef char v64qi __attribute__ ((vector_size (64)));
+typedef short v64hi __attribute__ ((vector_size (128)));
+typedef int v64si __attribute__ ((vector_size (256)));
+typedef long v64di __attribute__ ((vector_size (512)));
+
+#ifndef TYPE
+#define TYPE v64si
+#endif
+#define N 64
+
+TYPE a;
+TYPE b;
+
+int main()
+{
+  int i;
+  TYPE squot, srem;
+  TYPE usquot, usrem;
+  TYPE vquot, vrem;
+  TYPE vquot2, vrem2;
+  TYPE refquot, refrem;
+
+  for (i = 0; i < 64; i++)
+    {
+      a[i] = i * (i >> 2) * (i&1 ? -1 : 1);
+      b[i] = i * (i&2 ? -1 : 1);
+    }
+
+  for (i = 0; i < N; i++)
+    {
+      /* Calculate reference values using regular scalar div and mod.  */
+      refquot[i] = a[i] / b[i];
+      __asm__ ("" ::: "memory");
+      refrem[i] = a[i] % b[i];
+    }
+
+  __asm__ ("" ::: "memory");
+  /* Scalar with divmod.  */
+  for (i = 0; i < N; i++)
+    {
+      squot[i] = a[i] / b[i];
+      srem[i] = a[i] % b[i];
+    }
+
+  __asm__ ("" ::: "memory");
+  /* Vectorized with divmod.  */
+  vquot = a / b;
+  vrem = a % b;
+
+  __asm__ ("" ::: "memory");
+  /* Vectorized with separte div and mod.  */
+  vquot2 = a / b;
+  __asm__ ("" ::: "memory");
+  vrem2 = a % b;
+
+#ifdef DEBUG
+#define DUMP(VAR) \
+  __builtin_printf ("%8s: ", #VAR); \
+  for (i = 0; i < N; i++) \
+    __builtin_printf ("%d ", (int)VAR[i]); \
+  __builtin_printf ("\n");
+  DUMP (refquot)
+  DUMP (squot)
+  DUMP (vquot)
+  DUMP (vquot2)
+  __builtin_printf ("\n");
+  DUMP (refrem)
+  DUMP (srem)
+  DUMP (vrem)
+  DUMP (vrem2)
+  __builtin_printf ("\n");
+#endif
+
+  for (i = 0; i < N; i++)
+    if (squot[i] != refquot[i]
+	|| vquot[i] != refquot[i]
+	|| vquot2[i] != refquot[i]
+	|| srem[i] != refrem[i]
+	|| vrem[i] != refrem[i]
+	|| vrem2[i] != refrem[i])
+      __builtin_abort ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {__divmodv64si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64si4@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c
new file mode 100644
index 0000000..41c1167
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c
@@ -0,0 +1,8 @@
+#define N 16
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv16si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv16si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16si3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c
new file mode 100644
index 0000000..3fb92b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c
@@ -0,0 +1,8 @@
+#define N 32
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv32si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv32si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32si3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c
new file mode 100644
index 0000000..ffcd512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c
@@ -0,0 +1,8 @@
+#define N 4
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv4si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv4si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4si3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c
new file mode 100644
index 0000000..5d855b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c
@@ -0,0 +1,8 @@
+#define N 8
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv8si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv8si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8si3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c
new file mode 100644
index 0000000..0ebf640
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c
@@ -0,0 +1,11 @@
+#define TYPE char
+#define N 16
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses HImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod16.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv16qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv16qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv16qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16qi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c
new file mode 100644
index 0000000..0905f31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c
@@ -0,0 +1,11 @@
+#define TYPE char
+#define N 32
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses HImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod32.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv32qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv32qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv32qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32qi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c
new file mode 100644
index 0000000..772fe37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c
@@ -0,0 +1,11 @@
+#define TYPE char
+#define N 4
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses HImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod4.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv4qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv4qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv4qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4qi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c
new file mode 100644
index 0000000..539ce9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c
@@ -0,0 +1,11 @@
+#define TYPE char
+#define N 8
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses HImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod8.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv8qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv8qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv8qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8qi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c
new file mode 100644
index 0000000..0f1af08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-char-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c
new file mode 100644
index 0000000..a2794c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-char-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c
new file mode 100644
index 0000000..a8e4187
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-char-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c
new file mode 100644
index 0000000..7a6a959
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-char-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c
new file mode 100644
index 0000000..d3ca775
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-char.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
new file mode 100644
index 0000000..2321c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c
@@ -0,0 +1,10 @@
+#define TYPE char
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses HImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmodv64si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv64qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv64qi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64qi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64qi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c
new file mode 100644
index 0000000..659907d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c
@@ -0,0 +1,9 @@
+#define TYPE long
+#define N 16
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv16di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv16di3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv16di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16di3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c
new file mode 100644
index 0000000..b03fd09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c
@@ -0,0 +1,9 @@
+#define TYPE long
+#define N 32
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv32di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv32di3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv32di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32di3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c
new file mode 100644
index 0000000..a8877b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c
@@ -0,0 +1,9 @@
+#define TYPE long
+#define N 4
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv4di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv4di3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv4di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4di3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c
new file mode 100644
index 0000000..5b1106c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c
@@ -0,0 +1,9 @@
+#define TYPE long
+#define N 8
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv8di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv8di3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv8di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8di3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c
new file mode 100644
index 0000000..2091925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c
new file mode 100644
index 0000000..c7ff7ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c
new file mode 100644
index 0000000..c6cf334
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c
new file mode 100644
index 0000000..85fdf6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c
new file mode 100644
index 0000000..b948fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
new file mode 100644
index 0000000..37b6cef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c
@@ -0,0 +1,8 @@
+#define TYPE long
+#include "simd-math-5.c"
+
+/* { dg-final { scan-assembler-times {__divmodv64di4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64di3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64di3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64di3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c
new file mode 100644
index 0000000..2091925
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c
new file mode 100644
index 0000000..c7ff7ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c
new file mode 100644
index 0000000..c6cf334
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c
new file mode 100644
index 0000000..85fdf6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-long-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c
new file mode 100644
index 0000000..de6504c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c
new file mode 100644
index 0000000..5d5953b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c
@@ -0,0 +1,11 @@
+#define TYPE short
+#define N 16
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses SImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod16.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv16si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv16hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv16hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv16hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv16hi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c
new file mode 100644
index 0000000..bf8a3ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c
@@ -0,0 +1,11 @@
+#define TYPE short
+#define N 32
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses SImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod32.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv32si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv32hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv32hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv32hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv32hi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c
new file mode 100644
index 0000000..a2cb46c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c
@@ -0,0 +1,11 @@
+#define TYPE short
+#define N 4
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses SImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod4.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv4si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv4hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv4hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv4hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv4hi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c
new file mode 100644
index 0000000..fa343e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c
@@ -0,0 +1,11 @@
+#define TYPE short
+#define N 8
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses SImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmod8.i4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv8si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv8hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv8hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv8hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv8hi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c
new file mode 100644
index 0000000..3fc946e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-short-16.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c
new file mode 100644
index 0000000..34b1d75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-short-32.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c
new file mode 100644
index 0000000..09385c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-short-4.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c
new file mode 100644
index 0000000..1de4d26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-short-8.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c
new file mode 100644
index 0000000..2e0c490
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "simd-math-5-short.c"
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
new file mode 100644
index 0000000..84cdc9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c
@@ -0,0 +1,10 @@
+#define TYPE short
+#include "simd-math-5.c"
+
+/* C integer promotion means that div uses SImode and divmod doesn't match.  */
+/* { dg-final { scan-assembler-times {__divmodv64si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__divv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__divv64hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__udivv64hi3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64hi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64hi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5.c b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
new file mode 100644
index 0000000..bc181b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/gcn/simd-math-5.c
@@ -0,0 +1,88 @@
+/* Test that the auto-vectorizer uses the libgcc vectorized division and
+   modulus functions.  */
+
+/* Setting it this way ensures the run tests use the same flag as the
+   compile tests.  */
+#pragma GCC optimize("O2")
+
+#ifndef TYPE
+#define TYPE int
+#endif
+#ifndef N
+#define N 64
+#endif
+
+TYPE a[N];
+TYPE b[N];
+
+int main()
+{
+  int i;
+  TYPE quot[N], rem[N];
+  TYPE quot2[N], rem2[N];
+  TYPE refquot[N], refrem[N];
+
+  for (i = 0; i < N; i++)
+    {
+      a[i] = i * (i >> 2) + (i >> 1);
+      b[i] = i;
+    }
+  __asm__ ("" ::: "memory");
+
+  /* Vector divmod.  */
+  for (i = 0; i < N; i++)
+    {
+      quot[i] = (TYPE)a[i] / (TYPE)b[i];
+      rem[i] = (TYPE)a[i] % (TYPE)b[i];
+    }
+  __asm__ ("" ::: "memory");
+
+  /* Vector div.  */
+  for (i = 0; i < N; i++)
+    quot2[i] = (TYPE)a[i] / (TYPE)b[i];
+  __asm__ ("" ::: "memory");
+
+  /* Vector mod.  */
+  for (i = 0; i < N; i++)
+    rem2[i] = (TYPE)a[i] % (TYPE)b[i];
+
+  /* Calculate reference values with no vectorization.  */
+  for (i = 0; i < N; i++)
+    {
+      refquot[i] = (TYPE)a[i] / (TYPE)b[i];
+      __asm__ ("" ::: "memory");
+      refrem[i] = (TYPE)a[i] % (TYPE)b[i];
+    }
+
+#ifdef DEBUG
+#define DUMP(VAR) \
+  __builtin_printf ("%8s: ", #VAR); \
+  for (i = 0; i < N; i++) \
+    __builtin_printf ("%d ", (int)VAR[i]); \
+  __builtin_printf ("\n");
+  DUMP (refquot)
+  DUMP (quot)
+  DUMP (quot2)
+  __builtin_printf ("\n");
+  DUMP (refrem)
+  DUMP (rem)
+  DUMP (rem2)
+#endif
+
+  for (i = 0; i < N; i++)
+    if (quot[i] != refquot[i]
+	|| quot2[i] != refquot[i]
+	|| rem[i] != refrem[i]
+	|| rem2[i] != refrem[i])
+      __builtin_abort ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {__divmodv64si4@rel32@lo} 1 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times {__udivmodv64si4@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivv64si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__modv64si3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__umodv64si3@rel32@lo} 0 } } */
+/* { dg-final { scan-assembler-times {__divsi3@rel32@lo} 1 } } */
+/* { dg-final { scan-assembler-times {__udivsi3@rel32@lo} 0 } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c
new file mode 100644
index 0000000..ae839e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpackssdw-3.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw" } */
+/* { dg-require-effective-target avx512bw } */
+
+#define AVX512BW
+#include "avx512f-helper.h"
+
+#define DST_SIZE (AVX512F_LEN / 16)
+#define SRC_SIZE (AVX512F_LEN / 32)
+
+#include "limits.h"
+
+#include "avx512f-mask-type.h"
+
+static short
+int_to_short (int iVal)
+{
+  short sVal;
+
+  if (iVal < -32768)
+    sVal = -32768;
+  else if (iVal > 32767)
+    sVal = 32767;
+  else
+    sVal = iVal;
+
+  return sVal;
+}
+
+void
+TEST (void)
+{
+  union512i_d s1, s2;
+  union512i_w res1;
+  short dst_ref[32];
+  int i;
+
+  s1.x = _mm512_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -65000);
+  s2.x = _mm512_set_epi32 (80, 40, 31, 21, 10, 99, 74, -65000, 2, 3, 4, 5, 65010, 21, 31, 91);
+  res1.x = _mm512_packs_epi32 (s1.x, s2.x);
+  for (int i = 0; i != 4; i++)
+    {
+      dst_ref[i] = int_to_short (s1.a[i]);
+      dst_ref[i + 4] = int_to_short (s2.a[i]);
+      dst_ref[i + 8] = int_to_short (s1.a[i + 4]);
+      dst_ref[i + 12] = int_to_short (s2.a[i + 4]);
+      dst_ref[i + 16] = int_to_short (s1.a[i + 8]);
+      dst_ref[i + 20] = int_to_short (s2.a[i + 8]);
+      dst_ref[i + 24] = int_to_short (s1.a[i + 12]);
+      dst_ref[i + 28] = int_to_short (s2.a[i + 12]);      
+    }
+
+  if (check_union512i_w (res1, dst_ref))
+    abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c
new file mode 100644
index 0000000..056c735
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpacksswb-3.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw" } */
+/* { dg-require-effective-target avx512bw } */
+
+#define AVX512BW
+#include "avx512f-helper.h"
+
+static char
+short_to_byte (short iVal)
+{
+  short sVal;
+
+  if (iVal < -128)
+    sVal = -128;
+  else if (iVal > 127)
+    sVal = 127;
+  else
+    sVal = iVal;
+
+  return sVal;
+}
+
+void
+TEST (void)
+{
+  union512i_w s1, s2;
+  union512i_b res1;
+  char dst_ref[64];
+  int i;
+
+  s1.x = _mm512_set_epi16 (1, 2, 3, 4, 650, 20, 30, 90, 88, 44, 33, 22, 11, 98, 76, -650,
+			   128, 230, -112, -128, -3, -4, -7, 9, 10, 11, 12, 13, -223, 10, 8, 11);
+  s2.x = _mm512_set_epi16 (80, 40, 31, 21, 10, 99, 74, -650, 2, 3, 4, 5, 650, 21, 31, 91,
+			   280, -140, 310, 20, 9, 98, 73, -651, 3, 4, 5, 6, 651, 22, 32, 92);
+  res1.x = _mm512_packs_epi16 (s1.x, s2.x);
+  for (int i = 0; i != 8; i++)
+    {
+      dst_ref[i] = short_to_byte (s1.a[i]);
+      dst_ref[i + 8] = short_to_byte (s2.a[i]);
+      dst_ref[i + 16] = short_to_byte (s1.a[i + 8]);
+      dst_ref[i + 24] = short_to_byte (s2.a[i + 8]);
+      dst_ref[i + 32] = short_to_byte (s1.a[i + 16]);
+      dst_ref[i + 40] = short_to_byte (s2.a[i + 16]);
+      dst_ref[i + 48] = short_to_byte (s1.a[i + 24]);
+      dst_ref[i + 56] = short_to_byte (s2.a[i + 24]);      
+    }
+
+  if (check_union512i_b (res1, dst_ref))
+    abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-copysign.c b/gcc/testsuite/gcc.target/i386/avx512f-copysign.c
new file mode 100644
index 0000000..51ca028
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-copysign.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -mno-avx512vl -mprefer-vector-width=512 -O2" } */
+/* { dg-final { scan-assembler-times "vpternlog\[dq\]\[ \\t\]+\\\$(?:216|228|0xd8|0xe4)," 5 } } */
+
+double cs_df (double x, double y)
+{
+  return __builtin_copysign (x, y);
+}
+
+float cs_sf (float x, float y)
+{
+  return __builtin_copysignf (x, y);
+}
+
+typedef double __attribute__ ((vector_size (16))) v2df;
+typedef double __attribute__ ((vector_size (32))) v4df;
+typedef double __attribute__ ((vector_size (64))) v8df;
+
+v2df cs_v2df (v2df x, v2df y)
+{
+  return __builtin_ia32_copysignpd (x, y);
+}
+
+v4df cs_v4df (v4df x, v4df y)
+{
+  return __builtin_ia32_copysignpd256 (x, y);
+}
+
+v8df cs_v8df (v8df x, v8df y)
+{
+  return __builtin_ia32_copysignpd512 (x, y);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c b/gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c
new file mode 100644
index 0000000..3ea689e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -mno-avx512vl -mprefer-vector-width=512 -O2" } */
+/* { dg-final { scan-assembler-not "vmovddup\[^\n\]*%xmm16" } } */
+
+typedef long long __attribute__ ((vector_size (16))) v2di;
+
+v2di bcst (long long ll)
+{
+  register long long x asm ("xmm16") = ll;
+
+  asm ("" : "+v" (x));
+  return (v2di) {x, x};
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr110018-1.c b/gcc/testsuite/gcc.target/i386/pr110018-1.c
new file mode 100644
index 0000000..b6a3be7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110018-1.c
@@ -0,0 +1,94 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2 -mavx512dq" } */
+/* { dg-final { scan-assembler-times {(?n)vcvttp[dsh]2[dqw]} 5 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvt[dqw]*2p[dsh]} 5 } } */
+
+void
+foo (double* __restrict a, signed char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo1 (float* __restrict a, signed char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
+
+void
+foo2 (_Float16* __restrict a, signed char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+  a[4] = b[4];
+  a[5] = b[5];
+  a[6] = b[6];
+  a[7] = b[7];
+}
+
+void
+foo3 (double* __restrict a, signed short* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo4 (float* __restrict a, signed char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
+
+void
+foo5 (double* __restrict b, signed char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo6 (float* __restrict b, signed char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
+
+void
+foo7 (_Float16* __restrict b, signed char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+  a[4] = b[4];
+  a[5] = b[5];
+  a[6] = b[6];
+  a[7] = b[7];
+}
+
+void
+foo8 (double* __restrict b, signed short* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo9 (float* __restrict b, signed char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr110018-2.c b/gcc/testsuite/gcc.target/i386/pr110018-2.c
new file mode 100644
index 0000000..a663e07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110018-2.c
@@ -0,0 +1,94 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2 -mavx512dq" } */
+/* { dg-final { scan-assembler-times {(?n)vcvttp[dsh]2[dqw]} 5 } } */
+/* { dg-final { scan-assembler-times {(?n)vcvt[dqw]*2p[dsh]} 5 } } */
+
+void
+foo (double* __restrict a, unsigned char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo1 (float* __restrict a, unsigned char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
+
+void
+foo2 (_Float16* __restrict a, unsigned char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+  a[4] = b[4];
+  a[5] = b[5];
+  a[6] = b[6];
+  a[7] = b[7];
+}
+
+void
+foo3 (double* __restrict a, unsigned short* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo4 (float* __restrict a, unsigned char* b)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
+
+void
+foo5 (double* __restrict b, unsigned char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo6 (float* __restrict b, unsigned char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
+
+void
+foo7 (_Float16* __restrict b, unsigned char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+  a[4] = b[4];
+  a[5] = b[5];
+  a[6] = b[6];
+  a[7] = b[7];
+}
+
+void
+foo8 (double* __restrict b, unsigned short* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+}
+
+void
+foo9 (float* __restrict b, unsigned char* a)
+{
+  a[0] = b[0];
+  a[1] = b[1];
+  a[2] = b[2];
+  a[3] = b[3];
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr79173-11.c b/gcc/testsuite/gcc.target/i386/pr79173-11.c
new file mode 100644
index 0000000..ee45afa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79173-11.c
@@ -0,0 +1,39 @@
+/* PR middle-end/79173 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-stack-protector -masm=att" } */
+/* { dg-final { scan-assembler-times "addq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "adcq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "subq\t%r\[^\n\r]*, \\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 8\\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 16\\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "sbbq\t%r\[^\n\r]*, 24\\\(%rdi\\\)" 1 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "addl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "adcl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "subl\t%e\[^\n\r]*, \\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 4\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 8\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "sbbl\t%e\[^\n\r]*, 12\\\(%e\[^\n\r]*\\\)" 1 { target ia32 } } } */
+
+void
+foo (unsigned long *p, unsigned long *q)
+{
+  unsigned long c;
+  p[0] = __builtin_addcl (p[0], q[0], 0, &c);
+  p[1] = __builtin_addcl (p[1], q[1], c, &c);
+  p[2] = __builtin_addcl (p[2], q[2], c, &c);
+  p[3] = __builtin_addcl (p[3], q[3], c, &c);
+}
+
+void
+bar (unsigned long *p, unsigned long *q)
+{
+  unsigned long c;
+  p[0] = __builtin_subcl (p[0], q[0], 0, &c);
+  p[1] = __builtin_subcl (p[1], q[1], c, &c);
+  p[2] = __builtin_subcl (p[2], q[2], c, &c);
+  p[3] = __builtin_subcl (p[3], q[3], c, &c);
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse2-v1ti-mov-2.c b/gcc/testsuite/gcc.target/i386/sse2-v1ti-mov-2.c
new file mode 100644
index 0000000..7e89085
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse2-v1ti-mov-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef unsigned __int128 uv1ti __attribute__ ((__vector_size__ (16)));
+typedef unsigned long uv2di __attribute__ ((__vector_size__ (16)));
+typedef unsigned int uv4si __attribute__ ((__vector_size__ (16)));
+typedef unsigned short uv8hi __attribute__ ((__vector_size__ (16)));
+typedef unsigned char uv16qi __attribute__ ((__vector_size__ (16)));
+
+uv1ti foo1(__int128 x) { return (uv1ti)x; }
+uv2di foo2(__int128 x) { return (uv2di)x; }
+uv4si foo4(__int128 x) { return (uv4si)x; }
+uv8hi foo8(__int128 x) { return (uv8hi)x; }
+uv16qi foo16(__int128 x) { return (uv16qi)x; }
+
+/* { dg-final { scan-assembler-not "%\[er\]sp" } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-partial-vectors-1.c b/gcc/testsuite/gcc.target/i386/vect-partial-vectors-1.c
new file mode 100644
index 0000000..3834720
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-partial-vectors-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f -mavx512vl -mprefer-vector-width=512 --param vect-partial-vector-usage=1" } */
+
+void foo (int * __restrict a, int *b)
+{
+  for (int i = 0; i < 4; ++i)
+    a[i] = b[i] + 42;
+}
+
+/* We do not want to optimize this using masked AVX or AXV512
+   but unmasked SSE.  */
+/* { dg-final { scan-assembler-not "\[yz\]mm" } } */
+/* { dg-final { scan-assembler "xmm" } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-partial-vectors-2.c b/gcc/testsuite/gcc.target/i386/vect-partial-vectors-2.c
new file mode 100644
index 0000000..4ab2cbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-partial-vectors-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f -mavx512vl -mprefer-vector-width=512 --param vect-partial-vector-usage=1" } */
+
+void foo (int * __restrict a, int *b)
+{
+  for (int i = 0; i < 7; ++i)
+    a[i] = b[i] + 42;
+}
+
+/* We want to optimize this using masked AVX, not AXV512 or SSE.  */
+/* { dg-final { scan-assembler-not "zmm" } } */
+/* { dg-final { scan-assembler "ymm\[^\r\n\]*\{%k" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-8.c
new file mode 100644
index 0000000..eedcfcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-8.c
@@ -0,0 +1,58 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target p9vector_hw } */
+/* { dg-options "-mdejagnu-cpu=power9 -save-temps" } */
+
+#include <altivec.h>
+#include <stdlib.h>
+
+#if DEBUG
+#include <stdio.h>
+#endif
+
+vector unsigned long long int
+get_exponents (__ieee128 *p)
+{
+  __ieee128 source = *p;
+
+  return scalar_extract_exp_to_vec (source);
+}
+
+int
+main ()
+{
+  vector unsigned long long int result, exp_result;
+  union conv128_t
+   {
+     __ieee128 val_ieee128;
+     __int128  val_int128;
+  } source;
+  
+#ifdef _BIG_ENDIAN
+  exp_result[1] = 0x0ULL;
+  exp_result[0] = 0x1234ULL;
+#else
+  exp_result[0] = 0x0ULL;
+  exp_result[1] = 0x1234ULL;
+#endif
+  source.val_int128 = 0x923456789ABCDEF0ULL;
+  source.val_int128 = (source.val_int128 << 64) | 0x123456789ABCDEFULL;
+
+  result = get_exponents (&source.val_ieee128);
+
+  if ((result[0] != exp_result[0]) || (result[1] != exp_result[1]))
+#if DEBUG
+    {
+      printf("result[0] = 0x%llx; exp_result[0] = 0x%llx\n",
+	     result[0], exp_result[0]);
+      printf("result[1] = 0x%llx; exp_result[1] = 0x%llx\n",
+	     result[1], exp_result[1]);
+    }
+#else
+    abort();
+#endif
+  return 0;
+}
+
+/* Check that the expected extract exponent instruction is generated. */
+/* { dg-final { scan-assembler-times {\mxsxexpqp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-8.c
new file mode 100644
index 0000000..69a908a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-8.c
@@ -0,0 +1,65 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target p9vector_hw } */
+/* { dg-options "-mdejagnu-cpu=power9 -save-temps" } */
+
+#include <altivec.h>
+#include <stdlib.h>
+
+#if DEBUG
+#include <stdio.h>
+#endif
+
+vector unsigned __int128
+get_significand (__ieee128 *p)
+{
+  __ieee128 source = *p;
+
+  return scalar_extract_sig_to_vec(source);
+}
+
+int
+main ()
+{
+  #define NOT_ZERO_OR_DENORMAL  0x1000000000000
+
+  union conv128_t
+   {
+     __ieee128 val_ieee128;
+     unsigned long long int val_ull[2];
+     unsigned __int128  val_uint128;
+     vector unsigned __int128  val_vuint128;
+  } source, result, exp_result;
+  
+  /* Result is not zero or denormal.  */
+#ifdef _BIG_ENDIAN
+  exp_result.val_ull[0] = 0x00056789ABCDEF0ULL | NOT_ZERO_OR_DENORMAL;
+  exp_result.val_ull[1] = 0x123456789ABCDEFULL;
+#else
+  exp_result.val_ull[1] = 0x00056789ABCDEF0ULL | NOT_ZERO_OR_DENORMAL;
+  exp_result.val_ull[0] = 0x123456789ABCDEFULL;
+#endif
+  source.val_uint128 = 0x923456789ABCDEF0ULL;
+  source.val_uint128 = (source.val_uint128 << 64) | 0x123456789ABCDEFULL;
+
+  /* Note, bits[0:14] are set to 0, bit[15] is 0 if the input was zero or
+     Denormal, 1 otherwise.  */
+  result.val_vuint128 = get_significand (&source.val_ieee128);
+
+  if ((result.val_ull[0] != exp_result.val_ull[0])
+      || (result.val_ull[1] != exp_result.val_ull[1]))
+#if DEBUG
+    {
+      printf("result[0] = 0x%llx; exp_result[0] = 0x%llx\n",
+	     result.val_ull[0], exp_result.val_ull[0]);
+      printf("result[1] = 0x%llx; exp_result[1] = 0x%llx\n",
+	     result.val_ull[1], exp_result.val_ull[1]);
+    }
+#else
+    abort();
+#endif
+  return 0;
+}
+
+/* Check that the expected extract significand instruction is generated. */
+/* { dg-final { scan-assembler-times {\mxsxsigqp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
new file mode 100644
index 0000000..f0e03c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-16.c
@@ -0,0 +1,103 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target p9vector_hw } */
+/* { dg-options "-mdejagnu-cpu=power9 -save-temps" } */
+
+#include <altivec.h>
+#include <stdlib.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+__ieee128
+insert_exponent (vector unsigned __int128 *significand_p,
+		 vector unsigned long long int *exponent_p)
+{
+  vector unsigned __int128 significand = *significand_p;
+  vector unsigned long long int exponent = *exponent_p;
+
+  return scalar_insert_exp (significand, exponent);
+}
+
+__ieee128
+insert_exponent2 (unsigned __int128 significand,
+		 unsigned long long int exponent)
+{
+   return scalar_insert_exp (significand, exponent);
+}
+
+int
+main ()
+{
+  __ieee128 val_ieee128, result_ieee128, exp_result_ieee128;
+  unsigned __int128 val_int128;
+  unsigned long long int  val_ull;
+  union conv128_t
+   {
+     __ieee128 val_ieee128;
+     vector unsigned __int128 val_vint128;
+     vector unsigned long long int  val_vull;
+  } result, exp_result, significand;
+
+  vector unsigned long long int exponent;
+
+  /* Scalar argument test */
+  val_ieee128 = 0xFEDCBA9876543210ULL;
+  val_ull = 0x5678;
+#ifdef _BIG_ENDIAN
+  exp_result.val_vull[1] = 0xfedcba9876543210;  
+  exp_result.val_vull[0] = 0x5678000000000000ULL;
+#else
+  exp_result.val_vull[0] = 0xfedcba9876543210;  
+  exp_result.val_vull[1] = 0x5678000000000000ULL;
+#endif
+  result_ieee128 = insert_exponent2 (val_ieee128, val_ull);
+
+  if (result_ieee128 != exp_result.val_ieee128)
+#ifdef DEBUG
+    {
+      result.val_ieee128 = result_ieee128;
+      printf("Scalar argument ERROR:\n");
+      printf(" val_ieee128 = 0x%llx %llx\n",
+	     result.val_vull[1], result.val_vull[0]);
+      printf(" exp_val_ieee128 = 0x%llx %llx\n",
+	     exp_result.val_vull[1], exp_result.val_vull[0]);
+    }
+#else
+    abort ();
+#endif
+
+  /* Vector argument test */
+  significand.val_vull[0] = 0xFEDCBA9876543210ULL;
+  significand.val_vull[1] = 0x7FFF12345678ABCDULL;  /* positive value */
+
+  exponent[0] = 0x5678;
+  exponent[1] = 0x1234;
+
+#ifdef _BIG_ENDIAN
+  exp_result.val_vull[0] = 0xD678BA9876543210ULL;
+  exp_result.val_vull[1] = 0x7FFF12345678ABCDULL;
+#else
+  exp_result.val_vull[0] = 0xFEDCBA9876543210ULL;
+  exp_result.val_vull[1] = 0x123412345678ABCDULL;
+#endif
+  result.val_ieee128 = insert_exponent(&significand.val_vint128, &exponent);
+  
+  if (result.val_ieee128 != exp_result.val_ieee128)
+#ifdef DEBUG
+    {
+      printf("Vector argument ERROR:\n");
+      printf(" result = 0x%llx %llx\n",
+	     result.val_vull[1], result.val_vull[0]);
+      printf(" exp_result = 0x%llx %llx\n",
+	     exp_result.val_vull[1], exp_result.val_vull[0]);
+    }
+#else
+    abort ();
+#endif
+
+}
+
+/* Check that the expected insert exponent instruction is generated. */
+/* { dg-final { scan-assembler-times {\mxsiexpqp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c
new file mode 100644
index 0000000..542e267
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target has_arch_ppc64 } } */
+/* { dg-options "-O2" } */
+
+#define C1 0x2351847027482577ULL
+#define C2 0x2351847027482578ULL
+
+void __attribute__ ((noinline)) foo (long long *a)
+{
+  *a++ = C1;
+  *a++ = C2;
+}
+
+void __attribute__ ((noinline)) foo1 (long long *a, long long b)
+{
+  *a++ = C1;
+  if (b)
+    *a++ = C2;
+}
+
+/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c
new file mode 100644
index 0000000..565b75a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/try_const_anchors_ice.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* __builtin_stack_restore could generates {[%1:DI]=0;} in BLK mode,
+   it could assert in try_const_anchors which only accepts SCALAR_INT.  */
+
+long
+foo (const int val)
+{
+  if (val == (0))
+    return 0;
+  void *p = __builtin_stack_save ();
+  char c = val;
+  __builtin_stack_restore (p);
+  return c;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c
new file mode 100644
index 0000000..aaafb08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c
@@ -0,0 +1,15 @@
+/* Verify that fcsr instructions emitted.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-O" } */
+
+extern int foo (void);
+
+void __attribute__ ((interrupt))
+sub (void)
+{
+  foo ();
+}
+
+/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */
+/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c
new file mode 100644
index 0000000..ea22e6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c
@@ -0,0 +1,15 @@
+/* Verify that fcsr instructions emitted.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-O" } */
+
+extern int foo (void);
+extern float interrupt_count;
+void __attribute__ ((interrupt))
+sub (void)
+{
+  interrupt_count++;
+}
+
+/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */
+/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c
new file mode 100644
index 0000000..5e7eac4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c
@@ -0,0 +1,14 @@
+/* Verify that fcsr instructions are not emitted.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-O" } */
+
+extern int foo (void);
+
+void __attribute__ ((interrupt))
+sub (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "frcsr\t" } } */
+/* { dg-final { scan-assembler-not "fscsr\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index ff3633b..d7052b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -32,12 +32,16 @@
     assert (as##TYPE[i] == (VAL >> (i % 4)));
 
 #define RUN_ALL()	\
+ RUN(int8_t, 1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, 1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, 3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, 5)	\
  RUN(uint64_t, 6)       \
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index 557a7c8..befa4b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -3,10 +3,6 @@
 
 #include "shift-template.h"
 
-/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
-   We don't check the assembler number since lacking patterns make
-   auto-vectorization inconsistent in LMUL = 1/2/4/8.  */
-
-/* { dg-final { scan-assembler {\tvsll\.vv} } } */
-/* { dg-final { scan-assembler {\tvsrl\.vv} } } */
-/* { dg-final { scan-assembler {\tvsra\.vv} } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index 01a9cb2..976b29f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -3,6 +3,6 @@
 
 #include "shift-template.h"
 
-/* { dg-final { scan-assembler-times {\tvsll\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
index 16ae48c..ca1b96f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
@@ -16,14 +16,17 @@
       dst[i] = a[i] >> b[i];					\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST1_TYPE(int8_t)	\
+ TEST1_TYPE(uint8_t)	\
  TEST1_TYPE(int16_t)	\
  TEST1_TYPE(uint16_t)	\
  TEST1_TYPE(int32_t)	\
  TEST1_TYPE(uint32_t)	\
  TEST1_TYPE(int64_t)	\
  TEST1_TYPE(uint64_t)   \
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index 8bdc7a2..12fb952 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vadd-template.h"
 
@@ -44,24 +44,36 @@
     assert (aim##TYPE[i] == VAL - 16);
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
- RUN(uint64_t, 6)    \
+ RUN(uint64_t, 6)	\
+ RUN(float, -5)		\
+ RUN(double, 6)		\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
- RUN2(uint64_t, 12)   \
+ RUN2(uint64_t, 12)	\
+ RUN2(float, -11)	\
+ RUN2(double, 12)	\
+ RUN3M(int8_t, 13)	\
+ RUN3(uint8_t, 14)	\
  RUN3M(int16_t, 13)	\
  RUN3(uint16_t, 14)	\
  RUN3M(int32_t, 15)	\
  RUN3(uint32_t, 16)	\
  RUN3M(int64_t, 17)	\
- RUN3(uint64_t, 18)
+ RUN3(uint64_t, 18)	\
+ RUN3(float, 17)	\
+ RUN3M(double, 18)	\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
index 799ed27..cd0da74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
@@ -1,7 +1,8 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vadd-template.h"
 
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
index 64c2eee..30c3ef7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
@@ -1,7 +1,8 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vadd-template.h"
 
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
index cd945d4..e05b9c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
@@ -32,25 +32,39 @@
       dst[i] = a[i] - 16;				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST_TYPE(_Float16)	\
+ TEST_TYPE(float)	\
+ TEST_TYPE(double)	\
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
  TEST2_TYPE(uint64_t)   \
+ TEST2_TYPE(_Float16)	\
+ TEST2_TYPE(float)	\
+ TEST2_TYPE(double)	\
+ TEST3M_TYPE(int8_t)	\
+ TEST3_TYPE(uint8_t)	\
  TEST3M_TYPE(int16_t)	\
  TEST3_TYPE(uint16_t)	\
  TEST3M_TYPE(int32_t)	\
  TEST3_TYPE(uint32_t)	\
  TEST3M_TYPE(int64_t)	\
- TEST3_TYPE(uint64_t)
+ TEST3_TYPE(uint64_t)   \
+ TEST3M_TYPE(_Float16)	\
+ TEST3_TYPE(float)	\
+ TEST3M_TYPE(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
new file mode 100644
index 0000000..30b467f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c
@@ -0,0 +1,54 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vadd-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 0;             		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 0;            		\
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == VAL);
+
+#define RUN3(TYPE,VAL)				\
+  TYPE ai##TYPE[SZ];	  	        	\
+  for (int i = 0; i < SZ; i++)			\
+    ai##TYPE[i] = VAL;				\
+  vaddi_##TYPE (ai##TYPE, ai##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (ai##TYPE[i] == VAL + 15);
+
+#define RUN3M(TYPE,VAL)				\
+  TYPE aim##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    aim##TYPE[i] = VAL;				\
+  vaddim_##TYPE (aim##TYPE, aim##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (aim##TYPE[i] == VAL - 16);
+
+#define RUN_ALL()	\
+ RUN(_Float16, 4)	\
+ RUN2(_Float16, 10)	\
+ RUN3M(_Float16, 17)	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index c13755e..3fa6cf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == (VAL & -16));
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
  RUN2(uint64_t, 12)	\
+ RUN3M(int8_t, 13)	\
+ RUN3(uint8_t, 14)	\
  RUN3M(int16_t, 13)	\
  RUN3(uint16_t, 14)	\
  RUN3M(int32_t, 15)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
index 24fc70b..f7636ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vand-template.h"
 
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
index 67f37c1..dee8a2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vand-template.h"
 
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
index 5cabe07..e240959 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] & -16;				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)	\
+ TEST3_TYPE(uint8_t)	\
  TEST3M_TYPE(int16_t)	\
  TEST3_TYPE(uint16_t)	\
  TEST3M_TYPE(int32_t)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index 5de3391..2cd841f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vdiv-template.h"
 
@@ -28,18 +28,26 @@
     assert (as##TYPE[i] == 5);
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN(float, -5)		\
+ RUN(double, 6)		\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
- RUN2(uint64_t, 12)
+ RUN2(uint64_t, 12)	\
+ RUN2(float, -11)	\
+ RUN2(double, 12)	\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index 1dce9dd..604d9ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -1,10 +1,15 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vdiv-template.h"
 
 /* Currently we use an epilogue loop which also contains vdivs.  Therefore we
-   expect 10 vdiv[u]s instead of 6.  */
+   expect 14 vdiv[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */
+
+/* Division by constant is done by calculating a reciprocal and
+   then multiplying.  Hence we do not expect 6 vfdivs.  */
+/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 16a18c4..2688403 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -1,10 +1,15 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vdiv-template.h"
 
 /* Currently we use an epilogue loop which also contains vdivs.  Therefore we
-   expect 10 vdiv[u]s instead of 6.  */
+   expect 14 vdiv[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */
+
+/* Division by constant is done by calculating a reciprocal and
+   then multiplying.  Hence we do not expect 6 vfdivs.  */
+/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
index f8d3bfd..7b0f579 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
@@ -17,17 +17,27 @@
   }
 
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST_TYPE(_Float16)	\
+ TEST_TYPE(float)	\
+ TEST_TYPE(double)	\
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
- TEST2_TYPE(uint64_t)
+ TEST2_TYPE(uint64_t)	\
+ TEST2_TYPE(_Float16)	\
+ TEST2_TYPE(float)	\
+ TEST2_TYPE(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
new file mode 100644
index 0000000..7407a4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vdiv-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = VAL * 3;       		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vdiv_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 3);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = VAL * 5;			\
+  vdivs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 5);
+
+#define RUN_ALL()	\
+ RUN(_Float16, 4)	\
+ RUN2(_Float16, 10)	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index cf184e2..20aceb3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmax-template.h"
 
@@ -27,19 +27,28 @@
   for (int i = 0; i < SZ; i++)			\
     assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
 
+
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN(float, -5)		\
+ RUN(double, 6)		\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
- RUN2(uint64_t, 12)
+ RUN2(uint64_t, 12)	\
+ RUN2(float, -11)	\
+ RUN2(double, 12)	\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
index 46a3212..fbfa3ab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
@@ -1,7 +1,8 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmax-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvfmax\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
index 9bbaf76..cf01ebc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
@@ -1,7 +1,8 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmax-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvfmax\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
index fc6a07e..54828cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
@@ -16,19 +16,28 @@
       dst[i] = a[i] > b ? a[i] : b;			\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST_TYPE(_Float16)	\
+ TEST_TYPE(float)	\
+ TEST_TYPE(double)	\
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
- TEST2_TYPE(uint64_t)
+ TEST2_TYPE(uint64_t)	\
+ TEST2_TYPE(_Float16)	\
+ TEST2_TYPE(float)	\
+ TEST2_TYPE(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
new file mode 100644
index 0000000..60226b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c
@@ -0,0 +1,38 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vmax-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 0;             		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vmax_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 0 > VAL ? 0 : VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 0;				\
+  vmaxs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
+
+
+#define RUN_ALL()	\
+ RUN(_Float16, 4)	\
+ RUN2(_Float16, 10)	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index b461f8b..2babc70 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmin-template.h"
 
@@ -28,18 +28,26 @@
     assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
- RUN(uint64_t, 6)    \
+ RUN(uint64_t, 6)	\
+ RUN(float, -5)		\
+ RUN(double, 6)		\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
- RUN2(uint64_t, 12)
+ RUN2(uint64_t, 12)	\
+ RUN2(float, -11)	\
+ RUN2(double, 12)	\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
index da3bb17..8764073 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
@@ -1,7 +1,8 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmin-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvfmin\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
index 07278b2..193dacc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
@@ -1,7 +1,8 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmin-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvfmin\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
index 06f6b95..ca0d4e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
@@ -16,19 +16,28 @@
       dst[i] = a[i] < b ? a[i] : b;			\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST_TYPE(_Float16)	\
+ TEST_TYPE(float)	\
+ TEST_TYPE(double)	\
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
- TEST2_TYPE(uint64_t)
+ TEST2_TYPE(uint64_t)	\
+ TEST2_TYPE(_Float16)	\
+ TEST2_TYPE(float)	\
+ TEST2_TYPE(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
new file mode 100644
index 0000000..2f74e80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vmin-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 0;             		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vmin_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 0 < VAL ? 0 : VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 0;				\
+  vmins_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
+
+#define RUN_ALL()	\
+ RUN(_Float16, 4)	\
+ RUN2(_Float16, 10)	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index e8441c0..390e0b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmul-template.h"
 
@@ -15,7 +15,7 @@
     a##TYPE[i] = 2;				\
     b##TYPE[i] = VAL;           		\
   }                             		\
-  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  vmul_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
   for (int i = 0; i < SZ; i++)			\
     assert (a##TYPE[i] == 2 * VAL);
 
@@ -23,23 +23,31 @@
   TYPE as##TYPE[SZ];				\
   for (int i = 0; i < SZ; i++)			\
     as##TYPE[i] = 3;            		\
-  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  vmuls_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
   for (int i = 0; i < SZ; i++)			\
     assert (as##TYPE[i] == 3 * VAL);
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN(float, -5)		\
+ RUN(double, 6)		\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
- RUN2(uint64_t, 12)
+ RUN2(uint64_t, 12)	\
+ RUN2(float, -11)	\
+ RUN2(double, 12)	\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index f4df04d..7d3dfad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmul-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index f436b8a..a549d6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vmul-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
index 37f7797..4b81f52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
@@ -2,7 +2,7 @@
 
 #define TEST_TYPE(TYPE) 				\
   __attribute__((noipa))				\
-  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
+  void vmul_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)	\
   {							\
     for (int i = 0; i < n; i++)				\
       dst[i] = a[i] * b[i];				\
@@ -10,25 +10,34 @@
 
 #define TEST2_TYPE(TYPE) 				\
   __attribute__((noipa))				\
-  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
+  void vmuls_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)	\
   {							\
     for (int i = 0; i < n; i++)				\
       dst[i] = a[i] * b;				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST_TYPE(_Float16)	\
+ TEST_TYPE(float)	\
+ TEST_TYPE(double)	\
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
- TEST2_TYPE(uint64_t)
+ TEST2_TYPE(uint64_t)	\
+ TEST2_TYPE(_Float16)	\
+ TEST2_TYPE(float)	\
+ TEST2_TYPE(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
new file mode 100644
index 0000000..aa056e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vmul-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 2;				\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 2 * VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 3;            		\
+  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 3 * VAL);
+
+#define RUN_ALL()	\
+ RUN(_Float16, 4)	\
+ RUN2(_Float16, 10)	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index 5401e8d..f6b3770 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == (VAL | -16));
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
  RUN2(uint64_t, 12)	\
+ RUN3M(int8_t, 13)	\
+ RUN3(uint8_t, 14)	\
  RUN3M(int16_t, 13)	\
  RUN3(uint16_t, 14)	\
  RUN3M(int32_t, 15)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
index fc76d1c..70ea8ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
index ae115a2..44d09a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
index e60146c..3daad2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] | -16;				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)	\
+ TEST3_TYPE(uint8_t)	\
  TEST3M_TYPE(int16_t)	\
  TEST3_TYPE(uint16_t)	\
  TEST3M_TYPE(int32_t)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index 4a4c064..58b69ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -28,12 +28,16 @@
     assert (as##TYPE[i] == 89 % VAL);
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index df99f50..86607d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -1,10 +1,9 @@
-/* { dg-do compile } */
 /* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include "vrem-template.h"
 
 /* Currently we use an epilogue loop which also contains vrems.  Therefore we
-   expect 10 vrem[u]s instead of 6.  */
+   expect 14 vrem[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 3cff13a..b7bc1cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -4,7 +4,7 @@
 #include "vrem-template.h"
 
 /* Currently we use an epilogue loop which also contains vrems.  Therefore we
-   expect 10 vrem[u]s instead of 6.  */
+   expect 14 vrem[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
index d5ef406..9c4e6ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
@@ -16,14 +16,17 @@
       dst[i] = a[i] % b;				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index 4f25487..28b2a0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vsub-template.h"
 
@@ -12,20 +12,20 @@
   TYPE b##TYPE[SZ];	  			\
   for (int i = 0; i < SZ; i++)			\
   {                             		\
-    a##TYPE[i] = 999;           		\
+    a##TYPE[i] = 123;           		\
     b##TYPE[i] = VAL;           		\
   }                             		\
   vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
   for (int i = 0; i < SZ; i++)			\
-    assert (a##TYPE[i] == 999 - VAL);
+    assert (a##TYPE[i] == 123 - VAL);
 
 #define RUN2(TYPE,VAL)				\
   TYPE as##TYPE[SZ];				\
   for (int i = 0; i < SZ; i++)			\
-    as##TYPE[i] = 999;            		\
+    as##TYPE[i] = 123;            		\
   vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
   for (int i = 0; i < SZ; i++)			\
-    assert (as##TYPE[i] == 999 - VAL);
+    assert (as##TYPE[i] == 123 - VAL);
 
 #define RUN3(TYPE)				\
   TYPE as2##TYPE[SZ];				\
@@ -44,30 +44,46 @@
     assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667)));
 
 #define RUN_ALL()	\
+ RUN(int8_t, 1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, 1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, 3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, 5)	\
  RUN(uint64_t, 6)	\
+ RUN(float, 5)		\
+ RUN(double, 6)		\
+ RUN2(int8_t, 7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, 7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, 9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, 11)	\
  RUN2(uint64_t, 12)	\
+ RUN2(float, 11)	\
+ RUN2(double, 12)	\
+ RUN3(int8_t)		\
+ RUN3(uint8_t)		\
  RUN3(int16_t)		\
  RUN3(uint16_t)		\
  RUN3(int32_t)		\
  RUN3(uint32_t)		\
  RUN3(int64_t)		\
  RUN3(uint64_t)		\
+ RUN3(float)		\
+ RUN3(double)		\
+ RUN4(int8_t)		\
+ RUN4(uint8_t)		\
  RUN4(int16_t)		\
  RUN4(uint16_t)		\
  RUN4(int32_t)		\
  RUN4(uint32_t)		\
  RUN4(int64_t)		\
- RUN4(uint64_t)
+ RUN4(uint64_t)		\
+ RUN4(float)		\
+ RUN4(double)		\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index a0d3802..f09d066 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -1,7 +1,13 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vsub-template.h"
 
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
+
+/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */
+
+/* Do not expect vfrsub for now, because we do not properly
+   handle vop.vx and vfop.vf yet.  */
+/* { dg-final { scan-assembler-times {\tvfrsub\.vv} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index 562c026..9f44f5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -1,7 +1,13 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vsub-template.h"
 
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
+
+/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */
+
+/* Do not expect vfrsub for now, because we do not properly
+   handle vop.vx and vfop.vf yet.  */
+/* { dg-final { scan-assembler-times {\tvfrsub\.vv} 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
index 47f07f1..d54b7ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
@@ -32,31 +32,53 @@
       dst[i] = 15 - a[i];				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST_TYPE(_Float16)	\
+ TEST_TYPE(float)	\
+ TEST_TYPE(double)	\
+
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
  TEST2_TYPE(uint64_t)
+ TEST2_TYPE(_Float16)	\
+ TEST2_TYPE(float)	\
+ TEST2_TYPE(double)	\
+
+ TEST3_TYPE(int8_t)	\
+ TEST3_TYPE(uint8_t)	\
  TEST3_TYPE(int16_t)	\
  TEST3_TYPE(uint16_t)	\
  TEST3_TYPE(int32_t)	\
  TEST3_TYPE(uint32_t)	\
  TEST3_TYPE(int64_t)	\
  TEST3_TYPE(uint64_t)	\
+ TEST3_TYPE(_Float16)	\
+ TEST3_TYPE(float)	\
+ TEST3_TYPE(double)	\
+
+ TEST4_TYPE(int8_t)	\
+ TEST4_TYPE(uint8_t)	\
  TEST4_TYPE(int16_t)	\
  TEST4_TYPE(uint16_t)	\
  TEST4_TYPE(int32_t)	\
  TEST4_TYPE(uint32_t)	\
  TEST4_TYPE(int64_t)	\
- TEST4_TYPE(uint64_t)
+ TEST4_TYPE(uint64_t)	\
+ TEST4_TYPE(_Float16)	\
+ TEST4_TYPE(float)	\
+ TEST4_TYPE(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
new file mode 100644
index 0000000..6ccec19
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c
@@ -0,0 +1,55 @@
+/* { dg-do run { target { riscv_vector && riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vsub-template.h"
+
+#include <assert.h>
+
+#define SZ 512
+
+#define RUN(TYPE,VAL)				\
+  TYPE a##TYPE[SZ];				\
+  TYPE b##TYPE[SZ];	  			\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = 999;           		\
+    b##TYPE[i] = VAL;           		\
+  }                             		\
+  vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == 999 - VAL);
+
+#define RUN2(TYPE,VAL)				\
+  TYPE as##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as##TYPE[i] = 999;            		\
+  vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as##TYPE[i] == 999 - VAL);
+
+#define RUN3(TYPE)				\
+  TYPE as2##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as2##TYPE[i] = i * 33 - 779;            	\
+  vsubi_##TYPE (as2##TYPE, as2##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as2##TYPE[i] == (TYPE)(-16 - (i * 33 - 779)));
+
+#define RUN4(TYPE)				\
+  TYPE as3##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+    as3##TYPE[i] = i * -17 + 667;            	\
+  vsubi2_##TYPE (as3##TYPE, as3##TYPE, SZ);	\
+  for (int i = 0; i < SZ; i++)			\
+    assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667)));
+
+#define RUN_ALL()	\
+ RUN(_Float16, 4)	\
+ RUN2(_Float16, 10)	\
+ RUN3(_Float16)		\
+ RUN4(_Float16)		\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index ab0975a..7239733 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == (VAL ^ -16));
 
 #define RUN_ALL()	\
+ RUN(int8_t, -1)	\
+ RUN(uint8_t, 2)	\
  RUN(int16_t, -1)	\
  RUN(uint16_t, 2)	\
  RUN(int32_t, -3)	\
  RUN(uint32_t, 4)	\
  RUN(int64_t, -5)	\
  RUN(uint64_t, 6)	\
+ RUN2(int8_t, -7)	\
+ RUN2(uint8_t, 8)	\
  RUN2(int16_t, -7)	\
  RUN2(uint16_t, 8)	\
  RUN2(int32_t, -9)	\
  RUN2(uint32_t, 10)	\
  RUN2(int64_t, -11)	\
  RUN2(uint64_t, 12)	\
+ RUN3M(int8_t, 13)	\
+ RUN3(uint8_t, 14)	\
  RUN3M(int16_t, 13)	\
  RUN3(uint16_t, 14)	\
  RUN3M(int32_t, 15)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
index fbef4a4..83b223e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vxor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
index 9729ad1..6ba007c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vxor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
index 370b242..b36698b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] ^ -16;				\
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()	\
+ TEST_TYPE(int8_t)	\
+ TEST_TYPE(uint8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(uint16_t)	\
  TEST_TYPE(int32_t)	\
  TEST_TYPE(uint32_t)	\
  TEST_TYPE(int64_t)	\
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)	\
+ TEST2_TYPE(uint8_t)	\
  TEST2_TYPE(int16_t)	\
  TEST2_TYPE(uint16_t)	\
  TEST2_TYPE(int32_t)	\
  TEST2_TYPE(uint32_t)	\
  TEST2_TYPE(int64_t)	\
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)	\
+ TEST3_TYPE(uint8_t)	\
  TEST3M_TYPE(int16_t)	\
  TEST3_TYPE(uint16_t)	\
  TEST3M_TYPE(int32_t)	\
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
index 09e8396..61eac38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index befb518..0bce836 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -20,3 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" } } */
+/* { dg-final { scan-assembler {\tvid\.v} } } */
+/* { dg-final { scan-assembler {\tvand} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
new file mode 100644
index 0000000..1a35bba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
+
+#include <stdint-gcc.h>
+
+void
+f (uint8_t *restrict a, uint8_t *restrict b, int n)
+{
+  for (int i = 0; i < n; ++i)
+    {
+      a[i * 8] = b[i * 8 + 3] + 1;
+      a[i * 8 + 1] = b[i * 8 + 2] + 2;
+      a[i * 8 + 2] = b[i * 8 + 1] + 3;
+      a[i * 8 + 3] = b[i * 8 + 0] + 4;
+      a[i * 8 + 4] = b[i * 8 + 7] + 5;
+      a[i * 8 + 5] = b[i * 8 + 6] + 6;
+      a[i * 8 + 6] = b[i * 8 + 5] + 7;
+      a[i * 8 + 7] = b[i * 8 + 4] + 8;
+    }
+}
+
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" } } */
+/* { dg-final { scan-assembler {\tvid\.v} } } */
+/* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
new file mode 100644
index 0000000..765ec51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c
@@ -0,0 +1,66 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */
+
+#include "slp-16.c"
+
+#define LIMIT 128
+void __attribute__ ((optimize (0)))
+f_golden (int8_t *restrict a, int8_t *restrict b, int n)
+{
+  for (int i = 0; i < n; ++i)
+    {
+      a[i * 8] = b[i * 8 + 3] + 1;
+      a[i * 8 + 1] = b[i * 8 + 2] + 2;
+      a[i * 8 + 2] = b[i * 8 + 1] + 3;
+      a[i * 8 + 3] = b[i * 8 + 0] + 4;
+      a[i * 8 + 4] = b[i * 8 + 7] + 5;
+      a[i * 8 + 5] = b[i * 8 + 6] + 6;
+      a[i * 8 + 6] = b[i * 8 + 5] + 7;
+      a[i * 8 + 7] = b[i * 8 + 4] + 8;
+    }
+}
+
+int
+main (void)
+{
+#define RUN(NUM)                                                               \
+  int8_t a_##NUM[NUM * 8 + 8] = {0};                                           \
+  int8_t a_golden_##NUM[NUM * 8 + 8] = {0};                                    \
+  int8_t b_##NUM[NUM * 8 + 8] = {0};                                           \
+  for (int i = 0; i < NUM * 8 + 8; i++)                                        \
+    {                                                                          \
+      if (i % NUM == 0)                                                        \
+	b_##NUM[i] = (i + NUM) % LIMIT;                                        \
+      else                                                                     \
+	b_##NUM[i] = (i - NUM) % (-LIMIT);                                     \
+    }                                                                          \
+  f (a_##NUM, b_##NUM, NUM);                                                   \
+  f_golden (a_golden_##NUM, b_##NUM, NUM);                                     \
+  for (int i = 0; i < NUM * 8 + 8; i++)                                        \
+    {                                                                          \
+      if (a_##NUM[i] != a_golden_##NUM[i])                                     \
+	__builtin_abort ();                                                    \
+    }
+
+  RUN (3);
+  RUN (5);
+  RUN (15);
+  RUN (16);
+  RUN (17);
+  RUN (31);
+  RUN (32);
+  RUN (33);
+  RUN (63);
+  RUN (64);
+  RUN (65);
+  RUN (127);
+  RUN (128);
+  RUN (129);
+  RUN (239);
+  RUN (359);
+  RUN (498);
+  RUN (799);
+  RUN (977);
+  RUN (5789);
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
index d864b54..5575ece 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "abs-template.h"
 
@@ -7,30 +7,32 @@
 
 #define SZ 128
 
-#define RUN(TYPE)				\
-  TYPE a##TYPE[SZ];				\
-  for (int i = 0; i < SZ; i++)			\
-    {                             		\
-      if (i & 1)				\
-	a##TYPE[i] = i - 64;            	\
-      else					\
-	a##TYPE[i] = i;            		\
-    }                             		\
-  vabs_##TYPE (a##TYPE, a##TYPE, SZ);	        \
-  for (int i = 0; i < SZ; i++)			\
-    {						\
-      if (i & 1)				\
-	assert (a##TYPE[i] == abs (i - 64));    \
-      else					\
-	assert (a##TYPE[i] == i);		\
+#define RUN(TYPE)					  \
+  TYPE a##TYPE[SZ];					  \
+  for (int i = 0; i < SZ; i++)				  \
+    {                             			  \
+      if (i & 1)					  \
+	a##TYPE[i] = i - 64;            		  \
+      else						  \
+	a##TYPE[i] = i;            			  \
+    }                             			  \
+  vabs_##TYPE (a##TYPE, a##TYPE, SZ);	        	  \
+  for (int i = 0; i < SZ; i++)				  \
+    {							  \
+      if (i & 1)					  \
+	assert (a##TYPE[i] == __builtin_abs (i - 64));	  \
+      else						  \
+	assert (a##TYPE[i] == i);			  \
     }
 
 
-#define RUN_ALL()	                        \
- RUN(int8_t)	                                \
- RUN(int16_t)	                                \
- RUN(int32_t)	                                \
- RUN(int64_t)
+#define RUN_ALL()					  \
+ RUN(int8_t)	                                	  \
+ RUN(int16_t)	                                	  \
+ RUN(int32_t)	                                	  \
+ RUN(int64_t)						  \
+ RUN(float)	                                	  \
+ RUN(double)						  \
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
index a8b92c9..dea790c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c
@@ -1,8 +1,9 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "abs-template.h"
 
 /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
 /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
index 2e7f086..b58f1aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c
@@ -1,8 +1,9 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "abs-template.h"
 
 /* { dg-final { scan-assembler-times {\tvseti?vli\s+[a-z0-9,]+,ta,mu} 4 } } */
 /* { dg-final { scan-assembler-times {\tvmslt\.vi} 4 } } */
 /* { dg-final { scan-assembler-times {\tvneg.v\sv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfabs.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
index 882de9f..08bd5b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-template.h
@@ -6,7 +6,7 @@
   void vabs_##TYPE (TYPE *dst, TYPE *a, int n)		\
   {							\
     for (int i = 0; i < n; i++)				\
-      dst[i] = abs (a[i]);				\
+      dst[i] = __builtin_abs (a[i]);				\
   }
 
 #define TEST_TYPE2(TYPE) 				\
@@ -14,13 +14,24 @@
   void vabs_##TYPE (TYPE *dst, TYPE *a, int n)		\
   {							\
     for (int i = 0; i < n; i++)				\
-      dst[i] = llabs (a[i]);				\
+      dst[i] = __builtin_llabs (a[i]);				\
+  }
+
+#define TEST_TYPE3(TYPE) 				\
+  __attribute__((noipa))				\
+  void vabs_##TYPE (TYPE *dst, TYPE *a, int n)		\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = __builtin_fabs (a[i]);				\
   }
 
 #define TEST_ALL()	\
  TEST_TYPE(int8_t)	\
  TEST_TYPE(int16_t)	\
  TEST_TYPE(int32_t)	\
- TEST_TYPE2(int64_t)
+ TEST_TYPE2(int64_t)	\
+ TEST_TYPE3(_Float16)	\
+ TEST_TYPE3(float)	\
+ TEST_TYPE3(double)	\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
new file mode 100644
index 0000000..65087d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "abs-template.h"
+
+#include <assert.h>
+
+#define SZ 128
+
+#define RUN(TYPE)					  \
+  TYPE a##TYPE[SZ];					  \
+  for (int i = 0; i < SZ; i++)				  \
+    {                             			  \
+      if (i & 1)					  \
+	a##TYPE[i] = i - 64;            		  \
+      else						  \
+	a##TYPE[i] = i;            			  \
+    }                             			  \
+  vabs_##TYPE (a##TYPE, a##TYPE, SZ);	        	  \
+  for (int i = 0; i < SZ; i++)				  \
+    {							  \
+      if (i & 1)					  \
+	assert (a##TYPE[i] == __builtin_abs (i - 64));    \
+      else						  \
+	assert (a##TYPE[i] == i);			  \
+    }
+
+
+#define RUN_ALL()					  \
+ RUN(_Float16)	                                	  \
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
new file mode 100644
index 0000000..01a5184
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+#include <assert.h>
+
+#define SZ 255
+
+#define EPS 1e-5
+
+#define RUN(TYPE)						\
+  TYPE a##TYPE[SZ];					      	\
+  for (int i = 0; i < SZ; i++)				      	\
+  {                             			      	\
+    a##TYPE[i] = (TYPE)i;             			      	\
+  }                             			      	\
+  vsqrt_##TYPE (a##TYPE, a##TYPE, SZ);	        	      	\
+  for (int i = 0; i < SZ; i++)				      	\
+    assert (__builtin_fabs				      	\
+	    (a##TYPE[i] -  __builtin_sqrtf ((TYPE)i)) < EPS);	\
+
+#define RUN_ALL()						\
+ RUN(float)	                                	      	\
+ RUN(double)	                                	      	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
new file mode 100644
index 0000000..a1874c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the Zvfh extension so define
+   it here instead of in the template directly (which is also
+   included by the run test that might need to be linked without
+   the extension).  */
+TEST_TYPE3(_Float16)
+
+/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
new file mode 100644
index 0000000..955621d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the Zvfh extension so define
+   it here instead of in the template directly (which is also
+   included by the run test that might need to be linked without
+   the extension).  */
+TEST_TYPE3(_Float16)
+
+/* { dg-final { scan-assembler-times {\tvfsqrt\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
new file mode 100644
index 0000000..314ea64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h
@@ -0,0 +1,31 @@
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n)		\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = __builtin_sqrtf (a[i]);			\
+  }
+
+#define TEST_TYPE2(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n)		\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = __builtin_sqrt (a[i]);			\
+  }
+
+#define TEST_TYPE3(TYPE) 				\
+  __attribute__((noipa))				\
+  void vsqrt_##TYPE (TYPE *dst, TYPE *a, int n)		\
+  {							\
+    for (int i = 0; i < n; i++)				\
+      dst[i] = __builtin_sqrtf16 (a[i]);		\
+  }
+
+#define TEST_ALL()					\
+ TEST_TYPE(float)					\
+ TEST_TYPE2(double)					\
+
+TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
new file mode 100644
index 0000000..5849e48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vfsqrt-template.h"
+
+/* We cannot link this without the Zvfh extension so define
+   it here instead of in the template directly.  */
+TEST_TYPE3(_Float16)
+
+#include <assert.h>
+
+#define SZ 255
+
+#define EPS 1e-5
+
+#define RUN(TYPE)						\
+  TYPE a##TYPE[SZ];						\
+  for (int i = 0; i < SZ; i++)				    	\
+  {                             			    	\
+    a##TYPE[i] = (TYPE)i;             			    	\
+  }                             			    	\
+  vsqrt_##TYPE (a##TYPE, a##TYPE, SZ);	        	    	\
+  for (int i = 0; i < SZ; i++)				    	\
+    assert (__builtin_fabs				    	\
+	    (a##TYPE[i] - __builtin_sqrtf ((TYPE)i)) < EPS);	\
+
+#define RUN_ALL()						\
+ RUN(_Float16)	                                	    	\
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
index abeb50f..f9fb126 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vneg-template.h"
 
@@ -13,7 +13,7 @@
   {                             		\
     a##TYPE[i] = i - 127;             		\
   }                             		\
-  vneg_##TYPE (a##TYPE, a##TYPE, SZ);	\
+  vneg_##TYPE (a##TYPE, a##TYPE, SZ);		\
   for (int i = 0; i < SZ; i++)			\
     assert (a##TYPE[i] == -(i - 127));
 
@@ -21,7 +21,9 @@
  RUN(int8_t)	                                \
  RUN(int16_t)	                                \
  RUN(int32_t)	                                \
- RUN(int64_t)
+ RUN(int64_t)					\
+ RUN(float)	                                \
+ RUN(double)					\
 
 int main ()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
index 69d9ebb..4a9ceb5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vneg-template.h"
 
 /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
index d2c2e17..2c5e2bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
 
 #include "vneg-template.h"
 
 /* { dg-final { scan-assembler-times {\tvneg\.v} 4 } } */
+/* { dg-final { scan-assembler-times {\tvfneg\.v} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
index 93e690f..892d9d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-template.h
@@ -13,6 +13,9 @@
  TEST_TYPE(int8_t)					\
  TEST_TYPE(int16_t)					\
  TEST_TYPE(int32_t)					\
- TEST_TYPE(int64_t)
+ TEST_TYPE(int64_t)					\
+ TEST_TYPE(_Float16)					\
+ TEST_TYPE(float)					\
+ TEST_TYPE(double)					\
 
 TEST_ALL()
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
new file mode 100644
index 0000000..64c965f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */
+
+#include "vneg-template.h"
+
+#include <assert.h>
+
+#define SZ 255
+
+#define RUN(TYPE)				\
+  TYPE a##TYPE[SZ];				\
+  for (int i = 0; i < SZ; i++)			\
+  {                             		\
+    a##TYPE[i] = i - 127;             		\
+  }                             		\
+  vneg_##TYPE (a##TYPE, a##TYPE, SZ);		\
+  for (int i = 0; i < SZ; i++)			\
+    assert (a##TYPE[i] == -(i - 127));
+
+#define RUN_ALL()	                        \
+ RUN(_Float16)	                                \
+
+int main ()
+{
+  RUN_ALL()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index c32c31e..9ed7c4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
index efeb23e..3e3ecd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
index 35b2aa8..f07b658 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
index 957d5b2..57bf8fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
index 398d0dc..8bc29c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
index 4d1b9e2..f6140fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
index 43acea6..7ab4bca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
index 2f38c3d..a501026 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
index 7449f63..d6e8248b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
index 248a304..08506e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
index a587dd4..ff92c39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
index 18dedb0..86a3f2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
index 61dbd5b..a64f82f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
index da7c462..6193d2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
index 7aaa6b3..267c1ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "merge-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
index 58c2cd8..b361a04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
index d88b6461..9e9123a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
index 110df49..0cefb24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
index aa32881..9df69a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
index 7117a49..e03f8e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
index 67b2e6f..c74ad03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
index 0ac9828..46c4a71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
 
 #include "perm.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
index cb216a9..8fe80e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
index 1b51b31..04906d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
index 4cae7f4..f5e9f9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
index e60b19f..8460491 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
index b619909..5394dec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
index b23df90..cee7efc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */
 
 #include "perm-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
index d935d36..49b2583 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_vector } } } */
-/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0" } */
+/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */
 
 #include "perm-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
new file mode 100644
index 0000000..9cb167a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx2di __attribute__((vector_size (16)));
+typedef int32_t vnx4si __attribute__((vector_size (16)));
+typedef int16_t vnx8hi __attribute__((vector_size (16)));
+typedef int8_t vnx16qi __attribute__((vector_size (16)));
+typedef _Float16 vnx8hf __attribute__((vector_size (16)));
+typedef float vnx4sf __attribute__((vector_size (16)));
+typedef double vnx2df __attribute__((vector_size (16)));
+
+
+#define VEC_EXTRACT(S,V,IDX)			\
+  S						\
+  __attribute__((noipa))			\
+  vec_extract_##V##_##IDX (V v)			\
+  {						\
+    return v[IDX];				\
+  }
+
+#define TEST_ALL1(T)				\
+  T (_Float16, vnx8hf, 0)			\
+  T (_Float16, vnx8hf, 3)			\
+  T (_Float16, vnx8hf, 7)			\
+  T (float, vnx4sf, 0)				\
+  T (float, vnx4sf, 1)				\
+  T (float, vnx4sf, 3)				\
+  T (double, vnx2df, 0)				\
+  T (double, vnx2df, 1)				\
+  T (int64_t, vnx2di, 0)			\
+  T (int64_t, vnx2di, 1)			\
+  T (int32_t, vnx4si, 0)			\
+  T (int32_t, vnx4si, 1)			\
+  T (int32_t, vnx4si, 3)			\
+  T (int16_t, vnx8hi, 0)			\
+  T (int16_t, vnx8hi, 2)			\
+  T (int16_t, vnx8hi, 6)			\
+  T (int8_t, vnx16qi, 0)			\
+  T (int8_t, vnx16qi, 1)			\
+  T (int8_t, vnx16qi, 7)			\
+  T (int8_t, vnx16qi, 11)			\
+  T (int8_t, vnx16qi, 15)			\
+
+TEST_ALL1 (VEC_EXTRACT)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*ta,\s*ma} 5 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*ta,\s*ma} 6 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*ta,\s*ma} 6 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*ta,\s*ma} 4 } } */
+
+/* { dg-final { scan-assembler-times {\tvslidedown.vi} 14 } } */
+/* { dg-final { scan-assembler-times {\tvslidedown.vx} 0 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.f.s} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmv.x.s} 13 } } */
+
+/* { dg-final { scan-assembler-not {\tsext} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
new file mode 100644
index 0000000..2837ff5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
@@ -0,0 +1,70 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx4di __attribute__((vector_size (32)));
+typedef int32_t vnx8si __attribute__((vector_size (32)));
+typedef int16_t vnx16hi __attribute__((vector_size (32)));
+typedef int8_t vnx32qi __attribute__((vector_size (32)));
+typedef _Float16 vnx16hf __attribute__((vector_size (32)));
+typedef float vnx8sf __attribute__((vector_size (32)));
+typedef double vnx4df __attribute__((vector_size (32)));
+
+#define VEC_EXTRACT(S,V,IDX)			\
+  S						\
+  __attribute__((noipa))			\
+  vec_extract_##V##_##IDX (V v)			\
+  {						\
+    return v[IDX];				\
+  }
+
+#define TEST_ALL2(T)				\
+  T (_Float16, vnx16hf, 0)			\
+  T (_Float16, vnx16hf, 3)			\
+  T (_Float16, vnx16hf, 7)			\
+  T (_Float16, vnx16hf, 8)			\
+  T (_Float16, vnx16hf, 15)			\
+  T (float, vnx8sf, 0)				\
+  T (float, vnx8sf, 1)				\
+  T (float, vnx8sf, 3)				\
+  T (float, vnx8sf, 4)				\
+  T (float, vnx8sf, 7)				\
+  T (double, vnx4df, 0)				\
+  T (double, vnx4df, 1)				\
+  T (double, vnx4df, 2)				\
+  T (double, vnx4df, 3)				\
+  T (int64_t, vnx4di, 0)			\
+  T (int64_t, vnx4di, 1)			\
+  T (int64_t, vnx4di, 2)			\
+  T (int64_t, vnx4di, 3)			\
+  T (int32_t, vnx8si, 0)			\
+  T (int32_t, vnx8si, 1)			\
+  T (int32_t, vnx8si, 3)			\
+  T (int32_t, vnx8si, 4)			\
+  T (int32_t, vnx8si, 7)			\
+  T (int16_t, vnx16hi, 0)			\
+  T (int16_t, vnx16hi, 1)			\
+  T (int16_t, vnx16hi, 7)			\
+  T (int16_t, vnx16hi, 8)			\
+  T (int16_t, vnx16hi, 15)			\
+  T (int8_t, vnx32qi, 0)			\
+  T (int8_t, vnx32qi, 1)			\
+  T (int8_t, vnx32qi, 15)			\
+  T (int8_t, vnx32qi, 16)			\
+  T (int8_t, vnx32qi, 31)			\
+
+TEST_ALL2 (VEC_EXTRACT)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m2,\s*ta,\s*ma} 5 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m2,\s*ta,\s*ma} 10 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m2,\s*ta,\s*ma} 10 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m2,\s*ta,\s*ma} 8 } } */
+
+/* { dg-final { scan-assembler-times {\tvslidedown.vi} 26 } } */
+/* { dg-final { scan-assembler-times {\tvslidedown.vx} 0 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.f.s} 14 } } */
+/* { dg-final { scan-assembler-times {\tvmv.x.s} 19 } } */
+
+/* { dg-final { scan-assembler-not {\tsext} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
new file mode 100644
index 0000000..47f30ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
@@ -0,0 +1,71 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx8di __attribute__((vector_size (64)));
+typedef int32_t vnx16si __attribute__((vector_size (64)));
+typedef int16_t vnx32hi __attribute__((vector_size (64)));
+typedef int8_t vnx64qi __attribute__((vector_size (64)));
+typedef _Float16 vnx32hf __attribute__((vector_size (64)));
+typedef float vnx16sf __attribute__((vector_size (64)));
+typedef double vnx8df __attribute__((vector_size (64)));
+
+#define VEC_EXTRACT(S,V,IDX)			\
+  S						\
+  __attribute__((noipa))			\
+  vec_extract_##V##_##IDX (V v)			\
+  {						\
+    return v[IDX];				\
+  }
+
+#define TEST_ALL3(T)				\
+  T (_Float16, vnx32hf, 0)			\
+  T (_Float16, vnx32hf, 3)			\
+  T (_Float16, vnx32hf, 7)			\
+  T (_Float16, vnx32hf, 8)			\
+  T (_Float16, vnx32hf, 16)			\
+  T (_Float16, vnx32hf, 31)			\
+  T (float, vnx16sf, 0)				\
+  T (float, vnx16sf, 2)				\
+  T (float, vnx16sf, 6)				\
+  T (float, vnx16sf, 8)				\
+  T (float, vnx16sf, 14)			\
+  T (double, vnx8df, 0)				\
+  T (double, vnx8df, 2)				\
+  T (double, vnx8df, 4)				\
+  T (double, vnx8df, 6)				\
+  T (int64_t, vnx8di, 0)			\
+  T (int64_t, vnx8di, 2)			\
+  T (int64_t, vnx8di, 4)			\
+  T (int64_t, vnx8di, 6)			\
+  T (int32_t, vnx16si, 0)			\
+  T (int32_t, vnx16si, 2)			\
+  T (int32_t, vnx16si, 6)			\
+  T (int32_t, vnx16si, 8)			\
+  T (int32_t, vnx16si, 14)			\
+  T (int16_t, vnx32hi, 0)			\
+  T (int16_t, vnx32hi, 2)			\
+  T (int16_t, vnx32hi, 14)			\
+  T (int16_t, vnx32hi, 16)			\
+  T (int16_t, vnx32hi, 30)			\
+  T (int8_t, vnx64qi, 0)			\
+  T (int8_t, vnx64qi, 2)			\
+  T (int8_t, vnx64qi, 30)			\
+  T (int8_t, vnx64qi, 32)			\
+  T (int8_t, vnx64qi, 63)			\
+
+TEST_ALL3 (VEC_EXTRACT)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m4,\s*ta,\s*ma} 5 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m4,\s*ta,\s*ma} 11 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m4,\s*ta,\s*ma} 10 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m4,\s*ta,\s*ma} 8 } } */
+
+/* { dg-final { scan-assembler-times {\tvslidedown.vi} 25 } } */
+/* { dg-final { scan-assembler-times {\tvslidedown.vx} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.f.s} 15 } } */
+/* { dg-final { scan-assembler-times {\tvmv.x.s} 19 } } */
+
+/* { dg-final { scan-assembler-not {\tsext} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
new file mode 100644
index 0000000..f7169f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
@@ -0,0 +1,74 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx16di __attribute__((vector_size (128)));
+typedef int32_t vnx32si __attribute__((vector_size (128)));
+typedef int16_t vnx64hi __attribute__((vector_size (128)));
+typedef int8_t vnx128qi __attribute__((vector_size (128)));
+typedef _Float16 vnx64hf __attribute__((vector_size (128)));
+typedef float vnx32sf __attribute__((vector_size (128)));
+typedef double vnx16df __attribute__((vector_size (128)));
+
+#define VEC_EXTRACT(S,V,IDX)			\
+  S						\
+  __attribute__((noipa))			\
+  vec_extract_##V##_##IDX (V v)			\
+  {						\
+    return v[IDX];				\
+  }
+
+#define TEST_ALL4(T)				\
+  T (_Float16, vnx64hf, 0)			\
+  T (_Float16, vnx64hf, 3)			\
+  T (_Float16, vnx64hf, 7)			\
+  T (_Float16, vnx64hf, 8)			\
+  T (_Float16, vnx64hf, 16)			\
+  T (_Float16, vnx64hf, 31)			\
+  T (_Float16, vnx64hf, 42)			\
+  T (_Float16, vnx64hf, 63)			\
+  T (float, vnx32sf, 0)				\
+  T (float, vnx32sf, 3)				\
+  T (float, vnx32sf, 12)			\
+  T (float, vnx32sf, 17)			\
+  T (float, vnx32sf, 14)			\
+  T (double, vnx16df, 0)			\
+  T (double, vnx16df, 4)			\
+  T (double, vnx16df, 8)			\
+  T (double, vnx16df, 12)			\
+  T (int64_t, vnx16di, 0)			\
+  T (int64_t, vnx16di, 4)			\
+  T (int64_t, vnx16di, 8)			\
+  T (int64_t, vnx16di, 12)			\
+  T (int32_t, vnx32si, 0)			\
+  T (int32_t, vnx32si, 4)			\
+  T (int32_t, vnx32si, 12)			\
+  T (int32_t, vnx32si, 16)			\
+  T (int32_t, vnx32si, 28)			\
+  T (int16_t, vnx64hi, 0)			\
+  T (int16_t, vnx64hi, 4)			\
+  T (int16_t, vnx64hi, 28)			\
+  T (int16_t, vnx64hi, 32)			\
+  T (int16_t, vnx64hi, 60)			\
+  T (int8_t, vnx128qi, 0)			\
+  T (int8_t, vnx128qi, 4)			\
+  T (int8_t, vnx128qi, 30)			\
+  T (int8_t, vnx128qi, 60)			\
+  T (int8_t, vnx128qi, 64)			\
+  T (int8_t, vnx128qi, 127)			\
+
+TEST_ALL4 (VEC_EXTRACT)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m8,\s*ta,\s*ma} 6 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m8,\s*ta,\s*ma} 13 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m8,\s*ta,\s*ma} 10 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m8,\s*ta,\s*ma} 8 } } */
+
+/* { dg-final { scan-assembler-times {\tvslidedown.vi} 23 } } */
+/* { dg-final { scan-assembler-times {\tvslidedown.vx} 7 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.f.s} 17 } } */
+/* { dg-final { scan-assembler-times {\tvmv.x.s} 20 } } */
+
+/* { dg-final { scan-assembler-not {\tsext} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
new file mode 100644
index 0000000..43110c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
@@ -0,0 +1,239 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
+
+#include <assert.h>
+
+#include "vec_extract-1.c"
+#include "vec_extract-2.c"
+#include "vec_extract-3.c"
+#include "vec_extract-4.c"
+
+#define CHECK(S, V, IDX)				\
+void check_##V##_##IDX ()				\
+  {							\
+    V v;						\
+    for (int i = 0; i < sizeof (V) / sizeof (S); i++)	\
+      v[i] = i;						\
+    S res = vec_extract_##V##_##IDX (v);		\
+    assert (res == v[IDX]);				\
+  }
+
+#define CHECK_ALL(T)					\
+  T (float, vnx4sf, 0)					\
+  T (float, vnx4sf, 1)					\
+  T (float, vnx4sf, 3)					\
+  T (double, vnx2df, 0)					\
+  T (double, vnx2df, 1)					\
+  T (int64_t, vnx2di, 0)				\
+  T (int64_t, vnx2di, 1)				\
+  T (int32_t, vnx4si, 0)				\
+  T (int32_t, vnx4si, 1)				\
+  T (int32_t, vnx4si, 3)				\
+  T (int16_t, vnx8hi, 0)				\
+  T (int16_t, vnx8hi, 2)				\
+  T (int16_t, vnx8hi, 6)				\
+  T (int8_t, vnx16qi, 0)				\
+  T (int8_t, vnx16qi, 1)				\
+  T (int8_t, vnx16qi, 7)				\
+  T (int8_t, vnx16qi, 11)				\
+  T (int8_t, vnx16qi, 15)				\
+  T (float, vnx8sf, 0)					\
+  T (float, vnx8sf, 1)					\
+  T (float, vnx8sf, 3)					\
+  T (float, vnx8sf, 4)					\
+  T (float, vnx8sf, 7)					\
+  T (double, vnx4df, 0)					\
+  T (double, vnx4df, 1)					\
+  T (double, vnx4df, 2)					\
+  T (double, vnx4df, 3)					\
+  T (int64_t, vnx4di, 0)				\
+  T (int64_t, vnx4di, 1)				\
+  T (int64_t, vnx4di, 2)				\
+  T (int64_t, vnx4di, 3)				\
+  T (int32_t, vnx8si, 0)				\
+  T (int32_t, vnx8si, 1)				\
+  T (int32_t, vnx8si, 3)				\
+  T (int32_t, vnx8si, 4)				\
+  T (int32_t, vnx8si, 7)				\
+  T (int16_t, vnx16hi, 0)				\
+  T (int16_t, vnx16hi, 1)				\
+  T (int16_t, vnx16hi, 7)				\
+  T (int16_t, vnx16hi, 8)				\
+  T (int16_t, vnx16hi, 15)				\
+  T (int8_t, vnx32qi, 0)				\
+  T (int8_t, vnx32qi, 1)				\
+  T (int8_t, vnx32qi, 15)				\
+  T (int8_t, vnx32qi, 16)				\
+  T (int8_t, vnx32qi, 31)				\
+  T (float, vnx16sf, 0)					\
+  T (float, vnx16sf, 2)					\
+  T (float, vnx16sf, 6)					\
+  T (float, vnx16sf, 8)					\
+  T (float, vnx16sf, 14)				\
+  T (double, vnx8df, 0)					\
+  T (double, vnx8df, 2)					\
+  T (double, vnx8df, 4)					\
+  T (double, vnx8df, 6)					\
+  T (int64_t, vnx8di, 0)				\
+  T (int64_t, vnx8di, 2)				\
+  T (int64_t, vnx8di, 4)				\
+  T (int64_t, vnx8di, 6)				\
+  T (int32_t, vnx16si, 0)				\
+  T (int32_t, vnx16si, 2)				\
+  T (int32_t, vnx16si, 6)				\
+  T (int32_t, vnx16si, 8)				\
+  T (int32_t, vnx16si, 14)				\
+  T (int16_t, vnx32hi, 0)				\
+  T (int16_t, vnx32hi, 2)				\
+  T (int16_t, vnx32hi, 14)				\
+  T (int16_t, vnx32hi, 16)				\
+  T (int16_t, vnx32hi, 30)				\
+  T (int8_t, vnx64qi, 0)				\
+  T (int8_t, vnx64qi, 2)				\
+  T (int8_t, vnx64qi, 30)				\
+  T (int8_t, vnx64qi, 32)				\
+  T (int8_t, vnx64qi, 63)				\
+  T (float, vnx32sf, 0)					\
+  T (float, vnx32sf, 3)					\
+  T (float, vnx32sf, 12)				\
+  T (float, vnx32sf, 17)				\
+  T (float, vnx32sf, 14)				\
+  T (double, vnx16df, 0)				\
+  T (double, vnx16df, 4)				\
+  T (double, vnx16df, 8)				\
+  T (double, vnx16df, 12)				\
+  T (int64_t, vnx16di, 0)				\
+  T (int64_t, vnx16di, 4)				\
+  T (int64_t, vnx16di, 8)				\
+  T (int64_t, vnx16di, 12)				\
+  T (int32_t, vnx32si, 0)				\
+  T (int32_t, vnx32si, 4)				\
+  T (int32_t, vnx32si, 12)				\
+  T (int32_t, vnx32si, 16)				\
+  T (int32_t, vnx32si, 28)				\
+  T (int16_t, vnx64hi, 0)				\
+  T (int16_t, vnx64hi, 4)				\
+  T (int16_t, vnx64hi, 28)				\
+  T (int16_t, vnx64hi, 32)				\
+  T (int16_t, vnx64hi, 60)				\
+  T (int8_t, vnx128qi, 0)				\
+  T (int8_t, vnx128qi, 4)				\
+  T (int8_t, vnx128qi, 30)				\
+  T (int8_t, vnx128qi, 60)				\
+  T (int8_t, vnx128qi, 64)				\
+  T (int8_t, vnx128qi, 127)				\
+
+CHECK_ALL (CHECK)
+
+#define RUN(S, V, IDX)						\
+  check_##V##_##IDX ();
+
+#define RUN_ALL(T)						\
+  T (float, vnx4sf, 0)					\
+  T (float, vnx4sf, 1)					\
+  T (float, vnx4sf, 3)					\
+  T (double, vnx2df, 0)					\
+  T (double, vnx2df, 1)					\
+  T (int64_t, vnx2di, 0)				\
+  T (int64_t, vnx2di, 1)				\
+  T (int32_t, vnx4si, 0)				\
+  T (int32_t, vnx4si, 1)				\
+  T (int32_t, vnx4si, 3)				\
+  T (int16_t, vnx8hi, 0)				\
+  T (int16_t, vnx8hi, 2)				\
+  T (int16_t, vnx8hi, 6)				\
+  T (int8_t, vnx16qi, 0)				\
+  T (int8_t, vnx16qi, 1)				\
+  T (int8_t, vnx16qi, 7)				\
+  T (int8_t, vnx16qi, 11)				\
+  T (int8_t, vnx16qi, 15)				\
+  T (float, vnx8sf, 0)					\
+  T (float, vnx8sf, 1)					\
+  T (float, vnx8sf, 3)					\
+  T (float, vnx8sf, 4)					\
+  T (float, vnx8sf, 7)					\
+  T (double, vnx4df, 0)					\
+  T (double, vnx4df, 1)					\
+  T (double, vnx4df, 2)					\
+  T (double, vnx4df, 3)					\
+  T (int64_t, vnx4di, 0)				\
+  T (int64_t, vnx4di, 1)				\
+  T (int64_t, vnx4di, 2)				\
+  T (int64_t, vnx4di, 3)				\
+  T (int32_t, vnx8si, 0)				\
+  T (int32_t, vnx8si, 1)				\
+  T (int32_t, vnx8si, 3)				\
+  T (int32_t, vnx8si, 4)				\
+  T (int32_t, vnx8si, 7)				\
+  T (int16_t, vnx16hi, 0)				\
+  T (int16_t, vnx16hi, 1)				\
+  T (int16_t, vnx16hi, 7)				\
+  T (int16_t, vnx16hi, 8)				\
+  T (int16_t, vnx16hi, 15)				\
+  T (int8_t, vnx32qi, 0)				\
+  T (int8_t, vnx32qi, 1)				\
+  T (int8_t, vnx32qi, 15)				\
+  T (int8_t, vnx32qi, 16)				\
+  T (int8_t, vnx32qi, 31)				\
+  T (float, vnx16sf, 0)					\
+  T (float, vnx16sf, 2)					\
+  T (float, vnx16sf, 6)					\
+  T (float, vnx16sf, 8)					\
+  T (float, vnx16sf, 14)				\
+  T (double, vnx8df, 0)					\
+  T (double, vnx8df, 2)					\
+  T (double, vnx8df, 4)					\
+  T (double, vnx8df, 6)					\
+  T (int64_t, vnx8di, 0)				\
+  T (int64_t, vnx8di, 2)				\
+  T (int64_t, vnx8di, 4)				\
+  T (int64_t, vnx8di, 6)				\
+  T (int32_t, vnx16si, 0)				\
+  T (int32_t, vnx16si, 2)				\
+  T (int32_t, vnx16si, 6)				\
+  T (int32_t, vnx16si, 8)				\
+  T (int32_t, vnx16si, 14)				\
+  T (int16_t, vnx32hi, 0)				\
+  T (int16_t, vnx32hi, 2)				\
+  T (int16_t, vnx32hi, 14)				\
+  T (int16_t, vnx32hi, 16)				\
+  T (int16_t, vnx32hi, 30)				\
+  T (int8_t, vnx64qi, 0)				\
+  T (int8_t, vnx64qi, 2)				\
+  T (int8_t, vnx64qi, 30)				\
+  T (int8_t, vnx64qi, 32)				\
+  T (int8_t, vnx64qi, 63)				\
+  T (float, vnx32sf, 0)					\
+  T (float, vnx32sf, 3)					\
+  T (float, vnx32sf, 12)				\
+  T (float, vnx32sf, 17)				\
+  T (float, vnx32sf, 14)				\
+  T (double, vnx16df, 0)				\
+  T (double, vnx16df, 4)				\
+  T (double, vnx16df, 8)				\
+  T (double, vnx16df, 12)				\
+  T (int64_t, vnx16di, 0)				\
+  T (int64_t, vnx16di, 4)				\
+  T (int64_t, vnx16di, 8)				\
+  T (int64_t, vnx16di, 12)				\
+  T (int32_t, vnx32si, 0)				\
+  T (int32_t, vnx32si, 4)				\
+  T (int32_t, vnx32si, 12)				\
+  T (int32_t, vnx32si, 16)				\
+  T (int32_t, vnx32si, 28)				\
+  T (int16_t, vnx64hi, 0)				\
+  T (int16_t, vnx64hi, 4)				\
+  T (int16_t, vnx64hi, 28)				\
+  T (int16_t, vnx64hi, 32)				\
+  T (int16_t, vnx64hi, 60)				\
+  T (int8_t, vnx128qi, 0)				\
+  T (int8_t, vnx128qi, 4)				\
+  T (int8_t, vnx128qi, 30)				\
+  T (int8_t, vnx128qi, 60)				\
+  T (int8_t, vnx128qi, 64)				\
+  T (int8_t, vnx128qi, 127)				\
+
+int main ()
+{
+  RUN_ALL (RUN);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c
new file mode 100644
index 0000000..db54acc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c
@@ -0,0 +1,77 @@
+/* { dg-do run {target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-Wno-pedantic" } */
+
+#include <assert.h>
+
+#include "vec_extract-1.c"
+#include "vec_extract-2.c"
+#include "vec_extract-3.c"
+#include "vec_extract-4.c"
+
+#define CHECK(S, V, IDX)				\
+void check_##V##_##IDX ()				\
+  {							\
+    V v;						\
+    for (int i = 0; i < sizeof (V) / sizeof (S); i++)	\
+      v[i] = i;						\
+    S res = vec_extract_##V##_##IDX (v);		\
+    assert (res == v[IDX]);				\
+  }
+
+#define CHECK_ALL(T)					\
+  T (_Float16, vnx8hf, 0)				\
+  T (_Float16, vnx8hf, 3)				\
+  T (_Float16, vnx8hf, 7)				\
+  T (_Float16, vnx16hf, 0)				\
+  T (_Float16, vnx16hf, 3)				\
+  T (_Float16, vnx16hf, 7)				\
+  T (_Float16, vnx16hf, 8)				\
+  T (_Float16, vnx16hf, 15)				\
+  T (_Float16, vnx32hf, 0)				\
+  T (_Float16, vnx32hf, 3)				\
+  T (_Float16, vnx32hf, 7)				\
+  T (_Float16, vnx32hf, 8)				\
+  T (_Float16, vnx32hf, 16)				\
+  T (_Float16, vnx32hf, 31)				\
+  T (_Float16, vnx64hf, 0)				\
+  T (_Float16, vnx64hf, 3)				\
+  T (_Float16, vnx64hf, 7)				\
+  T (_Float16, vnx64hf, 8)				\
+  T (_Float16, vnx64hf, 16)				\
+  T (_Float16, vnx64hf, 31)				\
+  T (_Float16, vnx64hf, 42)				\
+  T (_Float16, vnx64hf, 63)				\
+
+CHECK_ALL (CHECK)
+
+#define RUN(S, V, IDX)					\
+  check_##V##_##IDX ();
+
+#define RUN_ALL(T)					\
+  T (_Float16, vnx8hf, 0)				\
+  T (_Float16, vnx8hf, 3)				\
+  T (_Float16, vnx8hf, 7)				\
+  T (_Float16, vnx16hf, 0)				\
+  T (_Float16, vnx16hf, 3)				\
+  T (_Float16, vnx16hf, 7)				\
+  T (_Float16, vnx16hf, 8)				\
+  T (_Float16, vnx16hf, 15)				\
+  T (_Float16, vnx32hf, 0)				\
+  T (_Float16, vnx32hf, 3)				\
+  T (_Float16, vnx32hf, 7)				\
+  T (_Float16, vnx32hf, 8)				\
+  T (_Float16, vnx32hf, 16)				\
+  T (_Float16, vnx32hf, 31)				\
+  T (_Float16, vnx64hf, 0)				\
+  T (_Float16, vnx64hf, 3)				\
+  T (_Float16, vnx64hf, 7)				\
+  T (_Float16, vnx64hf, 8)				\
+  T (_Float16, vnx64hf, 16)				\
+  T (_Float16, vnx64hf, 31)				\
+  T (_Float16, vnx64hf, 42)				\
+  T (_Float16, vnx64hf, 63)				\
+
+int main ()
+{
+  RUN_ALL (RUN);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
new file mode 100644
index 0000000..3d60e63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx2di __attribute__((vector_size (16)));
+typedef int32_t vnx4si __attribute__((vector_size (16)));
+typedef int16_t vnx8hi __attribute__((vector_size (16)));
+typedef int8_t vnx16qi __attribute__((vector_size (16)));
+typedef _Float16 vnx8hf __attribute__((vector_size (16)));
+typedef float vnx4sf __attribute__((vector_size (16)));
+typedef double vnx2df __attribute__((vector_size (16)));
+
+#define VEC_SET(S,V,IDX)			\
+  V						\
+  __attribute__((noipa))			\
+  vec_set_##V##_##IDX (V v, S s)		\
+  {						\
+    v[IDX] = s;					\
+    return v;					\
+  }
+
+#define TEST_ALL1(T)				\
+  T (_Float16, vnx8hf, 0)			\
+  T (_Float16, vnx8hf, 3)			\
+  T (_Float16, vnx8hf, 7)			\
+  T (float, vnx4sf, 0)				\
+  T (float, vnx4sf, 1)				\
+  T (float, vnx4sf, 3)				\
+  T (double, vnx2df, 0)				\
+  T (double, vnx2df, 1)				\
+  T (int64_t, vnx2di, 0)			\
+  T (int64_t, vnx2di, 1)			\
+  T (int32_t, vnx4si, 0)			\
+  T (int32_t, vnx4si, 1)			\
+  T (int32_t, vnx4si, 3)			\
+  T (int16_t, vnx8hi, 0)			\
+  T (int16_t, vnx8hi, 2)			\
+  T (int16_t, vnx8hi, 6)			\
+  T (int8_t, vnx16qi, 0)			\
+  T (int8_t, vnx16qi, 1)			\
+  T (int8_t, vnx16qi, 7)			\
+  T (int8_t, vnx16qi, 11)			\
+  T (int8_t, vnx16qi, 15)			\
+
+TEST_ALL1 (VEC_SET)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*tu,\s*ma} 4 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*tu,\s*ma} 4 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*tu,\s*ma} 4 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*tu,\s*ma} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvmv.v.x} 9 } } */
+/* { dg-final { scan-assembler-times {\tvfmv.v.f} 5 } } */
+/* { dg-final { scan-assembler-times {\tvslideup.vi} 14 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.s.f} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmv.s.x} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
new file mode 100644
index 0000000..6929c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
@@ -0,0 +1,74 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx4di __attribute__((vector_size (32)));
+typedef int32_t vnx8si __attribute__((vector_size (32)));
+typedef int16_t vnx16hi __attribute__((vector_size (32)));
+typedef int8_t vnx32qi __attribute__((vector_size (32)));
+typedef _Float16 vnx16hf __attribute__((vector_size (32)));
+typedef float vnx8sf __attribute__((vector_size (32)));
+typedef double vnx4df __attribute__((vector_size (32)));
+
+#define VEC_SET(S,V,IDX)			\
+  V						\
+  __attribute__((noipa))			\
+  vec_set_##V##_##IDX (V v, S s)		\
+  {						\
+    v[IDX] = s;					\
+    return v;					\
+  }
+
+#define TEST_ALL2(T)				\
+  T (_Float16, vnx16hf, 0)			\
+  T (_Float16, vnx16hf, 3)			\
+  T (_Float16, vnx16hf, 7)			\
+  T (_Float16, vnx16hf, 8)			\
+  T (_Float16, vnx16hf, 15)			\
+  T (float, vnx8sf, 0)				\
+  T (float, vnx8sf, 1)				\
+  T (float, vnx8sf, 3)				\
+  T (float, vnx8sf, 4)				\
+  T (float, vnx8sf, 7)				\
+  T (double, vnx4df, 0)				\
+  T (double, vnx4df, 1)				\
+  T (double, vnx4df, 2)				\
+  T (double, vnx4df, 3)				\
+  T (int64_t, vnx4di, 0)			\
+  T (int64_t, vnx4di, 1)			\
+  T (int64_t, vnx4di, 2)			\
+  T (int64_t, vnx4di, 3)			\
+  T (int32_t, vnx8si, 0)			\
+  T (int32_t, vnx8si, 1)			\
+  T (int32_t, vnx8si, 3)			\
+  T (int32_t, vnx8si, 4)			\
+  T (int32_t, vnx8si, 7)			\
+  T (int16_t, vnx16hi, 0)			\
+  T (int16_t, vnx16hi, 1)			\
+  T (int16_t, vnx16hi, 7)			\
+  T (int16_t, vnx16hi, 8)			\
+  T (int16_t, vnx16hi, 15)			\
+  T (int8_t, vnx32qi, 0)			\
+  T (int8_t, vnx32qi, 1)			\
+  T (int8_t, vnx32qi, 15)			\
+  T (int8_t, vnx32qi, 16)			\
+  T (int8_t, vnx32qi, 31)			\
+
+TEST_ALL2 (VEC_SET)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m2,\s*tu,\s*ma} 4 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m2,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m2,\s*tu,\s*ma} 8 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m2,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m2,\s*tu,\s*ma} 8 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m2,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m2,\s*tu,\s*ma} 6 } } */
+
+/* { dg-final { scan-assembler-times {\tvmv.v.x} 15 } } */
+/* { dg-final { scan-assembler-times {\tvfmv.v.f} 11 } } */
+/* { dg-final { scan-assembler-times {\tvslideup.vi} 26 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.s.f} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmv.s.x} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
new file mode 100644
index 0000000..903deae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
@@ -0,0 +1,76 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx8di __attribute__((vector_size (64)));
+typedef int32_t vnx16si __attribute__((vector_size (64)));
+typedef int16_t vnx32hi __attribute__((vector_size (64)));
+typedef int8_t vnx64qi __attribute__((vector_size (64)));
+typedef _Float16 vnx32hf __attribute__((vector_size (64)));
+typedef float vnx16sf __attribute__((vector_size (64)));
+typedef double vnx8df __attribute__((vector_size (64)));
+
+#define VEC_SET(S,V,IDX)			\
+  V						\
+  __attribute__((noipa))			\
+  vec_set_##V##_##IDX (V v, S s)		\
+  {						\
+    v[IDX] = s;					\
+    return v;					\
+  }
+
+#define TEST_ALL3(T)				\
+  T (_Float16, vnx32hf, 0)			\
+  T (_Float16, vnx32hf, 3)			\
+  T (_Float16, vnx32hf, 7)			\
+  T (_Float16, vnx32hf, 8)			\
+  T (_Float16, vnx32hf, 16)			\
+  T (_Float16, vnx32hf, 31)			\
+  T (float, vnx16sf, 0)				\
+  T (float, vnx16sf, 2)				\
+  T (float, vnx16sf, 6)				\
+  T (float, vnx16sf, 8)				\
+  T (float, vnx16sf, 14)			\
+  T (double, vnx8df, 0)				\
+  T (double, vnx8df, 2)				\
+  T (double, vnx8df, 4)				\
+  T (double, vnx8df, 6)				\
+  T (int64_t, vnx8di, 0)			\
+  T (int64_t, vnx8di, 2)			\
+  T (int64_t, vnx8di, 4)			\
+  T (int64_t, vnx8di, 6)			\
+  T (int32_t, vnx16si, 0)			\
+  T (int32_t, vnx16si, 2)			\
+  T (int32_t, vnx16si, 6)			\
+  T (int32_t, vnx16si, 8)			\
+  T (int32_t, vnx16si, 14)			\
+  T (int16_t, vnx32hi, 0)			\
+  T (int16_t, vnx32hi, 2)			\
+  T (int16_t, vnx32hi, 14)			\
+  T (int16_t, vnx32hi, 16)			\
+  T (int16_t, vnx32hi, 30)			\
+  T (int8_t, vnx64qi, 0)			\
+  T (int8_t, vnx64qi, 2)			\
+  T (int8_t, vnx64qi, 30)			\
+  T (int8_t, vnx64qi, 32)			\
+  T (int8_t, vnx64qi, 63)			\
+
+TEST_ALL3 (VEC_SET)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m4,\s*tu,\s*ma} 4 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m4,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m4,\s*tu,\s*ma} 9 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m4,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m4,\s*tu,\s*ma} 8 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m4,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m4,\s*tu,\s*ma} 6 } } */
+
+/* { dg-final { scan-assembler-times {\tvmv.v.x} 15 } } */
+/* { dg-final { scan-assembler-times {\tvfmv.v.f} 12 } } */
+/* { dg-final { scan-assembler-times {\tvslideup.vi} 25 } } */
+/* { dg-final { scan-assembler-times {\tvslideup.vx} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.s.f} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmv.s.x} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
new file mode 100644
index 0000000..7d73399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx16di __attribute__((vector_size (128)));
+typedef int32_t vnx32si __attribute__((vector_size (128)));
+typedef int16_t vnx64hi __attribute__((vector_size (128)));
+typedef int8_t vnx128qi __attribute__((vector_size (128)));
+typedef _Float16 vnx64hf __attribute__((vector_size (128)));
+typedef float vnx32sf __attribute__((vector_size (128)));
+typedef double vnx16df __attribute__((vector_size (128)));
+
+#define VEC_SET(S,V,IDX)			\
+  V						\
+  __attribute__((noipa))			\
+  vec_set_##V##_##IDX (V v, S s)		\
+  {						\
+    v[IDX] = s;					\
+    return v;					\
+  }
+
+#define TEST_ALL4(T)				\
+  T (_Float16, vnx64hf, 0)			\
+  T (_Float16, vnx64hf, 3)			\
+  T (_Float16, vnx64hf, 7)			\
+  T (_Float16, vnx64hf, 8)			\
+  T (_Float16, vnx64hf, 16)			\
+  T (_Float16, vnx64hf, 31)			\
+  T (_Float16, vnx64hf, 42)			\
+  T (_Float16, vnx64hf, 63)			\
+  T (float, vnx32sf, 0)				\
+  T (float, vnx32sf, 3)				\
+  T (float, vnx32sf, 12)			\
+  T (float, vnx32sf, 17)			\
+  T (float, vnx32sf, 14)			\
+  T (double, vnx16df, 0)			\
+  T (double, vnx16df, 4)			\
+  T (double, vnx16df, 8)			\
+  T (double, vnx16df, 12)			\
+  T (int64_t, vnx16di, 0)			\
+  T (int64_t, vnx16di, 4)			\
+  T (int64_t, vnx16di, 8)			\
+  T (int64_t, vnx16di, 12)			\
+  T (int32_t, vnx32si, 0)			\
+  T (int32_t, vnx32si, 4)			\
+  T (int32_t, vnx32si, 12)			\
+  T (int32_t, vnx32si, 16)			\
+  T (int32_t, vnx32si, 28)			\
+  T (int16_t, vnx64hi, 0)			\
+  T (int16_t, vnx64hi, 4)			\
+  T (int16_t, vnx64hi, 28)			\
+  T (int16_t, vnx64hi, 32)			\
+  T (int16_t, vnx64hi, 60)			\
+  T (int8_t, vnx128qi, 0)			\
+  T (int8_t, vnx128qi, 4)			\
+  T (int8_t, vnx128qi, 30)			\
+  T (int8_t, vnx128qi, 60)			\
+  T (int8_t, vnx128qi, 64)			\
+  T (int8_t, vnx128qi, 127)			\
+
+TEST_ALL4 (VEC_SET)
+
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m8,\s*ta,\s*ma} 1 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m8,\s*tu,\s*ma} 5 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m8,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m8,\s*tu,\s*ma} 11 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m8,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m8,\s*tu,\s*ma} 8 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m8,\s*ta,\s*ma} 2 } } */
+/* { dg-final { scan-assembler-times {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m8,\s*tu,\s*ma} 6 } } */
+
+/* { dg-final { scan-assembler-times {\tvmv.v.x} 16 } } */
+/* { dg-final { scan-assembler-times {\tvfmv.v.f} 14 } } */
+/* { dg-final { scan-assembler-times {\tvslideup.vi} 23 } } */
+/* { dg-final { scan-assembler-times {\tvslideup.vx} 7 } } */
+
+/* { dg-final { scan-assembler-times {\tvfmv.s.f} 3 } } */
+/* { dg-final { scan-assembler-times {\tvmv.s.x} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
new file mode 100644
index 0000000..6a08f26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
@@ -0,0 +1,240 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
+
+#include <assert.h>
+
+#include "vec_set-1.c"
+#include "vec_set-2.c"
+#include "vec_set-3.c"
+#include "vec_set-4.c"
+
+#define CHECK(S, V, IDX)				\
+void check_##V##_##IDX ()				\
+  {							\
+    V v;						\
+    for (int i = 0; i < sizeof (V) / sizeof (S); i++)	\
+      v[i] = i;						\
+    V res = vec_set_##V##_##IDX (v, 77);		\
+    for (int i = 0; i < sizeof (V) / sizeof (S); i++)	\
+      assert (res[i] == (i == IDX ? 77 : i));		\
+  }
+
+#define CHECK_ALL(T)					\
+  T (float, vnx4sf, 0)					\
+  T (float, vnx4sf, 1)					\
+  T (float, vnx4sf, 3)					\
+  T (double, vnx2df, 0)					\
+  T (double, vnx2df, 1)					\
+  T (int64_t, vnx2di, 0)				\
+  T (int64_t, vnx2di, 1)				\
+  T (int32_t, vnx4si, 0)				\
+  T (int32_t, vnx4si, 1)				\
+  T (int32_t, vnx4si, 3)				\
+  T (int16_t, vnx8hi, 0)				\
+  T (int16_t, vnx8hi, 2)				\
+  T (int16_t, vnx8hi, 6)				\
+  T (int8_t, vnx16qi, 0)				\
+  T (int8_t, vnx16qi, 1)				\
+  T (int8_t, vnx16qi, 7)				\
+  T (int8_t, vnx16qi, 11)				\
+  T (int8_t, vnx16qi, 15)				\
+  T (float, vnx8sf, 0)					\
+  T (float, vnx8sf, 1)					\
+  T (float, vnx8sf, 3)					\
+  T (float, vnx8sf, 4)					\
+  T (float, vnx8sf, 7)					\
+  T (double, vnx4df, 0)					\
+  T (double, vnx4df, 1)					\
+  T (double, vnx4df, 2)					\
+  T (double, vnx4df, 3)					\
+  T (int64_t, vnx4di, 0)				\
+  T (int64_t, vnx4di, 1)				\
+  T (int64_t, vnx4di, 2)				\
+  T (int64_t, vnx4di, 3)				\
+  T (int32_t, vnx8si, 0)				\
+  T (int32_t, vnx8si, 1)				\
+  T (int32_t, vnx8si, 3)				\
+  T (int32_t, vnx8si, 4)				\
+  T (int32_t, vnx8si, 7)				\
+  T (int16_t, vnx16hi, 0)				\
+  T (int16_t, vnx16hi, 1)				\
+  T (int16_t, vnx16hi, 7)				\
+  T (int16_t, vnx16hi, 8)				\
+  T (int16_t, vnx16hi, 15)				\
+  T (int8_t, vnx32qi, 0)				\
+  T (int8_t, vnx32qi, 1)				\
+  T (int8_t, vnx32qi, 15)				\
+  T (int8_t, vnx32qi, 16)				\
+  T (int8_t, vnx32qi, 31)				\
+  T (float, vnx16sf, 0)					\
+  T (float, vnx16sf, 2)					\
+  T (float, vnx16sf, 6)					\
+  T (float, vnx16sf, 8)					\
+  T (float, vnx16sf, 14)				\
+  T (double, vnx8df, 0)					\
+  T (double, vnx8df, 2)					\
+  T (double, vnx8df, 4)					\
+  T (double, vnx8df, 6)					\
+  T (int64_t, vnx8di, 0)				\
+  T (int64_t, vnx8di, 2)				\
+  T (int64_t, vnx8di, 4)				\
+  T (int64_t, vnx8di, 6)				\
+  T (int32_t, vnx16si, 0)				\
+  T (int32_t, vnx16si, 2)				\
+  T (int32_t, vnx16si, 6)				\
+  T (int32_t, vnx16si, 8)				\
+  T (int32_t, vnx16si, 14)				\
+  T (int16_t, vnx32hi, 0)				\
+  T (int16_t, vnx32hi, 2)				\
+  T (int16_t, vnx32hi, 14)				\
+  T (int16_t, vnx32hi, 16)				\
+  T (int16_t, vnx32hi, 30)				\
+  T (int8_t, vnx64qi, 0)				\
+  T (int8_t, vnx64qi, 2)				\
+  T (int8_t, vnx64qi, 30)				\
+  T (int8_t, vnx64qi, 32)				\
+  T (int8_t, vnx64qi, 63)				\
+  T (float, vnx32sf, 0)					\
+  T (float, vnx32sf, 3)					\
+  T (float, vnx32sf, 12)				\
+  T (float, vnx32sf, 17)				\
+  T (float, vnx32sf, 14)				\
+  T (double, vnx16df, 0)				\
+  T (double, vnx16df, 4)				\
+  T (double, vnx16df, 8)				\
+  T (double, vnx16df, 12)				\
+  T (int64_t, vnx16di, 0)				\
+  T (int64_t, vnx16di, 4)				\
+  T (int64_t, vnx16di, 8)				\
+  T (int64_t, vnx16di, 12)				\
+  T (int32_t, vnx32si, 0)				\
+  T (int32_t, vnx32si, 4)				\
+  T (int32_t, vnx32si, 12)				\
+  T (int32_t, vnx32si, 16)				\
+  T (int32_t, vnx32si, 28)				\
+  T (int16_t, vnx64hi, 0)				\
+  T (int16_t, vnx64hi, 4)				\
+  T (int16_t, vnx64hi, 28)				\
+  T (int16_t, vnx64hi, 32)				\
+  T (int16_t, vnx64hi, 60)				\
+  T (int8_t, vnx128qi, 0)				\
+  T (int8_t, vnx128qi, 4)				\
+  T (int8_t, vnx128qi, 30)				\
+  T (int8_t, vnx128qi, 60)				\
+  T (int8_t, vnx128qi, 64)				\
+  T (int8_t, vnx128qi, 127)				\
+
+CHECK_ALL (CHECK)
+
+#define RUN(S, V, IDX)					\
+  check_##V##_##IDX ();
+
+#define RUN_ALL(T)					\
+  T (float, vnx4sf, 0)					\
+  T (float, vnx4sf, 1)					\
+  T (float, vnx4sf, 3)					\
+  T (double, vnx2df, 0)					\
+  T (double, vnx2df, 1)					\
+  T (int64_t, vnx2di, 0)				\
+  T (int64_t, vnx2di, 1)				\
+  T (int32_t, vnx4si, 0)				\
+  T (int32_t, vnx4si, 1)				\
+  T (int32_t, vnx4si, 3)				\
+  T (int16_t, vnx8hi, 0)				\
+  T (int16_t, vnx8hi, 2)				\
+  T (int16_t, vnx8hi, 6)				\
+  T (int8_t, vnx16qi, 0)				\
+  T (int8_t, vnx16qi, 1)				\
+  T (int8_t, vnx16qi, 7)				\
+  T (int8_t, vnx16qi, 11)				\
+  T (int8_t, vnx16qi, 15)				\
+  T (float, vnx8sf, 0)					\
+  T (float, vnx8sf, 1)					\
+  T (float, vnx8sf, 3)					\
+  T (float, vnx8sf, 4)					\
+  T (float, vnx8sf, 7)					\
+  T (double, vnx4df, 0)					\
+  T (double, vnx4df, 1)					\
+  T (double, vnx4df, 2)					\
+  T (double, vnx4df, 3)					\
+  T (int64_t, vnx4di, 0)				\
+  T (int64_t, vnx4di, 1)				\
+  T (int64_t, vnx4di, 2)				\
+  T (int64_t, vnx4di, 3)				\
+  T (int32_t, vnx8si, 0)				\
+  T (int32_t, vnx8si, 1)				\
+  T (int32_t, vnx8si, 3)				\
+  T (int32_t, vnx8si, 4)				\
+  T (int32_t, vnx8si, 7)				\
+  T (int16_t, vnx16hi, 0)				\
+  T (int16_t, vnx16hi, 1)				\
+  T (int16_t, vnx16hi, 7)				\
+  T (int16_t, vnx16hi, 8)				\
+  T (int16_t, vnx16hi, 15)				\
+  T (int8_t, vnx32qi, 0)				\
+  T (int8_t, vnx32qi, 1)				\
+  T (int8_t, vnx32qi, 15)				\
+  T (int8_t, vnx32qi, 16)				\
+  T (int8_t, vnx32qi, 31)				\
+  T (float, vnx16sf, 0)					\
+  T (float, vnx16sf, 2)					\
+  T (float, vnx16sf, 6)					\
+  T (float, vnx16sf, 8)					\
+  T (float, vnx16sf, 14)				\
+  T (double, vnx8df, 0)					\
+  T (double, vnx8df, 2)					\
+  T (double, vnx8df, 4)					\
+  T (double, vnx8df, 6)					\
+  T (int64_t, vnx8di, 0)				\
+  T (int64_t, vnx8di, 2)				\
+  T (int64_t, vnx8di, 4)				\
+  T (int64_t, vnx8di, 6)				\
+  T (int32_t, vnx16si, 0)				\
+  T (int32_t, vnx16si, 2)				\
+  T (int32_t, vnx16si, 6)				\
+  T (int32_t, vnx16si, 8)				\
+  T (int32_t, vnx16si, 14)				\
+  T (int16_t, vnx32hi, 0)				\
+  T (int16_t, vnx32hi, 2)				\
+  T (int16_t, vnx32hi, 14)				\
+  T (int16_t, vnx32hi, 16)				\
+  T (int16_t, vnx32hi, 30)				\
+  T (int8_t, vnx64qi, 0)				\
+  T (int8_t, vnx64qi, 2)				\
+  T (int8_t, vnx64qi, 30)				\
+  T (int8_t, vnx64qi, 32)				\
+  T (int8_t, vnx64qi, 63)				\
+  T (float, vnx32sf, 0)					\
+  T (float, vnx32sf, 3)					\
+  T (float, vnx32sf, 12)				\
+  T (float, vnx32sf, 17)				\
+  T (float, vnx32sf, 14)				\
+  T (double, vnx16df, 0)				\
+  T (double, vnx16df, 4)				\
+  T (double, vnx16df, 8)				\
+  T (double, vnx16df, 12)				\
+  T (int64_t, vnx16di, 0)				\
+  T (int64_t, vnx16di, 4)				\
+  T (int64_t, vnx16di, 8)				\
+  T (int64_t, vnx16di, 12)				\
+  T (int32_t, vnx32si, 0)				\
+  T (int32_t, vnx32si, 4)				\
+  T (int32_t, vnx32si, 12)				\
+  T (int32_t, vnx32si, 16)				\
+  T (int32_t, vnx32si, 28)				\
+  T (int16_t, vnx64hi, 0)				\
+  T (int16_t, vnx64hi, 4)				\
+  T (int16_t, vnx64hi, 28)				\
+  T (int16_t, vnx64hi, 32)				\
+  T (int16_t, vnx64hi, 60)				\
+  T (int8_t, vnx128qi, 0)				\
+  T (int8_t, vnx128qi, 4)				\
+  T (int8_t, vnx128qi, 30)				\
+  T (int8_t, vnx128qi, 60)				\
+  T (int8_t, vnx128qi, 64)				\
+  T (int8_t, vnx128qi, 127)				\
+
+int main ()
+{
+  RUN_ALL (RUN);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c
new file mode 100644
index 0000000..df8363e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c
@@ -0,0 +1,78 @@
+/* { dg-do run { target { riscv_zvfh_hw } } } */
+/* { dg-additional-options "-Wno-pedantic" } */
+
+#include <assert.h>
+
+#include "vec_set-1.c"
+#include "vec_set-2.c"
+#include "vec_set-3.c"
+#include "vec_set-4.c"
+
+#define CHECK(S, V, IDX)				\
+void check_##V##_##IDX ()				\
+  {							\
+    V v;						\
+    for (int i = 0; i < sizeof (V) / sizeof (S); i++)	\
+      v[i] = i;						\
+    V res = vec_set_##V##_##IDX (v, 77);		\
+    for (int i = 0; i < sizeof (V) / sizeof (S); i++)	\
+      assert (res[i] == (i == IDX ? 77 : i));		\
+  }
+
+#define CHECK_ALL(T)					\
+  T (_Float16, vnx8hf, 0)				\
+  T (_Float16, vnx8hf, 3)				\
+  T (_Float16, vnx8hf, 7)				\
+  T (_Float16, vnx16hf, 0)				\
+  T (_Float16, vnx16hf, 3)				\
+  T (_Float16, vnx16hf, 7)				\
+  T (_Float16, vnx16hf, 8)				\
+  T (_Float16, vnx16hf, 15)				\
+  T (_Float16, vnx32hf, 0)				\
+  T (_Float16, vnx32hf, 3)				\
+  T (_Float16, vnx32hf, 7)				\
+  T (_Float16, vnx32hf, 8)				\
+  T (_Float16, vnx32hf, 16)				\
+  T (_Float16, vnx32hf, 31)				\
+  T (_Float16, vnx64hf, 0)				\
+  T (_Float16, vnx64hf, 3)				\
+  T (_Float16, vnx64hf, 7)				\
+  T (_Float16, vnx64hf, 8)				\
+  T (_Float16, vnx64hf, 16)				\
+  T (_Float16, vnx64hf, 31)				\
+  T (_Float16, vnx64hf, 42)				\
+  T (_Float16, vnx64hf, 63)				\
+
+CHECK_ALL (CHECK)
+
+#define RUN(S, V, IDX)					\
+  check_##V##_##IDX ();
+
+#define RUN_ALL(T)					\
+  T (_Float16, vnx8hf, 0)				\
+  T (_Float16, vnx8hf, 3)				\
+  T (_Float16, vnx8hf, 7)				\
+  T (_Float16, vnx16hf, 0)				\
+  T (_Float16, vnx16hf, 3)				\
+  T (_Float16, vnx16hf, 7)				\
+  T (_Float16, vnx16hf, 8)				\
+  T (_Float16, vnx16hf, 15)				\
+  T (_Float16, vnx32hf, 0)				\
+  T (_Float16, vnx32hf, 3)				\
+  T (_Float16, vnx32hf, 7)				\
+  T (_Float16, vnx32hf, 8)				\
+  T (_Float16, vnx32hf, 16)				\
+  T (_Float16, vnx32hf, 31)				\
+  T (_Float16, vnx64hf, 0)				\
+  T (_Float16, vnx64hf, 3)				\
+  T (_Float16, vnx64hf, 7)				\
+  T (_Float16, vnx64hf, 8)				\
+  T (_Float16, vnx64hf, 16)				\
+  T (_Float16, vnx64hf, 31)				\
+  T (_Float16, vnx64hf, 42)				\
+  T (_Float16, vnx64hf, 63)				\
+
+int main ()
+{
+  RUN_ALL (RUN);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
new file mode 100644
index 0000000..534d5fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include "riscv_vector.h"
+
+void test_vreinterpret_v_b64_i8m1 (uint8_t *in, int8_t *out)
+{
+  vbool64_t vmask = __riscv_vlm_v_b64 (in, 2);
+  vint8m1_t vout = __riscv_vreinterpret_v_b64_i8m1 (vmask);
+  __riscv_vse8_v_i8m1(out, vout, 16);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c
index 08da48d..109fcbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c
@@ -31,5 +31,19 @@ void f4 (_Float16 * __restrict a, _Float16 * __restrict b, int n)
     a[i] = a[i]/b[i];
 }
 
-/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization when -march="*zvfhmin*".  */
+void f6 (_Float16 * __restrict a, _Float16 * __restrict b, int n)
+{
+  for (int i = 0; i < n; i++)
+    a[i] = __builtin_fabs (b[i]);
+}
+
+void f7 (_Float16 * __restrict a, _Float16 * __restrict b, int n)
+{
+  for (int i = 0; i < n; i++)
+    a[i] = __builtin_sqrtf (b[i]);
+}
+
+/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV/ABS/SQRTF auto-vectorization
+   when -march="*zvfhmin*" because the min variant of the extension only
+   provides loads, stores and conversions.  */
 /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 0 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
index f16502b..c5d9b15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
index b233ff1..958d1ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gczve32x --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */
 
 #include <stdint.h>
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c
new file mode 100644
index 0000000..2e4aeb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32f -O3 -Wno-psabi" } */
+
+#include "pr110265-1.h"
+
+/* { dg-final { scan-assembler-times {vredand\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredmax\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredmaxu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredmin\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredminu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredor\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredsum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vredxor\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.h
new file mode 100644
index 0000000..ade44cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-1.h
@@ -0,0 +1,65 @@
+#include "riscv_vector.h"
+
+vint8m1_t test_vredand_vs_i8mf4_i8m1(vint8mf4_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredand_vs_i8mf4_i8m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vredand_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vredand_vs_u32m8_u32m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredmax_vs_i8mf4_i8m1(vint8mf4_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredmax_vs_i8mf4_i8m1(vector, scalar, vl);
+}
+
+vint32m1_t test_vredmax_vs_i32m8_i32m1(vint32m8_t vector, vint32m1_t scalar, size_t vl) {
+  return __riscv_vredmax_vs_i32m8_i32m1(vector, scalar, vl);
+}
+
+vuint8m1_t test_vredmaxu_vs_u8mf4_u8m1(vuint8mf4_t vector, vuint8m1_t scalar, size_t vl) {
+  return __riscv_vredmaxu_vs_u8mf4_u8m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vredmaxu_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vredmaxu_vs_u32m8_u32m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredmin_vs_i8mf4_i8m1(vint8mf4_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredmin_vs_i8mf4_i8m1(vector, scalar, vl);
+}
+
+vint32m1_t test_vredmin_vs_i32m8_i32m1(vint32m8_t vector, vint32m1_t scalar, size_t vl) {
+  return __riscv_vredmin_vs_i32m8_i32m1(vector, scalar, vl);
+}
+
+vuint8m1_t test_vredminu_vs_u8mf4_u8m1(vuint8mf4_t vector, vuint8m1_t scalar, size_t vl) {
+  return __riscv_vredminu_vs_u8mf4_u8m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vredminu_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vredminu_vs_u32m8_u32m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredor_vs_i8mf4_i8m1(vint8mf4_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredor_vs_i8mf4_i8m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vredor_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vredor_vs_u32m8_u32m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredsum_vs_i8mf4_i8m1(vint8mf4_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredsum_vs_i8mf4_i8m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vredsum_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vredsum_vs_u32m8_u32m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredxor_vs_i8mf4_i8m1(vint8mf4_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredxor_vs_i8mf4_i8m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vredxor_vs_u32m8_u32m1(vuint32m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vredxor_vs_u32m8_u32m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c
new file mode 100644
index 0000000..7454c1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi" } */
+
+#include "pr110265-1.h"
+#include "pr110265-2.h"
+
+/* { dg-final { scan-assembler-times {vredand\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredmax\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vredmaxu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredmin\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vredminu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredor\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredsum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredxor\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.h
new file mode 100644
index 0000000..6a7e14e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-2.h
@@ -0,0 +1,57 @@
+#include "riscv_vector.h"
+
+vint8m1_t test_vredand_vs_i8mf8_i8m1(vint8mf8_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredand_vs_i8mf8_i8m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredmax_vs_i8mf8_i8m1(vint8mf8_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredmax_vs_i8mf8_i8m1(vector, scalar, vl);
+}
+
+vuint8m1_t test_vredmaxu_vs_u8mf8_u8m1(vuint8mf8_t vector, vuint8m1_t scalar, size_t vl) {
+  return __riscv_vredmaxu_vs_u8mf8_u8m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredmin_vs_i8mf8_i8m1(vint8mf8_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredmin_vs_i8mf8_i8m1(vector, scalar, vl);
+}
+
+vuint8m1_t test_vredminu_vs_u8mf8_u8m1(vuint8mf8_t vector, vuint8m1_t scalar, size_t vl) {
+  return __riscv_vredminu_vs_u8mf8_u8m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredor_vs_i8mf8_i8m1(vint8mf8_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredor_vs_i8mf8_i8m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredsum_vs_i8mf8_i8m1(vint8mf8_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredsum_vs_i8mf8_i8m1(vector, scalar, vl);
+}
+
+vint8m1_t test_vredxor_vs_i8mf8_i8m1(vint8mf8_t vector, vint8m1_t scalar, size_t vl) {
+  return __riscv_vredxor_vs_i8mf8_i8m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vredand_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vredand_vs_u64m8_u64m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vredmaxu_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vredmaxu_vs_u64m8_u64m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vredminu_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vredminu_vs_u64m8_u64m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vredor_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vredor_vs_u64m8_u64m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vredsum_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vredsum_vs_u64m8_u64m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vredxor_vs_u64m8_u64m1(vuint64m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vredxor_vs_u64m8_u64m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c
new file mode 100644
index 0000000..0ed1fba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110265-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32f -O3 -Wno-psabi" } */
+
+#include "pr110265-1.h"
+#include "pr110265-2.h"
+
+/* { dg-final { scan-assembler-times {vredand\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredmax\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vredmaxu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredmin\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {vredminu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredor\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredsum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vredxor\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c
new file mode 100644
index 0000000..24a4ba3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3 -Wno-psabi" } */
+
+#include "pr110277-1.h"
+
+/* { dg-final { scan-assembler-times {vfredmax\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfredmin\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.h
new file mode 100644
index 0000000..67c296c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-1.h
@@ -0,0 +1,33 @@
+#include "riscv_vector.h"
+
+vfloat16m1_t test_vfredmax_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredmax_vs_f16mf2_f16m1(vector, scalar, vl);
+}
+
+vfloat32m1_t test_vfredmax_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfredmax_vs_f32m8_f32m1(vector, scalar, vl);
+}
+
+vfloat16m1_t test_vfredmin_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredmin_vs_f16mf2_f16m1(vector, scalar, vl);
+}
+
+vfloat32m1_t test_vfredmin_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfredmin_vs_f32m8_f32m1(vector, scalar, vl);
+}
+
+vfloat16m1_t test_vfredosum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredosum_vs_f16mf2_f16m1(vector, scalar, vl);
+}
+
+vfloat32m1_t test_vfredosum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfredosum_vs_f32m8_f32m1(vector, scalar, vl);
+}
+
+vfloat16m1_t test_vfredusum_vs_f16mf2_f16m1(vfloat16mf2_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredusum_vs_f16mf2_f16m1(vector, scalar, vl);
+}
+
+vfloat32m1_t test_vfredusum_vs_f32m8_f32m1(vfloat32m8_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfredusum_vs_f32m8_f32m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c
new file mode 100644
index 0000000..23d7361
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3 -Wno-psabi" } */
+
+#include "pr110277-1.h"
+#include "pr110277-2.h"
+
+/* { dg-final { scan-assembler-times {vfredmax\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vfredmin\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vfredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.h
new file mode 100644
index 0000000..7e5c81a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110277-2.h
@@ -0,0 +1,33 @@
+#include "riscv_vector.h"
+
+vfloat16m1_t test_vfredmax_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredmax_vs_f16mf4_f16m1(vector, scalar, vl);
+}
+
+vfloat16m1_t test_vfredmin_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredmin_vs_f16mf4_f16m1(vector, scalar, vl);
+}
+
+vfloat16m1_t test_vfredosum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredosum_vs_f16mf4_f16m1(vector, scalar, vl);
+}
+
+vfloat16m1_t test_vfredusum_vs_f16mf4_f16m1(vfloat16mf4_t vector, vfloat16m1_t scalar, size_t vl) {
+  return __riscv_vfredusum_vs_f16mf4_f16m1(vector, scalar, vl);
+}
+
+vfloat64m1_t test_vfredmax_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+  return __riscv_vfredmax_vs_f64m8_f64m1(vector, scalar, vl);
+}
+
+vfloat64m1_t test_vfredmin_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+  return __riscv_vfredmin_vs_f64m8_f64m1(vector, scalar, vl);
+}
+
+vfloat64m1_t test_vfredosum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+  return __riscv_vfredosum_vs_f64m8_f64m1(vector, scalar, vl);
+}
+
+vfloat64m1_t test_vfredusum_vs_f64m8_f64m1(vfloat64m8_t vector, vfloat64m1_t scalar, size_t vl) {
+  return __riscv_vfredusum_vs_f64m8_f64m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
new file mode 100644
index 0000000..d83eea9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3 -Wno-psabi" } */
+
+#include "pr110299-1.h"
+
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h
new file mode 100644
index 0000000..a8ea018
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h
@@ -0,0 +1,9 @@
+#include "riscv_vector.h"
+
+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfwredosum_vs_f16m8_f32m1(vector, scalar, vl);
+}
+
+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfwredusum_vs_f16m8_f32m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
new file mode 100644
index 0000000..cdcde1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3 -Wno-psabi" } */
+
+#include "pr110299-1.h"
+#include "pr110299-2.h"
+
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h
new file mode 100644
index 0000000..51d4d44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h
@@ -0,0 +1,17 @@
+#include "riscv_vector.h"
+
+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfwredosum_vs_f16mf4_f32m1(vector, scalar, vl);
+}
+
+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
+  return __riscv_vfwredusum_vs_f16mf4_f32m1(vector, scalar, vl);
+}
+
+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+  return __riscv_vfwredusum_vs_f32m8_f64m1(vector, scalar, vl);
+}
+
+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {
+  return __riscv_vfwredosum_vs_f32m8_f64m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
new file mode 100644
index 0000000..0f84c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32f -O3 -Wno-psabi" } */
+
+#include "pr110299-3.h"
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h
new file mode 100644
index 0000000..3416196b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h
@@ -0,0 +1,17 @@
+#include "riscv_vector.h"
+
+vint16m1_t test_vwredsum_vs_i8mf4_i16m1(vint8mf4_t vector, vint16m1_t scalar, size_t vl) {
+  return __riscv_vwredsum_vs_i8mf4_i16m1(vector, scalar, vl);
+}
+
+vint32m1_t test_vwredsum_vs_i16m8_i32m1(vint16m8_t vector, vint32m1_t scalar, size_t vl) {
+  return __riscv_vwredsum_vs_i16m8_i32m1(vector, scalar, vl);
+}
+
+vuint16m1_t test_vwredsumu_vs_u8mf4_u16m1(vuint8mf4_t vector, vuint16m1_t scalar, size_t vl) {
+  return __riscv_vwredsumu_vs_u8mf4_u16m1(vector, scalar, vl);
+}
+
+vuint32m1_t test_vwredsumu_vs_u16m8_u32m1(vuint16m8_t vector, vuint32m1_t scalar, size_t vl) {
+  return __riscv_vwredsumu_vs_u16m8_u32m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
new file mode 100644
index 0000000..8297cd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi" } */
+
+#include "pr110299-3.h"
+#include "pr110299-4.h"
+
+/* { dg-final { scan-assembler-times {vwredsum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {vwredsumu\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h
new file mode 100644
index 0000000..b4f7d40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h
@@ -0,0 +1,17 @@
+#include "riscv_vector.h"
+
+vint16m1_t test_vwredsum_vs_i8mf8_i16m1(vint8mf8_t vector, vint16m1_t scalar, size_t vl) {
+  return __riscv_vwredsum_vs_i8mf8_i16m1(vector, scalar, vl);
+}
+
+vint64m1_t test_vwredsum_vs_i32m8_i64m1(vint32m8_t vector, vint64m1_t scalar, size_t vl) {
+  return __riscv_vwredsum_vs_i32m8_i64m1(vector, scalar, vl);
+}
+
+vuint16m1_t test_vwredsumu_vs_u8mf8_u16m1(vuint8mf8_t vector, vuint16m1_t scalar, size_t vl) {
+  return __riscv_vwredsumu_vs_u8mf8_u16m1(vector, scalar, vl);
+}
+
+vuint64m1_t test_vwredsumu_vs_u32m8_u64m1(vuint32m8_t vector, vuint64m1_t scalar, size_t vl) {
+  return __riscv_vwredsumu_vs_u32m8_u64m1(vector, scalar, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c
new file mode 100644
index 0000000..f36129e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-28.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */
+
+#include "riscv_vector.h"
+
+void
+f_vfloat16mf4x2_t (void *base, void *out)
+{
+  vfloat16mf4x2_t v = *(vfloat16mf4x2_t*)base;
+  *(vfloat16mf4x2_t*)out = v;
+}
+
+void
+f_vfloat16mf4x3_t (void *base, void *out)
+{
+  vfloat16mf4x3_t v = *(vfloat16mf4x3_t*)base;
+  *(vfloat16mf4x3_t*)out = v;
+}
+
+void
+f_vfloat16mf4x4_t (void *base, void *out)
+{
+  vfloat16mf4x4_t v = *(vfloat16mf4x4_t*)base;
+  *(vfloat16mf4x4_t*)out = v;
+}
+
+void
+f_vfloat16mf4x5_t (void *base, void *out)
+{
+  vfloat16mf4x5_t v = *(vfloat16mf4x5_t*)base;
+  *(vfloat16mf4x5_t*)out = v;
+}
+
+void
+f_vfloat16mf4x6_t (void *base, void *out)
+{
+  vfloat16mf4x6_t v = *(vfloat16mf4x6_t*)base;
+  *(vfloat16mf4x6_t*)out = v;
+}
+
+void
+f_vfloat16mf4x7_t (void *base, void *out)
+{
+  vfloat16mf4x7_t v = *(vfloat16mf4x7_t*)base;
+  *(vfloat16mf4x7_t*)out = v;
+}
+
+void
+f_vfloat16mf4x8_t (void *base, void *out)
+{
+  vfloat16mf4x8_t v = *(vfloat16mf4x8_t*)base;
+  *(vfloat16mf4x8_t*)out = v;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */
+/* { dg-final { scan-assembler {srai} } } */
+/* { dg-final { scan-assembler-not {slli} } } */
+/* { dg-final { scan-assembler-times {vle16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
+/* { dg-final { scan-assembler-times {vse16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c
new file mode 100644
index 0000000..c6807c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-29.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */
+
+#include "riscv_vector.h"
+
+void
+f_vfloat16mf2x2_t (void *base, void *out)
+{
+  vfloat16mf2x2_t v = *(vfloat16mf2x2_t*)base;
+  *(vfloat16mf2x2_t*)out = v;
+}
+
+void
+f_vfloat16mf2x3_t (void *base, void *out)
+{
+  vfloat16mf2x3_t v = *(vfloat16mf2x3_t*)base;
+  *(vfloat16mf2x3_t*)out = v;
+}
+
+void
+f_vfloat16mf2x4_t (void *base, void *out)
+{
+  vfloat16mf2x4_t v = *(vfloat16mf2x4_t*)base;
+  *(vfloat16mf2x4_t*)out = v;
+}
+
+void
+f_vfloat16mf2x5_t (void *base, void *out)
+{
+  vfloat16mf2x5_t v = *(vfloat16mf2x5_t*)base;
+  *(vfloat16mf2x5_t*)out = v;
+}
+
+void
+f_vfloat16mf2x6_t (void *base, void *out)
+{
+  vfloat16mf2x6_t v = *(vfloat16mf2x6_t*)base;
+  *(vfloat16mf2x6_t*)out = v;
+}
+
+void
+f_vfloat16mf2x7_t (void *base, void *out)
+{
+  vfloat16mf2x7_t v = *(vfloat16mf2x7_t*)base;
+  *(vfloat16mf2x7_t*)out = v;
+}
+
+void
+f_vfloat16mf2x8_t (void *base, void *out)
+{
+  vfloat16mf2x8_t v = *(vfloat16mf2x8_t*)base;
+  *(vfloat16mf2x8_t*)out = v;
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 7 } } */
+/* { dg-final { scan-assembler {srai} } } */
+/* { dg-final { scan-assembler-not {slli} } } */
+/* { dg-final { scan-assembler-times {vle16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
+/* { dg-final { scan-assembler-times {vse16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c
new file mode 100644
index 0000000..dd4de3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-30.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */
+
+#include "riscv_vector.h"
+
+void
+f_vfloat16m1x2_t (void *base, void *out)
+{
+  vfloat16m1x2_t v = *(vfloat16m1x2_t*)base;
+  *(vfloat16m1x2_t*)out = v;
+}
+
+void
+f_vfloat16m1x3_t (void *base, void *out)
+{
+  vfloat16m1x3_t v = *(vfloat16m1x3_t*)base;
+  *(vfloat16m1x3_t*)out = v;
+}
+
+void
+f_vfloat16m1x4_t (void *base, void *out)
+{
+  vfloat16m1x4_t v = *(vfloat16m1x4_t*)base;
+  *(vfloat16m1x4_t*)out = v;
+}
+
+void
+f_vfloat16m1x5_t (void *base, void *out)
+{
+  vfloat16m1x5_t v = *(vfloat16m1x5_t*)base;
+  *(vfloat16m1x5_t*)out = v;
+}
+
+void
+f_vfloat16m1x6_t (void *base, void *out)
+{
+  vfloat16m1x6_t v = *(vfloat16m1x6_t*)base;
+  *(vfloat16m1x6_t*)out = v;
+}
+
+void
+f_vfloat16m1x7_t (void *base, void *out)
+{
+  vfloat16m1x7_t v = *(vfloat16m1x7_t*)base;
+  *(vfloat16m1x7_t*)out = v;
+}
+
+void
+f_vfloat16m1x8_t (void *base, void *out)
+{
+  vfloat16m1x8_t v = *(vfloat16m1x8_t*)base;
+  *(vfloat16m1x8_t*)out = v;
+}
+
+/* { dg-final { scan-assembler-not {srai} } } */
+/* { dg-final { scan-assembler-not {slli} } } */
+/* { dg-final { scan-assembler-times {vl1re16\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
+/* { dg-final { scan-assembler-times {vs1r\.v\tv[0-9]+,0\([a-x0-9]+\)} 35 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c
new file mode 100644
index 0000000..48b084e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-31.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */
+
+#include "riscv_vector.h"
+
+void
+f_vfloat16m2x2_t (void *base, void *out)
+{
+  vfloat16m2x2_t v = *(vfloat16m2x2_t*)base;
+  *(vfloat16m2x2_t*)out = v;
+}
+
+void
+f_vfloat16m2x3_t (void *base, void *out)
+{
+  vfloat16m2x3_t v = *(vfloat16m2x3_t*)base;
+  *(vfloat16m2x3_t*)out = v;
+}
+
+void
+f_vfloat16m2x4_t (void *base, void *out)
+{
+  vfloat16m2x4_t v = *(vfloat16m2x4_t*)base;
+  *(vfloat16m2x4_t*)out = v;
+}
+
+/* { dg-final { scan-assembler-not {srai} } } */
+/* { dg-final { scan-assembler {slli} } } */
+/* { dg-final { scan-assembler-times {vl2re16\.v\tv[0-9]+,0\([a-x0-9]+\)} 9 } } */
+/* { dg-final { scan-assembler-times {vs2r\.v\tv[0-9]+,0\([a-x0-9]+\)} 9 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c
new file mode 100644
index 0000000..90693d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple-32.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv32gcv_zvfh -mabi=ilp32d" } */
+
+#include "riscv_vector.h"
+
+void
+f_vfloat16m4x2_t (void *base, void *out)
+{
+  vfloat16m4x2_t v = *(vfloat16m4x2_t*)base;
+  *(vfloat16m4x2_t*)out = v;
+}
+
+/* { dg-final { scan-assembler-not {srai} } } */
+/* { dg-final { scan-assembler {slli} } } */
+/* { dg-final { scan-assembler-times {vl4re16\.v\tv[0-9]+,0\([a-x0-9]+\)} 2 } } */
+/* { dg-final { scan-assembler-times {vs4r\.v\tv[0-9]+,0\([a-x0-9]+\)} 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
index 969f142..114ee6d 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c
@@ -4,7 +4,7 @@
 #include "riscv_vector.h"
 
 void
-fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
index 63d97d3..0b24ccb 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c
@@ -5,7 +5,7 @@
 #include "riscv_vector.h"
 
 vint32m1_t
-fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the scalable vector type" } */
+fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
index 90ece60..844a5db 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c
@@ -4,7 +4,7 @@
 #include "riscv_vector.h"
 
 vint32m1_t*
-fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
index ecf6d4c..a5dc2df 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c
@@ -6,7 +6,7 @@
 typedef int v4si __attribute__ ((vector_size (16)));
 
 v4si
-fun (v4si a) {  return a; }  /* { dg-bogus "the scalable vector type" } */
+fun (v4si a) {  return a; }  /* { dg-bogus "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
index 6053e07..9dc6951 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c
@@ -2,10 +2,15 @@
 /* { dg-options "-march=rv64gcv -mabi=lp64d" } */
 
 typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; v4si b; };
+struct A { int a; int b; };
+
+void foo (int b);
 
 void
-fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */
+fun (struct A a) {
+
+        foo (a.b);
+} /* { dg-bogus "the vector type" } */
 
 void
 bar ()
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
index 63bc4a8..3a65f2c 100644
--- a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c
@@ -12,7 +12,7 @@ foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
     vl = __riscv_vsetvlmax_e16mf2();
   for (size_t i = 0; i < n; i += 1)
     {
-      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */
+      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
       vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
       vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
       __riscv_vse32_v_i32m1(out, c, vl);
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
new file mode 100644
index 0000000..2795fd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void
+fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1x3_t a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
new file mode 100644
index 0000000..9cf68d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+vint32m1x3_t*
+fun (vint32m1x3_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
+
+void
+bar ()
+{
+  vint32m1x3_t a;
+  fun (&a);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-9.c b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
new file mode 100644
index 0000000..b5f130f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/vector-abi-9.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "riscv_vector.h"
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+v4si
+fun (v4si a) {  return a; }  /* { dg-warning "the vector type" } */
+
+void
+bar ()
+{
+  v4si a;
+  fun (a);
+}
diff --git a/gcc/testsuite/gfortran.dg/pr107900.f90 b/gcc/testsuite/gfortran.dg/pr107900.f90
new file mode 100644
index 0000000..2bd80a7
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr107900.f90
@@ -0,0 +1,49 @@
+! { dg-do run }
+!
+! Contributed by Karl Kaiser  <kaiserkarl31@yahoo.com>
+!
+program test
+
+   class(*), pointer :: ptr1, ptr2(:)
+   integer, target :: i = 42
+   integer :: check = 0
+! First with associate name and no selector in select types
+   associate (c => ptr1)
+        select type (c)  ! Segfault - vptr not set
+           type is (integer)
+              stop 1
+           class default
+              check = 1
+        end select
+   end associate
+! Now do the same with the array version
+   associate (c => ptr2)
+        select type (d =>c)  ! Segfault - vptr not set
+           type is (integer)
+              stop 2
+           class default
+              check = check + 10
+        end select
+   end associate
+
+! And now with the associate name and selector
+   associate (c => ptr1)
+        select type (d => c)  ! Segfault - vptr not set
+           type is (integer)
+              stop 3
+           class default
+              check = check + 100
+        end select
+   end associate
+! Now do the same with the array version
+!   ptr2 => NULL()            !This did not fix the problem
+   associate (c => ptr2)
+        select type (d => c)  ! Segfault - vptr not set
+           type is (integer)
+              stop 4
+           class default
+              check = check + 1000
+        end select
+   end associate
+   if (check .ne. 1111) stop 5
+end program test
diff --git a/gcc/testsuite/gfortran.dg/pr108961.f90 b/gcc/testsuite/gfortran.dg/pr108961.f90
new file mode 100644
index 0000000..3e6c9df
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr108961.f90
@@ -0,0 +1,26 @@
+! { dg-do run }
+!
+! Contributed by Jeffrey Hill  <jeffrey.p.hill@nasa.gov>
+!
+module associate_ptr
+    use iso_c_binding
+contains
+    subroutine c_f_strpointer(cptr, ptr2)
+        type(c_ptr), target, intent(in) :: cptr
+        character(kind=c_char,len=4), pointer :: ptr1
+        character(kind=c_char,len=:), pointer, intent(out) :: ptr2
+        call c_f_pointer(cptr, ptr1)
+        if (ptr1 .ne. 'abcd') stop 1
+        ptr2 => ptr1                              ! Failed here
+    end subroutine
+end module
+
+program test_associate_ptr
+    use associate_ptr
+    character(kind=c_char, len=1), target :: char_array(7)
+    character(kind=c_char,len=:), pointer :: ptr2
+    char_array = ['a', 'b', 'c', 'd', c_null_char, 'e', 'f']
+! The first argument was providing a constant hidden string length => segfault
+    call c_f_strpointer(c_loc(char_array), ptr2)
+    if (ptr2 .ne. 'abcd') stop 2
+end program
diff --git a/gcc/testsuite/gfortran.dg/pr110224.f90 b/gcc/testsuite/gfortran.dg/pr110224.f90
new file mode 100644
index 0000000..186bbf5
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr110224.f90
@@ -0,0 +1,29 @@
+! { dg-do compile }
+!
+! Contributed by Neil Carlson  <neil.n.carlson@gmail.com>
+!
+module mod
+  type :: foo
+    real, pointer :: var
+  contains
+    procedure :: var_ptr
+  end type
+contains
+  function var_ptr(this) result(ref)
+    class(foo) :: this
+    real, pointer :: ref
+    ref => this%var
+  end function
+end module
+program main
+  use mod
+  type(foo) :: x
+  allocate (x%var, source = 2.0)
+  associate (var => x%var_ptr())
+    var = 1.0
+  end associate
+  if (x%var .ne. 1.0) stop 1
+  x%var_ptr() = 2.0
+  if (x%var .ne. 2.0) stop 2
+  deallocate (x%var)
+end program
diff --git a/gcc/testsuite/gfortran.dg/pr88688.f90 b/gcc/testsuite/gfortran.dg/pr88688.f90
new file mode 100644
index 0000000..3d65118
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr88688.f90
@@ -0,0 +1,62 @@
+! { dg-do run }
+!
+! Contributed by Thomas Fanning <thfanning@gmail.com>
+!
+!
+module mod
+
+    type test
+        class(*), pointer :: ptr
+    contains
+        procedure :: setref
+    end type
+
+contains
+
+    subroutine setref(my,ip)
+    implicit none
+        class(test) :: my
+        integer, pointer :: ip
+        my%ptr => ip
+    end subroutine
+
+    subroutine set7(ptr)
+    implicit none
+        class(*), pointer :: ptr
+        select type (ptr)
+            type is (integer)
+                ptr = 7
+        end select
+    end subroutine
+
+end module
+!---------------------------------------
+
+!---------------------------------------
+program bug
+use mod
+implicit none
+
+    integer, pointer :: i, j
+    type(test) :: tp
+    class(*), pointer :: lp
+
+    allocate(i,j)
+    i = 3; j = 4
+
+    call tp%setref(i)
+    select type (ap => tp%ptr)
+        class default
+            call tp%setref(j)
+            lp => ap
+            call set7(lp)
+    end select
+
+! gfortran used to give i=3 and j=7 because the associate name was not pointing
+! to the target of tp%ptr as required by F2018:19.5.1.6 but, rather, to the
+! selector itself.
+    if (i .ne. 7) stop 1
+    if (j .ne. 4) stop 2
+
+end program
+!---------------------------------------
diff --git a/gcc/testsuite/gfortran.dg/pr94380.f90 b/gcc/testsuite/gfortran.dg/pr94380.f90
new file mode 100644
index 0000000..e29594f
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr94380.f90
@@ -0,0 +1,18 @@
+! { dg-do compile }
+!
+! Contributed by Vladimir Nikishkin  <lockywolf@gmail.com>
+!
+module test
+  type testtype
+     class(*), allocatable :: t
+  end type testtype
+contains
+  subroutine testproc( x )
+    class(testtype) :: x
+    associate ( temp => x%t)
+      select type (temp)
+         type is (integer)
+      end select
+    end associate
+  end subroutine testproc
+end module test
diff --git a/gcc/testsuite/gfortran.dg/pr95398.f90 b/gcc/testsuite/gfortran.dg/pr95398.f90
index 81cc076..7576f38 100644
--- a/gcc/testsuite/gfortran.dg/pr95398.f90
+++ b/gcc/testsuite/gfortran.dg/pr95398.f90
@@ -1,5 +1,7 @@
 ! { dg-do compile }
 
+! { dg-options "-std=f2008" }
+
 program test
    implicit none
 
@@ -46,8 +48,8 @@ program test
 
 end
 
-! { dg-error "cannot be used in a variable definition context .assignment."  " " { target *-*-* } 21 }
-! { dg-error "cannot be used in a variable definition context .actual argument to INTENT = OUT.INOUT."  " " { target *-*-* } 23 }
-! { dg-error "Pointer assignment target is neither TARGET nor POINTER" " " { target *-*-* } 35 }
+! { dg-error "being used in a variable definition context .assignment."  " " { target *-*-* } 23 }
+! { dg-error "being used in a variable definition context .actual argument to INTENT = OUT.INOUT."  " " { target *-*-* } 25 }
 ! { dg-error "Pointer assignment target is neither TARGET nor POINTER" " " { target *-*-* } 37 }
+! { dg-error "Pointer assignment target is neither TARGET nor POINTER" " " { target *-*-* } 39 }
 
diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp
index 01c8c02..28529f5 100644
--- a/gcc/testsuite/lib/gcc-dg.exp
+++ b/gcc/testsuite/lib/gcc-dg.exp
@@ -364,6 +364,11 @@ proc gcc-dg-prune { system text } {
     # Always remember to clear it in .exp file after executed all tests.
     global dg_runtest_extra_prunes
 
+    # Call into multiline.exp to handle any multiline output directives.
+    # This is done before the check for blank lines so that multiline
+    # output directives can have blank lines within them.
+    set text [handle-multiline-outputs $text]
+
     # Complain about blank lines in the output (PR other/69006)
     global allow_blank_lines
     if { !$allow_blank_lines } {
diff --git a/gcc/testsuite/lib/multiline.exp b/gcc/testsuite/lib/multiline.exp
index 73621a0..4c25bb7 100644
--- a/gcc/testsuite/lib/multiline.exp
+++ b/gcc/testsuite/lib/multiline.exp
@@ -139,7 +139,7 @@ proc dg-end-multiline-output { args } {
     verbose "within dg-end-multiline-output: multiline_expected_outputs: $multiline_expected_outputs" 3
 }
 
-# Hook to be called by prune.exp's prune_gcc_output to
+# Hook to be called by gcc-dg.exp's gcc-dg-prune to
 # look for the expected multiline outputs, pruning them,
 # reporting PASS for those that are found, and FAIL for
 # those that weren't found.
@@ -149,6 +149,11 @@ proc dg-end-multiline-output { args } {
 proc handle-multiline-outputs { text } {
     global multiline_expected_outputs
     global testname_with_flags
+
+    # If dg-enable-nn-line-numbers was provided, then obscure source-margin
+    # line numbers by converting them to "NN" form.
+    set text [maybe-handle-nn-line-numbers $text]
+    
     set index 0
     foreach entry $multiline_expected_outputs {
 	verbose "  entry: $entry" 3
diff --git a/gcc/testsuite/lib/prune.exp b/gcc/testsuite/lib/prune.exp
index 8a448bb..c15034a 100644
--- a/gcc/testsuite/lib/prune.exp
+++ b/gcc/testsuite/lib/prune.exp
@@ -108,13 +108,6 @@ proc prune_gcc_output { text } {
     # Many tests that use visibility will still pass on platforms that don't support it.
     regsub -all "(^|\n)\[^\n\]*lto1: warning: visibility attribute not supported in this configuration; ignored\[^\n\]*" $text "" text
 
-    # If dg-enable-nn-line-numbers was provided, then obscure source-margin
-    # line numbers by converting them to "NN" form.
-    set text [maybe-handle-nn-line-numbers $text]
-    
-    # Call into multiline.exp to handle any multiline output directives.
-    set text [handle-multiline-outputs $text]
-
     #send_user "After:$text\n"
 
     return $text
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 184fafb..d79ad4b 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -686,7 +686,8 @@ proc check_effective_target_keeps_null_pointer_checks { } {
     if [target_info exists keeps_null_pointer_checks] {
       return 1
     }
-    if { [istarget msp430-*-*] } {
+    if { [istarget msp430-*-*]
+         || [istarget avr-*-*] } {
 	return 1;   
     }
     return 0
@@ -1804,6 +1805,55 @@ proc check_effective_target_riscv_vector { } {
     }]
 }
 
+# Return 1 if the we can build a vector example with proper -march flags
+# and the current target can execute it, 0 otherwise.  Cache the result.
+
+proc check_effective_target_riscv_vector_hw { } {
+
+    return [check_runtime riscv_vector_hw32 {
+        int main (void)
+        {
+            asm ("vsetivli zero,8,e16,m1,ta,ma");
+            asm ("vadd.vv v8,v8,v16" : : : "v8");
+            return 0;
+        }
+    } "-march=rv32gcv -mabi=ilp32d"] || [check_runtime riscv_vector_hw64 {
+        int main (void)
+        {
+            asm ("vsetivli zero,8,e16,m1,ta,ma");
+            asm ("vadd.vv v8,v8,v16" : : : "v8");
+            return 0;
+        }
+    } "-march=rv64gcv -mabi=lp64d"]
+}
+
+# Return 1 if the we can build a Zvfh vector example with proper -march flags
+# and the current target can execute it, 0 otherwise.  Cache the result.
+
+proc check_effective_target_riscv_zvfh_hw { } {
+    if ![check_effective_target_riscv_vector_hw] then {
+        return 0
+    }
+
+    return [check_runtime riscv_zvfh_hw32 {
+        int main (void)
+        {
+            asm ("vsetivli zero,8,e16,m1,ta,ma");
+            asm ("vfadd.vv v8,v8,v16" : : : "v8");
+            return 0;
+        }
+    } "-march=rv32gcv_zvfh -mabi=ilp32d"]
+    || [check_runtime riscv_zvfh_hw64 {
+        int main (void)
+        {
+            asm ("vsetivli zero,8,e16,m1,ta,ma");
+            asm ("vfadd.vv v8,v8,v16" : : : "v8");
+            return 0;
+        }
+    } "-march=rv64gcv_zvfh -mabi=lp64d"]
+}
+
+
 # Return 1 if the target is RV32, 0 otherwise.  Cache the result.
 
 proc check_effective_target_rv32 { } {
@@ -8443,8 +8493,9 @@ proc check_effective_target_vect_long_mult { } {
 
 proc check_effective_target_vect_int_mod { } {
     return [check_cached_effective_target_indexed vect_int_mod {
-      expr { [istarget powerpc*-*-*]
-	     && [check_effective_target_has_arch_pwr10] }}]
+      expr { ([istarget powerpc*-*-*]
+	      && [check_effective_target_has_arch_pwr10])
+             || [istarget amdgcn-*-*] }}]
 }
 
 # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise.
@@ -11577,7 +11628,8 @@ proc check_effective_target_divmod { } {
     #TODO: Add checks for all targets that have either hardware divmod insn
     # or define libfunc for divmod.
     if { [istarget arm*-*-*]
-	 || [istarget i?86-*-*] || [istarget x86_64-*-*] } {
+	 || [istarget i?86-*-*] || [istarget x86_64-*-*]
+         || [istarget amdgcn-*-*] } {
 	return 1
     }
     return 0
diff --git a/gcc/trans-mem.cc b/gcc/trans-mem.cc
index d036e43..9c3d112 100644
--- a/gcc/trans-mem.cc
+++ b/gcc/trans-mem.cc
@@ -637,6 +637,9 @@ diagnose_tm_1 (gimple_stmt_iterator *gsi, bool *handled_ops_p,
     {
     case GIMPLE_CALL:
       {
+	if (gimple_call_internal_p (stmt))
+	  break;
+
 	tree fn = gimple_call_fn (stmt);
 
 	if ((d->summary_flags & DIAG_TM_OUTER) == 0
diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc
index 1393ce1..e342532 100644
--- a/gcc/tree-if-conv.cc
+++ b/gcc/tree-if-conv.cc
@@ -92,7 +92,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "ssa.h"
 #include "expmed.h"
 #include "expr.h"
-#include "optabs-query.h"
+#include "optabs-tree.h"
 #include "gimple-pretty-print.h"
 #include "alias.h"
 #include "fold-const.h"
diff --git a/gcc/tree-loop-distribution.cc b/gcc/tree-loop-distribution.cc
index 6291f94..cf7c197 100644
--- a/gcc/tree-loop-distribution.cc
+++ b/gcc/tree-loop-distribution.cc
@@ -1756,11 +1756,12 @@ classify_builtin_st (loop_p loop, partition *partition, data_reference_p dr)
       return;
     }
 
-  poly_uint64 base_offset;
-  unsigned HOST_WIDE_INT const_base_offset;
-  tree base_base = strip_offset (base, &base_offset);
-  if (!base_offset.is_constant (&const_base_offset))
+  tree base_offset;
+  tree base_base;
+  split_constant_offset (base, &base_base, &base_offset);
+  if (!cst_and_fits_in_hwi (base_offset))
     return;
+  unsigned HOST_WIDE_INT const_base_offset = int_cst_value (base_offset);
 
   struct builtin_info *builtin;
   builtin = alloc_builtin (dr, NULL, base, NULL_TREE, size);
diff --git a/gcc/tree-ssa-dse.cc b/gcc/tree-ssa-dse.cc
index eabe8ba..3c7a2e9 100644
--- a/gcc/tree-ssa-dse.cc
+++ b/gcc/tree-ssa-dse.cc
@@ -1118,7 +1118,26 @@ dse_classify_store (ao_ref *ref, gimple *stmt,
       if (defs.is_empty ())
 	{
 	  if (ref_may_alias_global_p (ref, false))
-	    return DSE_STORE_LIVE;
+	    {
+	      basic_block def_bb = gimple_bb (SSA_NAME_DEF_STMT (defvar));
+	      /* Assume that BUILT_IN_UNREACHABLE and BUILT_IN_UNREACHABLE_TRAP
+		 do not need to keep (global) memory side-effects live.
+		 We do not have virtual operands on BUILT_IN_UNREACHABLE
+		 but we can do poor mans reachability when the last
+		 definition we want to elide is in the block that ends
+		 in such a call.  */
+	      if (EDGE_COUNT (def_bb->succs) == 0)
+		if (gcall *last = dyn_cast <gcall *> (*gsi_last_bb (def_bb)))
+		  if (gimple_call_builtin_p (last, BUILT_IN_UNREACHABLE)
+		      || gimple_call_builtin_p (last,
+						BUILT_IN_UNREACHABLE_TRAP))
+		    {
+		      if (by_clobber_p)
+			*by_clobber_p = false;
+		      return DSE_STORE_DEAD;
+		    }
+	      return DSE_STORE_LIVE;
+	    }
 
 	  if (by_clobber_p)
 	    *by_clobber_p = false;
diff --git a/gcc/tree-ssa-loop-ivcanon.cc b/gcc/tree-ssa-loop-ivcanon.cc
index 6a962a9..491b57e 100644
--- a/gcc/tree-ssa-loop-ivcanon.cc
+++ b/gcc/tree-ssa-loop-ivcanon.cc
@@ -1520,15 +1520,16 @@ tree_unroll_loops_completely (bool may_increase_size, bool unroll_outer)
 	    }
 	  BITMAP_FREE (fathers);
 
+	  /* Clean up the information about numbers of iterations, since
+	     complete unrolling might have invalidated it.  */
+	  scev_reset ();
+
 	  /* This will take care of removing completely unrolled loops
 	     from the loop structures so we can continue unrolling now
 	     innermost loops.  */
 	  if (cleanup_tree_cfg ())
 	    update_ssa (TODO_update_ssa_only_virtuals);
 
-	  /* Clean up the information about numbers of iterations, since
-	     complete unrolling might have invalidated it.  */
-	  scev_reset ();
 	  if (flag_checking && loops_state_satisfies_p (LOOP_CLOSED_SSA))
 	    verify_loop_closed_ssa (true);
 	}
diff --git a/gcc/tree-ssa-loop-ivopts.cc b/gcc/tree-ssa-loop-ivopts.cc
index 6fbd2d5..6671ff6 100644
--- a/gcc/tree-ssa-loop-ivopts.cc
+++ b/gcc/tree-ssa-loop-ivopts.cc
@@ -1606,7 +1606,10 @@ record_group_use (struct ivopts_data *data, tree *use_p,
     {
       unsigned int i;
 
-      addr_base = strip_offset (iv->base, &addr_offset);
+      gcc_assert (POINTER_TYPE_P (TREE_TYPE (iv->base)));
+      tree addr_toffset;
+      split_constant_offset (iv->base, &addr_base, &addr_toffset);
+      addr_offset = int_cst_value (addr_toffset);
       for (i = 0; i < data->vgroups.length (); i++)
 	{
 	  struct iv_use *use;
@@ -2942,7 +2945,7 @@ strip_offset_1 (tree expr, bool inside_addr, bool top_compref,
 
 /* Strips constant offsets from EXPR and stores them to OFFSET.  */
 
-tree
+static tree
 strip_offset (tree expr, poly_uint64_pod *offset)
 {
   poly_int64 off;
@@ -3582,9 +3585,10 @@ add_iv_candidate_for_use (struct ivopts_data *data, struct iv_use *use)
       step = fold_convert (sizetype, step);
       record_common_cand (data, base, step, use);
       /* Also record common candidate with offset stripped.  */
-      base = strip_offset (base, &offset);
-      if (maybe_ne (offset, 0U))
-	record_common_cand (data, base, step, use);
+      tree alt_base, alt_offset;
+      split_constant_offset (base, &alt_base, &alt_offset);
+      if (!integer_zerop (alt_offset))
+	record_common_cand (data, alt_base, step, use);
     }
 
   /* At last, add auto-incremental candidates.  Make such variables
diff --git a/gcc/tree-ssa-loop-ivopts.h b/gcc/tree-ssa-loop-ivopts.h
index 9514861..7a53ce4 100644
--- a/gcc/tree-ssa-loop-ivopts.h
+++ b/gcc/tree-ssa-loop-ivopts.h
@@ -28,7 +28,6 @@ extern void dump_cand (FILE *, struct iv_cand *);
 extern bool contains_abnormal_ssa_name_p (tree);
 extern class loop *outermost_invariant_loop_for_expr (class loop *, tree);
 extern bool expr_invariant_in_loop_p (class loop *, tree);
-extern tree strip_offset (tree, poly_uint64_pod *);
 bool may_be_nonaddressable_p (tree expr);
 void tree_ssa_iv_optimize (void);
 
diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc
index b2764d4..da01d4a 100644
--- a/gcc/tree-ssa-math-opts.cc
+++ b/gcc/tree-ssa-math-opts.cc
@@ -4728,6 +4728,7 @@ match_uaddc_usubc (gimple_stmt_iterator *gsi, gimple *stmt, tree_code code)
   if (!types_compatible_p (type, TREE_TYPE (arg1)))
     return false;
   int kind[2] = { 0, 0 };
+  tree arg_im[2] = { NULL_TREE, NULL_TREE };
   /* At least one of arg2 and arg3 should have type compatible
      with arg1/rhs[0], and the other one should have value in [0, 1]
      range.  If both are in [0, 1] range and type compatible with
@@ -4758,6 +4759,7 @@ match_uaddc_usubc (gimple_stmt_iterator *gsi, gimple *stmt, tree_code code)
 	  g = uaddc_ne0 (g);
 	  if (!uaddc_is_cplxpart (g, IMAGPART_EXPR))
 	    continue;
+	  arg_im[i] = gimple_assign_lhs (g);
 	  g = SSA_NAME_DEF_STMT (TREE_OPERAND (gimple_assign_rhs1 (g), 0));
 	  if (!is_gimple_call (g) || !gimple_call_internal_p (g))
 	    continue;
@@ -4781,6 +4783,7 @@ match_uaddc_usubc (gimple_stmt_iterator *gsi, gimple *stmt, tree_code code)
     {
       std::swap (arg2, arg3);
       std::swap (kind[0], kind[1]);
+      std::swap (arg_im[0], arg_im[1]);
     }
   if ((kind[0] & 1) == 0 || (kind[1] & 6) == 0)
     return false;
@@ -4810,6 +4813,8 @@ match_uaddc_usubc (gimple_stmt_iterator *gsi, gimple *stmt, tree_code code)
   /* Build .UADDC/.USUBC call which will be placed before the stmt.  */
   gimple_stmt_iterator gsi2 = gsi_for_stmt (ovf2);
   gimple *g;
+  if ((kind[1] & 4) != 0 && types_compatible_p (type, TREE_TYPE (arg_im[1])))
+    arg3 = arg_im[1];
   if ((kind[1] & 1) == 0)
     {
       if (TREE_CODE (arg3) == INTEGER_CST)
@@ -5558,9 +5563,12 @@ math_opts_dom_walker::after_dom_children (basic_block bb)
 
 	    case PLUS_EXPR:
 	    case MINUS_EXPR:
-	      if (!convert_plusminus_to_widen (&gsi, stmt, code)
-		  && !match_arith_overflow (&gsi, stmt, code, m_cfg_changed_p))
-		match_uaddc_usubc (&gsi, stmt, code);
+	      if (!convert_plusminus_to_widen (&gsi, stmt, code))
+		{
+		  match_arith_overflow (&gsi, stmt, code, m_cfg_changed_p);
+		  if (gsi_stmt (gsi) == stmt)
+		    match_uaddc_usubc (&gsi, stmt, code);
+		}
 	      break;
 
 	    case BIT_NOT_EXPR:
diff --git a/gcc/tree-ssa-phiprop.cc b/gcc/tree-ssa-phiprop.cc
index 3cb4900..21a349a 100644
--- a/gcc/tree-ssa-phiprop.cc
+++ b/gcc/tree-ssa-phiprop.cc
@@ -33,6 +33,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "gimple-iterator.h"
 #include "stor-layout.h"
 #include "tree-ssa-loop.h"
+#include "tree-cfg.h"
 
 /* This pass propagates indirect loads through the PHI node for its
    address to make the load source possibly non-addressable and to
@@ -153,6 +154,8 @@ phiprop_insert_phi (basic_block bb, gphi *phi, gimple *use_stmt,
       print_gimple_stmt (dump_file, use_stmt, 0);
     }
 
+  gphi *vphi = get_virtual_phi (bb);
+
   /* Add PHI arguments for each edge inserting loads of the
      addressable operands.  */
   FOR_EACH_EDGE (e, ei, bb->preds)
@@ -190,9 +193,20 @@ phiprop_insert_phi (basic_block bb, gphi *phi, gimple *use_stmt,
 	{
 	  tree rhs = gimple_assign_rhs1 (use_stmt);
 	  gcc_assert (TREE_CODE (old_arg) == ADDR_EXPR);
+	  tree vuse = NULL_TREE;
 	  if (TREE_CODE (res) == SSA_NAME)
-	    new_var = make_ssa_name (TREE_TYPE (rhs));
+	    {
+	      new_var = make_ssa_name (TREE_TYPE (rhs));
+	      if (vphi)
+		vuse = PHI_ARG_DEF_FROM_EDGE (vphi, e);
+	      else
+		vuse = gimple_vuse (use_stmt);
+	    }
 	  else
+	    /* For the aggregate copy case updating virtual operands
+	       we'd have to possibly insert a virtual PHI and we have
+	       to split the existing VUSE lifetime.  Leave that to
+	       the generic SSA updating.  */
 	    new_var = unshare_expr (res);
 	  if (!is_gimple_min_invariant (old_arg))
 	    old_arg = PHI_ARG_DEF_FROM_EDGE (phi, e);
@@ -203,6 +217,8 @@ phiprop_insert_phi (basic_block bb, gphi *phi, gimple *use_stmt,
 						  old_arg,
 						  TREE_OPERAND (rhs, 1)));
 	  gimple_set_location (tmp, locus);
+	  if (vuse)
+	    gimple_set_vuse (tmp, vuse);
 
 	  gsi_insert_on_edge (e, tmp);
 	  update_stmt (tmp);
@@ -476,6 +492,7 @@ public:
   {}
 
   /* opt_pass methods: */
+  opt_pass * clone () final override { return new pass_phiprop (m_ctxt); }
   bool gate (function *) final override { return flag_tree_phiprop; }
   unsigned int execute (function *) final override;
 
diff --git a/gcc/tree-vect-generic.cc b/gcc/tree-vect-generic.cc
index b7d4a91..df04a0d 100644
--- a/gcc/tree-vect-generic.cc
+++ b/gcc/tree-vect-generic.cc
@@ -44,6 +44,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "gimple-fold.h"
 #include "gimple-match.h"
 #include "recog.h"		/* FIXME: for insn_data */
+#include "optabs-libfuncs.h"
 
 
 /* Build a ternary operation and gimplify it.  Emit code before GSI.
@@ -1714,7 +1715,9 @@ get_compute_type (enum tree_code code, optab op, tree type)
       machine_mode compute_mode = TYPE_MODE (compute_type);
       if (VECTOR_MODE_P (compute_mode))
 	{
-	  if (op && optab_handler (op, compute_mode) != CODE_FOR_nothing)
+	  if (op
+	      && (optab_handler (op, compute_mode) != CODE_FOR_nothing
+		  || optab_libfunc (op, compute_mode)))
 	    return compute_type;
 	  if (code == MULT_HIGHPART_EXPR
 	      && can_mult_highpart_p (compute_mode,
diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
index 1c8100c..20f570e 100644
--- a/gcc/tree-vect-loop-manip.cc
+++ b/gcc/tree-vect-loop-manip.cc
@@ -50,6 +50,9 @@ along with GCC; see the file COPYING3.  If not see
 #include "insn-config.h"
 #include "rtl.h"
 #include "recog.h"
+#include "langhooks.h"
+#include "tree-vector-builder.h"
+#include "optabs-tree.h"
 
 /*************************************************************************
   Simple Loop Peeling Utilities
@@ -817,6 +820,8 @@ vect_set_loop_condition_partial_vectors (class loop *loop,
   tree ni_actual_type = TREE_TYPE (niters);
   unsigned int ni_actual_precision = TYPE_PRECISION (ni_actual_type);
   tree niters_skip = LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo);
+  if (niters_skip)
+    niters_skip = gimple_convert (&preheader_seq, compare_type, niters_skip);
 
   /* Convert NITERS to the same size as the compare.  */
   if (compare_precision > ni_actual_precision
@@ -845,7 +850,7 @@ vect_set_loop_condition_partial_vectors (class loop *loop,
   rgroup_controls *iv_rgc = nullptr;
   unsigned int i;
   auto_vec<rgroup_controls> *controls = use_masks_p
-					  ? &LOOP_VINFO_MASKS (loop_vinfo)
+					  ? &LOOP_VINFO_MASKS (loop_vinfo).rgc_vec
 					  : &LOOP_VINFO_LENS (loop_vinfo);
   FOR_EACH_VEC_ELT (*controls, i, rgc)
     if (!rgc->controls.is_empty ())
@@ -936,6 +941,244 @@ vect_set_loop_condition_partial_vectors (class loop *loop,
   return cond_stmt;
 }
 
+/* Set up the iteration condition and rgroup controls for LOOP in AVX512
+   style, given that LOOP_VINFO_USING_PARTIAL_VECTORS_P is true for the
+   vectorized loop.  LOOP_VINFO describes the vectorization of LOOP.  NITERS is
+   the number of iterations of the original scalar loop that should be
+   handled by the vector loop.  NITERS_MAYBE_ZERO and FINAL_IV are as
+   for vect_set_loop_condition.
+
+   Insert the branch-back condition before LOOP_COND_GSI and return the
+   final gcond.  */
+
+static gcond *
+vect_set_loop_condition_partial_vectors_avx512 (class loop *loop,
+					 loop_vec_info loop_vinfo, tree niters,
+					 tree final_iv,
+					 bool niters_maybe_zero,
+					 gimple_stmt_iterator loop_cond_gsi)
+{
+  tree niters_skip = LOOP_VINFO_MASK_SKIP_NITERS (loop_vinfo);
+  tree iv_type = LOOP_VINFO_RGROUP_IV_TYPE (loop_vinfo);
+  poly_uint64 vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo);
+  tree orig_niters = niters;
+  gimple_seq preheader_seq = NULL;
+
+  /* Create an IV that counts down from niters and whose step
+     is the number of iterations processed in the current iteration.
+     Produce the controls with compares like the following.
+
+       # iv_2 = PHI <niters, iv_3>
+       rem_4 = MIN <iv_2, VF>;
+       remv_6 = { rem_4, rem_4, rem_4, ... }
+       mask_5 = { 0, 0, 1, 1, 2, 2, ... } < remv6;
+       iv_3 = iv_2 - VF;
+       if (iv_2 > VF)
+	 continue;
+
+     Where the constant is built with elements at most VF - 1 and
+     repetitions according to max_nscalars_per_iter which is guarnateed
+     to be the same within a group.  */
+
+  /* Convert NITERS to the determined IV type.  */
+  if (TYPE_PRECISION (iv_type) > TYPE_PRECISION (TREE_TYPE (niters))
+      && niters_maybe_zero)
+    {
+      /* We know that there is always at least one iteration, so if the
+	 count is zero then it must have wrapped.  Cope with this by
+	 subtracting 1 before the conversion and adding 1 to the result.  */
+      gcc_assert (TYPE_UNSIGNED (TREE_TYPE (niters)));
+      niters = gimple_build (&preheader_seq, PLUS_EXPR, TREE_TYPE (niters),
+			     niters, build_minus_one_cst (TREE_TYPE (niters)));
+      niters = gimple_convert (&preheader_seq, iv_type, niters);
+      niters = gimple_build (&preheader_seq, PLUS_EXPR, iv_type,
+			     niters, build_one_cst (iv_type));
+    }
+  else
+    niters = gimple_convert (&preheader_seq, iv_type, niters);
+
+  /* Bias the initial value of the IV in case we need to skip iterations
+     at the beginning.  */
+  tree niters_adj = niters;
+  if (niters_skip)
+    {
+      tree skip = gimple_convert (&preheader_seq, iv_type, niters_skip);
+      niters_adj = gimple_build (&preheader_seq, PLUS_EXPR,
+				 iv_type, niters, skip);
+    }
+
+  /* The iteration step is the vectorization factor.  */
+  tree iv_step = build_int_cst (iv_type, vf);
+
+  /* Create the decrement IV.  */
+  tree index_before_incr, index_after_incr;
+  gimple_stmt_iterator incr_gsi;
+  bool insert_after;
+  standard_iv_increment_position (loop, &incr_gsi, &insert_after);
+  create_iv (niters_adj, MINUS_EXPR, iv_step, NULL_TREE, loop,
+	     &incr_gsi, insert_after, &index_before_incr,
+	     &index_after_incr);
+
+  /* Iterate over all the rgroups and fill in their controls.  */
+  for (auto &rgc : LOOP_VINFO_MASKS (loop_vinfo).rgc_vec)
+    {
+      if (rgc.controls.is_empty ())
+	continue;
+
+      tree ctrl_type = rgc.type;
+      poly_uint64 nitems_per_ctrl = TYPE_VECTOR_SUBPARTS (ctrl_type);
+
+      tree vectype = rgc.compare_type;
+
+      /* index_after_incr is the IV specifying the remaining iterations in
+	 the next iteration.  */
+      tree rem = index_after_incr;
+      /* When the data type for the compare to produce the mask is
+	 smaller than the IV type we need to saturate.  Saturate to
+	 the smallest possible value (IV_TYPE) so we only have to
+	 saturate once (CSE will catch redundant ones we add).  */
+      if (TYPE_PRECISION (TREE_TYPE (vectype)) < TYPE_PRECISION (iv_type))
+	rem = gimple_build (&incr_gsi, false, GSI_CONTINUE_LINKING,
+			    UNKNOWN_LOCATION,
+			    MIN_EXPR, TREE_TYPE (rem), rem, iv_step);
+      rem = gimple_convert (&incr_gsi, false, GSI_CONTINUE_LINKING,
+			    UNKNOWN_LOCATION, TREE_TYPE (vectype), rem);
+
+      /* Build a data vector composed of the remaining iterations.  */
+      rem = gimple_build_vector_from_val (&incr_gsi, false, GSI_CONTINUE_LINKING,
+					  UNKNOWN_LOCATION, vectype, rem);
+
+      /* Provide a definition of each vector in the control group.  */
+      tree next_ctrl = NULL_TREE;
+      tree first_rem = NULL_TREE;
+      tree ctrl;
+      unsigned int i;
+      FOR_EACH_VEC_ELT_REVERSE (rgc.controls, i, ctrl)
+	{
+	  /* Previous controls will cover BIAS items.  This control covers the
+	     next batch.  */
+	  poly_uint64 bias = nitems_per_ctrl * i;
+
+	  /* Build the constant to compare the remaining iters against,
+	     this is sth like { 0, 0, 1, 1, 2, 2, 3, 3, ... } appropriately
+	     split into pieces.  */
+	  unsigned n = TYPE_VECTOR_SUBPARTS (ctrl_type).to_constant ();
+	  tree_vector_builder builder (vectype, n, 1);
+	  for (unsigned i = 0; i < n; ++i)
+	    {
+	      unsigned HOST_WIDE_INT val
+		= (i + bias.to_constant ()) / rgc.max_nscalars_per_iter;
+	      gcc_assert (val < vf.to_constant ());
+	      builder.quick_push (build_int_cst (TREE_TYPE (vectype), val));
+	    }
+	  tree cmp_series = builder.build ();
+
+	  /* Create the initial control.  First include all items that
+	     are within the loop limit.  */
+	  tree init_ctrl = NULL_TREE;
+	  poly_uint64 const_limit;
+	  /* See whether the first iteration of the vector loop is known
+	     to have a full control.  */
+	  if (poly_int_tree_p (niters, &const_limit)
+	      && known_ge (const_limit, (i + 1) * nitems_per_ctrl))
+	    init_ctrl = build_minus_one_cst (ctrl_type);
+	  else
+	    {
+	      /* The remaining work items initially are niters.  Saturate,
+		 splat and compare.  */
+	      if (!first_rem)
+		{
+		  first_rem = niters;
+		  if (TYPE_PRECISION (TREE_TYPE (vectype))
+		      < TYPE_PRECISION (iv_type))
+		    first_rem = gimple_build (&preheader_seq,
+					      MIN_EXPR, TREE_TYPE (first_rem),
+					      first_rem, iv_step);
+		  first_rem = gimple_convert (&preheader_seq, TREE_TYPE (vectype),
+					      first_rem);
+		  first_rem = gimple_build_vector_from_val (&preheader_seq,
+							    vectype, first_rem);
+		}
+	      init_ctrl = gimple_build (&preheader_seq, LT_EXPR, ctrl_type,
+					cmp_series, first_rem);
+	    }
+
+	  /* Now AND out the bits that are within the number of skipped
+	     items.  */
+	  poly_uint64 const_skip;
+	  if (niters_skip
+	      && !(poly_int_tree_p (niters_skip, &const_skip)
+		   && known_le (const_skip, bias)))
+	    {
+	      /* For integer mode masks it's cheaper to shift out the bits
+		 since that avoids loading a constant.  */
+	      gcc_assert (GET_MODE_CLASS (TYPE_MODE (ctrl_type)) == MODE_INT);
+	      init_ctrl = gimple_build (&preheader_seq, VIEW_CONVERT_EXPR,
+					lang_hooks.types.type_for_mode
+					  (TYPE_MODE (ctrl_type), 1),
+					init_ctrl);
+	      /* ???  But when the shift amount isn't constant this requires
+		 a round-trip to GRPs.  We could apply the bias to either
+		 side of the compare instead.  */
+	      tree shift = gimple_build (&preheader_seq, MULT_EXPR,
+					 TREE_TYPE (niters_skip), niters_skip,
+					 build_int_cst (TREE_TYPE (niters_skip),
+							rgc.max_nscalars_per_iter));
+	      init_ctrl = gimple_build (&preheader_seq, LSHIFT_EXPR,
+					TREE_TYPE (init_ctrl),
+					init_ctrl, shift);
+	      init_ctrl = gimple_build (&preheader_seq, VIEW_CONVERT_EXPR,
+					ctrl_type, init_ctrl);
+	    }
+
+	  /* Get the control value for the next iteration of the loop.  */
+	  next_ctrl = gimple_build (&incr_gsi, false, GSI_CONTINUE_LINKING,
+				    UNKNOWN_LOCATION,
+				    LT_EXPR, ctrl_type, cmp_series, rem);
+
+	  vect_set_loop_control (loop, ctrl, init_ctrl, next_ctrl);
+	}
+    }
+
+  /* Emit all accumulated statements.  */
+  add_preheader_seq (loop, preheader_seq);
+
+  /* Adjust the exit test using the decrementing IV.  */
+  edge exit_edge = single_exit (loop);
+  tree_code code = (exit_edge->flags & EDGE_TRUE_VALUE) ? LE_EXPR : GT_EXPR;
+  /* When we peel for alignment with niter_skip != 0 this can
+     cause niter + niter_skip to wrap and since we are comparing the
+     value before the decrement here we get a false early exit.
+     We can't compare the value after decrement either because that
+     decrement could wrap as well as we're not doing a saturating
+     decrement.  To avoid this situation we force a larger
+     iv_type.  */
+  gcond *cond_stmt = gimple_build_cond (code, index_before_incr, iv_step,
+					NULL_TREE, NULL_TREE);
+  gsi_insert_before (&loop_cond_gsi, cond_stmt, GSI_SAME_STMT);
+
+  /* The loop iterates (NITERS - 1 + NITERS_SKIP) / VF + 1 times.
+     Subtract one from this to get the latch count.  */
+  tree niters_minus_one
+    = fold_build2 (PLUS_EXPR, TREE_TYPE (orig_niters), orig_niters,
+		   build_minus_one_cst (TREE_TYPE (orig_niters)));
+  tree niters_adj2 = fold_convert (iv_type, niters_minus_one);
+  if (niters_skip)
+    niters_adj2 = fold_build2 (PLUS_EXPR, iv_type, niters_minus_one,
+			       fold_convert (iv_type, niters_skip));
+  loop->nb_iterations = fold_build2 (TRUNC_DIV_EXPR, iv_type,
+				     niters_adj2, iv_step);
+
+  if (final_iv)
+    {
+      gassign *assign = gimple_build_assign (final_iv, orig_niters);
+      gsi_insert_on_edge_immediate (single_exit (loop), assign);
+    }
+
+  return cond_stmt;
+}
+
+
 /* Like vect_set_loop_condition, but handle the case in which the vector
    loop handles exactly VF scalars per iteration.  */
 
@@ -1114,10 +1357,18 @@ vect_set_loop_condition (class loop *loop, loop_vec_info loop_vinfo,
   gimple_stmt_iterator loop_cond_gsi = gsi_for_stmt (orig_cond);
 
   if (loop_vinfo && LOOP_VINFO_USING_PARTIAL_VECTORS_P (loop_vinfo))
-    cond_stmt = vect_set_loop_condition_partial_vectors (loop, loop_vinfo,
-							 niters, final_iv,
-							 niters_maybe_zero,
-							 loop_cond_gsi);
+    {
+      if (LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo) == vect_partial_vectors_avx512)
+	cond_stmt = vect_set_loop_condition_partial_vectors_avx512 (loop, loop_vinfo,
+								    niters, final_iv,
+								    niters_maybe_zero,
+								    loop_cond_gsi);
+      else
+	cond_stmt = vect_set_loop_condition_partial_vectors (loop, loop_vinfo,
+							     niters, final_iv,
+							     niters_maybe_zero,
+							     loop_cond_gsi);
+    }
   else
     cond_stmt = vect_set_loop_condition_normal (loop, niters, step, final_iv,
 						niters_maybe_zero,
@@ -2030,7 +2281,7 @@ void
 vect_prepare_for_masked_peels (loop_vec_info loop_vinfo)
 {
   tree misalign_in_elems;
-  tree type = LOOP_VINFO_RGROUP_COMPARE_TYPE (loop_vinfo);
+  tree type = TREE_TYPE (LOOP_VINFO_NITERS (loop_vinfo));
 
   gcc_assert (vect_use_loop_mask_for_alignment_p (loop_vinfo));
 
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index ace9e75..0a03f56 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -55,6 +55,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "vec-perm-indices.h"
 #include "tree-eh.h"
 #include "case-cfn-macros.h"
+#include "langhooks.h"
 
 /* Loop Vectorization Pass.
 
@@ -963,6 +964,7 @@ _loop_vec_info::_loop_vec_info (class loop *loop_in, vec_info_shared *shared)
     mask_skip_niters (NULL_TREE),
     rgroup_compare_type (NULL_TREE),
     simd_if_cond (NULL_TREE),
+    partial_vector_style (vect_partial_vectors_none),
     unaligned_dr (NULL),
     peeling_for_alignment (0),
     ptr_mask (0),
@@ -1058,7 +1060,7 @@ _loop_vec_info::~_loop_vec_info ()
 {
   free (bbs);
 
-  release_vec_loop_controls (&masks);
+  release_vec_loop_controls (&masks.rgc_vec);
   release_vec_loop_controls (&lens);
   delete ivexpr_map;
   delete scan_map;
@@ -1108,7 +1110,7 @@ can_produce_all_loop_masks_p (loop_vec_info loop_vinfo, tree cmp_type)
 {
   rgroup_controls *rgm;
   unsigned int i;
-  FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo), i, rgm)
+  FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo).rgc_vec, i, rgm)
     if (rgm->type != NULL_TREE
 	&& !direct_internal_fn_supported_p (IFN_WHILE_ULT,
 					    cmp_type, rgm->type,
@@ -1126,7 +1128,7 @@ vect_get_max_nscalars_per_iter (loop_vec_info loop_vinfo)
   unsigned int res = 1;
   unsigned int i;
   rgroup_controls *rgm;
-  FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo), i, rgm)
+  FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo).rgc_vec, i, rgm)
     res = MAX (res, rgm->max_nscalars_per_iter);
   return res;
 }
@@ -1210,8 +1212,6 @@ static bool
 vect_verify_full_masking (loop_vec_info loop_vinfo)
 {
   unsigned int min_ni_width;
-  unsigned int max_nscalars_per_iter
-    = vect_get_max_nscalars_per_iter (loop_vinfo);
 
   /* Use a normal loop if there are no statements that need masking.
      This only happens in rare degenerate cases: it means that the loop
@@ -1219,6 +1219,33 @@ vect_verify_full_masking (loop_vec_info loop_vinfo)
   if (LOOP_VINFO_MASKS (loop_vinfo).is_empty ())
     return false;
 
+  /* Produce the rgroup controls.  */
+  for (auto mask : LOOP_VINFO_MASKS (loop_vinfo).mask_set)
+    {
+      vec_loop_masks *masks = &LOOP_VINFO_MASKS (loop_vinfo);
+      tree vectype = mask.first;
+      unsigned nvectors = mask.second;
+
+      if (masks->rgc_vec.length () < nvectors)
+	masks->rgc_vec.safe_grow_cleared (nvectors, true);
+      rgroup_controls *rgm = &(*masks).rgc_vec[nvectors - 1];
+      /* The number of scalars per iteration and the number of vectors are
+	 both compile-time constants.  */
+      unsigned int nscalars_per_iter
+	  = exact_div (nvectors * TYPE_VECTOR_SUBPARTS (vectype),
+		       LOOP_VINFO_VECT_FACTOR (loop_vinfo)).to_constant ();
+
+      if (rgm->max_nscalars_per_iter < nscalars_per_iter)
+	{
+	  rgm->max_nscalars_per_iter = nscalars_per_iter;
+	  rgm->type = truth_type_for (vectype);
+	  rgm->factor = 1;
+	}
+    }
+
+  unsigned int max_nscalars_per_iter
+    = vect_get_max_nscalars_per_iter (loop_vinfo);
+
   /* Work out how many bits we need to represent the limit.  */
   min_ni_width
     = vect_min_prec_for_max_niters (loop_vinfo, max_nscalars_per_iter);
@@ -1278,10 +1305,152 @@ vect_verify_full_masking (loop_vec_info loop_vinfo)
     }
 
   if (!cmp_type)
-    return false;
+    {
+      LOOP_VINFO_MASKS (loop_vinfo).rgc_vec.release ();
+      return false;
+    }
 
   LOOP_VINFO_RGROUP_COMPARE_TYPE (loop_vinfo) = cmp_type;
   LOOP_VINFO_RGROUP_IV_TYPE (loop_vinfo) = iv_type;
+  LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo) = vect_partial_vectors_while_ult;
+  return true;
+}
+
+/* Each statement in LOOP_VINFO can be masked where necessary.  Check
+   whether we can actually generate AVX512 style masks.  Return true if so,
+   storing the type of the scalar IV in LOOP_VINFO_RGROUP_IV_TYPE.  */
+
+static bool
+vect_verify_full_masking_avx512 (loop_vec_info loop_vinfo)
+{
+  /* Produce differently organized rgc_vec and differently check
+     we can produce masks.  */
+
+  /* Use a normal loop if there are no statements that need masking.
+     This only happens in rare degenerate cases: it means that the loop
+     has no loads, no stores, and no live-out values.  */
+  if (LOOP_VINFO_MASKS (loop_vinfo).is_empty ())
+    return false;
+
+  /* For the decrementing IV we need to represent all values in
+     [0, niter + niter_skip] where niter_skip is the elements we
+     skip in the first iteration for prologue peeling.  */
+  tree iv_type = NULL_TREE;
+  widest_int iv_limit = vect_iv_limit_for_partial_vectors (loop_vinfo);
+  unsigned int iv_precision = UINT_MAX;
+  if (iv_limit != -1)
+    iv_precision = wi::min_precision (iv_limit, UNSIGNED);
+
+  /* First compute the type for the IV we use to track the remaining
+     scalar iterations.  */
+  opt_scalar_int_mode cmp_mode_iter;
+  FOR_EACH_MODE_IN_CLASS (cmp_mode_iter, MODE_INT)
+    {
+      unsigned int cmp_bits = GET_MODE_BITSIZE (cmp_mode_iter.require ());
+      if (cmp_bits >= iv_precision
+	  && targetm.scalar_mode_supported_p (cmp_mode_iter.require ()))
+	{
+	  iv_type = build_nonstandard_integer_type (cmp_bits, true);
+	  if (iv_type)
+	    break;
+	}
+    }
+  if (!iv_type)
+    return false;
+
+  /* Produce the rgroup controls.  */
+  for (auto const &mask : LOOP_VINFO_MASKS (loop_vinfo).mask_set)
+    {
+      vec_loop_masks *masks = &LOOP_VINFO_MASKS (loop_vinfo);
+      tree vectype = mask.first;
+      unsigned nvectors = mask.second;
+
+      /* The number of scalars per iteration and the number of vectors are
+	 both compile-time constants.  */
+      unsigned int nscalars_per_iter
+	= exact_div (nvectors * TYPE_VECTOR_SUBPARTS (vectype),
+		     LOOP_VINFO_VECT_FACTOR (loop_vinfo)).to_constant ();
+
+      /* We index the rgroup_controls vector with nscalars_per_iter
+	 which we keep constant and instead have a varying nvectors,
+	 remembering the vector mask with the fewest nV.  */
+      if (masks->rgc_vec.length () < nscalars_per_iter)
+	masks->rgc_vec.safe_grow_cleared (nscalars_per_iter, true);
+      rgroup_controls *rgm = &(*masks).rgc_vec[nscalars_per_iter - 1];
+
+      if (!rgm->type || rgm->factor > nvectors)
+	{
+	  rgm->type = truth_type_for (vectype);
+	  rgm->compare_type = NULL_TREE;
+	  rgm->max_nscalars_per_iter = nscalars_per_iter;
+	  rgm->factor = nvectors;
+	  rgm->bias_adjusted_ctrl = NULL_TREE;
+	}
+    }
+
+  /* There is no fixed compare type we are going to use but we have to
+     be able to get at one for each mask group.  */
+  unsigned int min_ni_width
+    = wi::min_precision (vect_max_vf (loop_vinfo), UNSIGNED);
+
+  bool ok = true;
+  for (auto &rgc : LOOP_VINFO_MASKS (loop_vinfo).rgc_vec)
+    {
+      tree mask_type = rgc.type;
+      if (!mask_type)
+	continue;
+
+      if (TYPE_PRECISION (TREE_TYPE (mask_type)) != 1)
+	{
+	  ok = false;
+	  break;
+	}
+
+      /* If iv_type is usable as compare type use that - we can elide the
+	 saturation in that case.   */
+      if (TYPE_PRECISION (iv_type) >= min_ni_width)
+	{
+	  tree cmp_vectype
+	    = build_vector_type (iv_type, TYPE_VECTOR_SUBPARTS (mask_type));
+	  if (expand_vec_cmp_expr_p (cmp_vectype, mask_type, LT_EXPR))
+	    rgc.compare_type = cmp_vectype;
+	}
+      if (!rgc.compare_type)
+	FOR_EACH_MODE_IN_CLASS (cmp_mode_iter, MODE_INT)
+	  {
+	    unsigned int cmp_bits = GET_MODE_BITSIZE (cmp_mode_iter.require ());
+	    if (cmp_bits >= min_ni_width
+		&& targetm.scalar_mode_supported_p (cmp_mode_iter.require ()))
+	      {
+		tree cmp_type = build_nonstandard_integer_type (cmp_bits, true);
+		if (!cmp_type)
+		  continue;
+
+		/* Check whether we can produce the mask with cmp_type.  */
+		tree cmp_vectype
+		  = build_vector_type (cmp_type, TYPE_VECTOR_SUBPARTS (mask_type));
+		if (expand_vec_cmp_expr_p (cmp_vectype, mask_type, LT_EXPR))
+		  {
+		    rgc.compare_type = cmp_vectype;
+		    break;
+		  }
+	      }
+	}
+      if (!rgc.compare_type)
+	{
+	  ok = false;
+	  break;
+	}
+    }
+  if (!ok)
+    {
+      release_vec_loop_controls (&LOOP_VINFO_MASKS (loop_vinfo).rgc_vec);
+      return false;
+    }
+
+  LOOP_VINFO_RGROUP_COMPARE_TYPE (loop_vinfo) = error_mark_node;
+  LOOP_VINFO_RGROUP_IV_TYPE (loop_vinfo) = iv_type;
+  LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo) = vect_partial_vectors_avx512;
   return true;
 }
 
@@ -1381,6 +1550,7 @@ vect_verify_loop_lens (loop_vec_info loop_vinfo)
 
   LOOP_VINFO_RGROUP_COMPARE_TYPE (loop_vinfo) = iv_type;
   LOOP_VINFO_RGROUP_IV_TYPE (loop_vinfo) = iv_type;
+  LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo) = vect_partial_vectors_len;
 
   return true;
 }
@@ -2722,16 +2892,24 @@ start_over:
 
   /* If we still have the option of using partial vectors,
      check whether we can generate the necessary loop controls.  */
-  if (LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo)
-      && !vect_verify_full_masking (loop_vinfo)
-      && !vect_verify_loop_lens (loop_vinfo))
-    LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) = false;
+  if (LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo))
+    {
+      if (!LOOP_VINFO_MASKS (loop_vinfo).is_empty ())
+	{
+	  if (!vect_verify_full_masking (loop_vinfo)
+	      && !vect_verify_full_masking_avx512 (loop_vinfo))
+	    LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) = false;
+	}
+      else /* !LOOP_VINFO_LENS (loop_vinfo).is_empty () */
+	if (!vect_verify_loop_lens (loop_vinfo))
+	  LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) = false;
+    }
 
   /* If we're vectorizing a loop that uses length "controls" and
      can iterate more than once, we apply decrementing IV approach
      in loop control.  */
   if (LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo)
-      && !LOOP_VINFO_LENS (loop_vinfo).is_empty ()
+      && LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo) == vect_partial_vectors_len
       && LOOP_VINFO_PARTIAL_LOAD_STORE_BIAS (loop_vinfo) == 0
       && !(LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
 	   && known_le (LOOP_VINFO_INT_NITERS (loop_vinfo),
@@ -3032,7 +3210,8 @@ again:
   delete loop_vinfo->vector_costs;
   loop_vinfo->vector_costs = nullptr;
   /* Reset accumulated rgroup information.  */
-  release_vec_loop_controls (&LOOP_VINFO_MASKS (loop_vinfo));
+  LOOP_VINFO_MASKS (loop_vinfo).mask_set.empty ();
+  release_vec_loop_controls (&LOOP_VINFO_MASKS (loop_vinfo).rgc_vec);
   release_vec_loop_controls (&LOOP_VINFO_LENS (loop_vinfo));
   /* Reset assorted flags.  */
   LOOP_VINFO_PEELING_FOR_NITER (loop_vinfo) = false;
@@ -4372,13 +4551,69 @@ vect_estimate_min_profitable_iters (loop_vec_info loop_vinfo,
 			  cond_branch_not_taken, vect_epilogue);
 
   /* Take care of special costs for rgroup controls of partial vectors.  */
-  if (LOOP_VINFO_FULLY_MASKED_P (loop_vinfo))
+  if (LOOP_VINFO_FULLY_MASKED_P (loop_vinfo)
+      && (LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo)
+	  == vect_partial_vectors_avx512))
+    {
+      /* Calculate how many masks we need to generate.  */
+      unsigned int num_masks = 0;
+      bool need_saturation = false;
+      for (auto rgm : LOOP_VINFO_MASKS (loop_vinfo).rgc_vec)
+	if (rgm.type)
+	  {
+	    unsigned nvectors = rgm.factor;
+	    num_masks += nvectors;
+	    if (TYPE_PRECISION (TREE_TYPE (rgm.compare_type))
+		< TYPE_PRECISION (LOOP_VINFO_RGROUP_IV_TYPE (loop_vinfo)))
+	      need_saturation = true;
+	  }
+
+      /* ???  The target isn't able to identify the costs below as
+	 producing masks so it cannot penaltize cases where we'd run
+	 out of mask registers for example.  */
+
+      /* ???  We are also failing to account for smaller vector masks
+	 we generate by splitting larger masks in vect_get_loop_mask.  */
+
+      /* In the worst case, we need to generate each mask in the prologue
+	 and in the loop body.  We need one splat per group and one
+	 compare per mask.
+
+	 Sometimes the prologue mask will fold to a constant,
+	 so the actual prologue cost might be smaller.  However, it's
+	 simpler and safer to use the worst-case cost; if this ends up
+	 being the tie-breaker between vectorizing or not, then it's
+	 probably better not to vectorize.  */
+      (void) add_stmt_cost (target_cost_data,
+			    num_masks
+			    + LOOP_VINFO_MASKS (loop_vinfo).rgc_vec.length (),
+			    vector_stmt, NULL, NULL, NULL_TREE, 0,
+			    vect_prologue);
+      (void) add_stmt_cost (target_cost_data,
+			    num_masks
+			    + LOOP_VINFO_MASKS (loop_vinfo).rgc_vec.length (),
+			    vector_stmt, NULL, NULL, NULL_TREE, 0, vect_body);
+
+      /* When we need saturation we need it both in the prologue and
+	 the epilogue.  */
+      if (need_saturation)
+	{
+	  (void) add_stmt_cost (target_cost_data, 1, scalar_stmt,
+				NULL, NULL, NULL_TREE, 0, vect_prologue);
+	  (void) add_stmt_cost (target_cost_data, 1, scalar_stmt,
+				NULL, NULL, NULL_TREE, 0, vect_body);
+	}
+    }
+  else if (LOOP_VINFO_FULLY_MASKED_P (loop_vinfo)
+	   && (LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo)
+	       == vect_partial_vectors_while_ult))
     {
       /* Calculate how many masks we need to generate.  */
       unsigned int num_masks = 0;
       rgroup_controls *rgm;
       unsigned int num_vectors_m1;
-      FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo), num_vectors_m1, rgm)
+      FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo).rgc_vec,
+			num_vectors_m1, rgm)
 	if (rgm->type)
 	  num_masks += num_vectors_m1 + 1;
       gcc_assert (num_masks > 0);
@@ -6647,7 +6882,7 @@ vectorize_fold_left_reduction (loop_vec_info loop_vinfo,
       gimple *new_stmt;
       tree mask = NULL_TREE;
       if (LOOP_VINFO_FULLY_MASKED_P (loop_vinfo))
-	mask = vect_get_loop_mask (gsi, masks, vec_num, vectype_in, i);
+	mask = vect_get_loop_mask (loop_vinfo, gsi, masks, vec_num, vectype_in, i);
 
       /* Handle MINUS by adding the negative.  */
       if (reduc_fn != IFN_LAST && code == MINUS_EXPR)
@@ -7960,8 +8195,8 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
 	      gcc_assert (commutative_binary_op_p (code, op.type));
 	      std::swap (vop[0], vop[1]);
 	    }
-	  tree mask = vect_get_loop_mask (gsi, masks, vec_num * ncopies,
-					  vectype_in, i);
+	  tree mask = vect_get_loop_mask (loop_vinfo, gsi, masks,
+					  vec_num * ncopies, vectype_in, i);
 	  gcall *call = gimple_build_call_internal (cond_fn, 4, mask,
 						    vop[0], vop[1], vop[0]);
 	  new_temp = make_ssa_name (vec_dest, call);
@@ -7977,8 +8212,8 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
 
 	  if (masked_loop_p && mask_by_cond_expr)
 	    {
-	      tree mask = vect_get_loop_mask (gsi, masks, vec_num * ncopies,
-					      vectype_in, i);
+	      tree mask = vect_get_loop_mask (loop_vinfo, gsi, masks,
+					      vec_num * ncopies, vectype_in, i);
 	      build_vect_cond_expr (code, vop, mask, gsi);
 	    }
 
@@ -10085,7 +10320,8 @@ vectorizable_live_operation (vec_info *vinfo,
 	     the loop mask for the final iteration.  */
 	  gcc_assert (ncopies == 1 && !slp_node);
 	  tree scalar_type = TREE_TYPE (STMT_VINFO_VECTYPE (stmt_info));
-	  tree mask = vect_get_loop_mask (gsi, &LOOP_VINFO_MASKS (loop_vinfo),
+	  tree mask = vect_get_loop_mask (loop_vinfo, gsi,
+					  &LOOP_VINFO_MASKS (loop_vinfo),
 					  1, vectype, 0);
 	  tree scalar_res = gimple_build (&stmts, CFN_EXTRACT_LAST, scalar_type,
 					  mask, vec_lhs_phi);
@@ -10338,14 +10574,6 @@ vect_record_loop_mask (loop_vec_info loop_vinfo, vec_loop_masks *masks,
 		       unsigned int nvectors, tree vectype, tree scalar_mask)
 {
   gcc_assert (nvectors != 0);
-  if (masks->length () < nvectors)
-    masks->safe_grow_cleared (nvectors, true);
-  rgroup_controls *rgm = &(*masks)[nvectors - 1];
-  /* The number of scalars per iteration and the number of vectors are
-     both compile-time constants.  */
-  unsigned int nscalars_per_iter
-    = exact_div (nvectors * TYPE_VECTOR_SUBPARTS (vectype),
-		 LOOP_VINFO_VECT_FACTOR (loop_vinfo)).to_constant ();
 
   if (scalar_mask)
     {
@@ -10353,12 +10581,7 @@ vect_record_loop_mask (loop_vec_info loop_vinfo, vec_loop_masks *masks,
       loop_vinfo->scalar_cond_masked_set.add (cond);
     }
 
-  if (rgm->max_nscalars_per_iter < nscalars_per_iter)
-    {
-      rgm->max_nscalars_per_iter = nscalars_per_iter;
-      rgm->type = truth_type_for (vectype);
-      rgm->factor = 1;
-    }
+  masks->mask_set.add (std::make_pair (vectype, nvectors));
 }
 
 /* Given a complete set of masks MASKS, extract mask number INDEX
@@ -10369,45 +10592,116 @@ vect_record_loop_mask (loop_vec_info loop_vinfo, vec_loop_masks *masks,
    arrangement.  */
 
 tree
-vect_get_loop_mask (gimple_stmt_iterator *gsi, vec_loop_masks *masks,
+vect_get_loop_mask (loop_vec_info loop_vinfo,
+		    gimple_stmt_iterator *gsi, vec_loop_masks *masks,
 		    unsigned int nvectors, tree vectype, unsigned int index)
 {
-  rgroup_controls *rgm = &(*masks)[nvectors - 1];
-  tree mask_type = rgm->type;
-
-  /* Populate the rgroup's mask array, if this is the first time we've
-     used it.  */
-  if (rgm->controls.is_empty ())
+  if (LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo)
+      == vect_partial_vectors_while_ult)
     {
-      rgm->controls.safe_grow_cleared (nvectors, true);
-      for (unsigned int i = 0; i < nvectors; ++i)
+      rgroup_controls *rgm = &(masks->rgc_vec)[nvectors - 1];
+      tree mask_type = rgm->type;
+
+      /* Populate the rgroup's mask array, if this is the first time we've
+	 used it.  */
+      if (rgm->controls.is_empty ())
 	{
-	  tree mask = make_temp_ssa_name (mask_type, NULL, "loop_mask");
-	  /* Provide a dummy definition until the real one is available.  */
-	  SSA_NAME_DEF_STMT (mask) = gimple_build_nop ();
-	  rgm->controls[i] = mask;
+	  rgm->controls.safe_grow_cleared (nvectors, true);
+	  for (unsigned int i = 0; i < nvectors; ++i)
+	    {
+	      tree mask = make_temp_ssa_name (mask_type, NULL, "loop_mask");
+	      /* Provide a dummy definition until the real one is available.  */
+	      SSA_NAME_DEF_STMT (mask) = gimple_build_nop ();
+	      rgm->controls[i] = mask;
+	    }
 	}
-    }
 
-  tree mask = rgm->controls[index];
-  if (maybe_ne (TYPE_VECTOR_SUBPARTS (mask_type),
-		TYPE_VECTOR_SUBPARTS (vectype)))
+      tree mask = rgm->controls[index];
+      if (maybe_ne (TYPE_VECTOR_SUBPARTS (mask_type),
+		    TYPE_VECTOR_SUBPARTS (vectype)))
+	{
+	  /* A loop mask for data type X can be reused for data type Y
+	     if X has N times more elements than Y and if Y's elements
+	     are N times bigger than X's.  In this case each sequence
+	     of N elements in the loop mask will be all-zero or all-one.
+	     We can then view-convert the mask so that each sequence of
+	     N elements is replaced by a single element.  */
+	  gcc_assert (multiple_p (TYPE_VECTOR_SUBPARTS (mask_type),
+				  TYPE_VECTOR_SUBPARTS (vectype)));
+	  gimple_seq seq = NULL;
+	  mask_type = truth_type_for (vectype);
+	  mask = gimple_build (&seq, VIEW_CONVERT_EXPR, mask_type, mask);
+	  if (seq)
+	    gsi_insert_seq_before (gsi, seq, GSI_SAME_STMT);
+	}
+      return mask;
+    }
+  else if (LOOP_VINFO_PARTIAL_VECTORS_STYLE (loop_vinfo)
+	   == vect_partial_vectors_avx512)
     {
-      /* A loop mask for data type X can be reused for data type Y
-	 if X has N times more elements than Y and if Y's elements
-	 are N times bigger than X's.  In this case each sequence
-	 of N elements in the loop mask will be all-zero or all-one.
-	 We can then view-convert the mask so that each sequence of
-	 N elements is replaced by a single element.  */
-      gcc_assert (multiple_p (TYPE_VECTOR_SUBPARTS (mask_type),
-			      TYPE_VECTOR_SUBPARTS (vectype)));
+      /* The number of scalars per iteration and the number of vectors are
+	 both compile-time constants.  */
+      unsigned int nscalars_per_iter
+	= exact_div (nvectors * TYPE_VECTOR_SUBPARTS (vectype),
+		     LOOP_VINFO_VECT_FACTOR (loop_vinfo)).to_constant ();
+
+      rgroup_controls *rgm = &masks->rgc_vec[nscalars_per_iter - 1];
+
+      /* The stored nV is dependent on the mask type produced.  */
+      gcc_assert (exact_div (nvectors * TYPE_VECTOR_SUBPARTS (vectype),
+			     TYPE_VECTOR_SUBPARTS (rgm->type)).to_constant ()
+		  == rgm->factor);
+      nvectors = rgm->factor;
+
+      /* Populate the rgroup's mask array, if this is the first time we've
+	 used it.  */
+      if (rgm->controls.is_empty ())
+	{
+	  rgm->controls.safe_grow_cleared (nvectors, true);
+	  for (unsigned int i = 0; i < nvectors; ++i)
+	    {
+	      tree mask = make_temp_ssa_name (rgm->type, NULL, "loop_mask");
+	      /* Provide a dummy definition until the real one is available.  */
+	      SSA_NAME_DEF_STMT (mask) = gimple_build_nop ();
+	      rgm->controls[i] = mask;
+	    }
+	}
+      if (known_eq (TYPE_VECTOR_SUBPARTS (rgm->type),
+		    TYPE_VECTOR_SUBPARTS (vectype)))
+	return rgm->controls[index];
+
+      /* Split the vector if needed.  Since we are dealing with integer mode
+	 masks with AVX512 we can operate on the integer representation
+	 performing the whole vector shifting.  */
+      unsigned HOST_WIDE_INT factor;
+      bool ok = constant_multiple_p (TYPE_VECTOR_SUBPARTS (rgm->type),
+				     TYPE_VECTOR_SUBPARTS (vectype), &factor);
+      gcc_assert (ok);
+      gcc_assert (GET_MODE_CLASS (TYPE_MODE (rgm->type)) == MODE_INT);
+      tree mask_type = truth_type_for (vectype);
+      gcc_assert (GET_MODE_CLASS (TYPE_MODE (mask_type)) == MODE_INT);
+      unsigned vi = index / factor;
+      unsigned vpart = index % factor;
+      tree vec = rgm->controls[vi];
       gimple_seq seq = NULL;
-      mask_type = truth_type_for (vectype);
-      mask = gimple_build (&seq, VIEW_CONVERT_EXPR, mask_type, mask);
+      vec = gimple_build (&seq, VIEW_CONVERT_EXPR,
+			  lang_hooks.types.type_for_mode
+				(TYPE_MODE (rgm->type), 1), vec);
+      /* For integer mode masks simply shift the right bits into position.  */
+      if (vpart != 0)
+	vec = gimple_build (&seq, RSHIFT_EXPR, TREE_TYPE (vec), vec,
+			    build_int_cst (integer_type_node,
+					   (TYPE_VECTOR_SUBPARTS (vectype)
+					    * vpart)));
+      vec = gimple_convert (&seq, lang_hooks.types.type_for_mode
+				    (TYPE_MODE (mask_type), 1), vec);
+      vec = gimple_build (&seq, VIEW_CONVERT_EXPR, mask_type, vec);
       if (seq)
 	gsi_insert_seq_before (gsi, seq, GSI_SAME_STMT);
+      return vec;
     }
-  return mask;
+  else
+    gcc_unreachable ();
 }
 
 /* Record that LOOP_VINFO would need LENS to contain a sequence of NVECTORS
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index a7acc03..ae24f3e 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -56,6 +56,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "gimple-fold.h"
 #include "regs.h"
 #include "attribs.h"
+#include "optabs-libfuncs.h"
 
 /* For lang_hooks.types.type_for_mode.  */
 #include "langhooks.h"
@@ -3692,7 +3693,8 @@ vectorizable_call (vec_info *vinfo,
 		      unsigned int vec_num = vec_oprnds0.length ();
 		      /* Always true for SLP.  */
 		      gcc_assert (ncopies == 1);
-		      vargs[varg++] = vect_get_loop_mask (gsi, masks, vec_num,
+		      vargs[varg++] = vect_get_loop_mask (loop_vinfo,
+							  gsi, masks, vec_num,
 							  vectype_out, i);
 		    }
 		  size_t k;
@@ -3733,7 +3735,8 @@ vectorizable_call (vec_info *vinfo,
 			  unsigned int vec_num = vec_oprnds0.length ();
 			  /* Always true for SLP.  */
 			  gcc_assert (ncopies == 1);
-			  tree mask = vect_get_loop_mask (gsi, masks, vec_num,
+			  tree mask = vect_get_loop_mask (loop_vinfo,
+							  gsi, masks, vec_num,
 							  vectype_out, i);
 			  vargs[mask_opno] = prepare_vec_mask
 			    (loop_vinfo, TREE_TYPE (mask), mask,
@@ -3758,7 +3761,7 @@ vectorizable_call (vec_info *vinfo,
 
 	  int varg = 0;
 	  if (masked_loop_p && reduc_idx >= 0)
-	    vargs[varg++] = vect_get_loop_mask (gsi, masks, ncopies,
+	    vargs[varg++] = vect_get_loop_mask (loop_vinfo, gsi, masks, ncopies,
 						vectype_out, j);
 	  for (i = 0; i < nargs; i++)
 	    {
@@ -3777,7 +3780,7 @@ vectorizable_call (vec_info *vinfo,
 
 	  if (mask_opno >= 0 && masked_loop_p)
 	    {
-	      tree mask = vect_get_loop_mask (gsi, masks, ncopies,
+	      tree mask = vect_get_loop_mask (loop_vinfo, gsi, masks, ncopies,
 					      vectype_out, j);
 	      vargs[mask_opno]
 		= prepare_vec_mask (loop_vinfo, TREE_TYPE (mask), mask,
@@ -5038,7 +5041,7 @@ vectorizable_conversion (vec_info *vinfo,
   tree scalar_dest;
   tree op0, op1 = NULL_TREE;
   loop_vec_info loop_vinfo = dyn_cast <loop_vec_info> (vinfo);
-  tree_code tc1;
+  tree_code tc1, tc2;
   code_helper code, code1, code2;
   code_helper codecvt1 = ERROR_MARK, codecvt2 = ERROR_MARK;
   tree new_temp;
@@ -5246,6 +5249,57 @@ vectorizable_conversion (vec_info *vinfo,
 	code1 = tc1;
 	break;
       }
+
+      /* For conversions between float and smaller integer types try whether we
+	 can use intermediate signed integer types to support the
+	 conversion.  */
+      if ((code == FLOAT_EXPR
+	   && GET_MODE_SIZE (lhs_mode) > GET_MODE_SIZE (rhs_mode))
+	  || (code == FIX_TRUNC_EXPR
+	      && GET_MODE_SIZE (rhs_mode) > GET_MODE_SIZE (lhs_mode)))
+	{
+	  bool float_expr_p = code == FLOAT_EXPR;
+	  scalar_mode imode = float_expr_p ? rhs_mode : lhs_mode;
+	  fltsz = GET_MODE_SIZE (float_expr_p ? lhs_mode : rhs_mode);
+	  code1 = float_expr_p ? code : NOP_EXPR;
+	  codecvt1 = float_expr_p ? NOP_EXPR : code;
+	  FOR_EACH_2XWIDER_MODE (rhs_mode_iter, imode)
+	    {
+	      imode = rhs_mode_iter.require ();
+	      if (GET_MODE_SIZE (imode) > fltsz)
+		break;
+
+	      cvt_type
+		= build_nonstandard_integer_type (GET_MODE_BITSIZE (imode),
+						  0);
+	      cvt_type = get_vectype_for_scalar_type (vinfo, cvt_type,
+						      slp_node);
+	      /* This should only happened for SLP as long as loop vectorizer
+		 only supports same-sized vector.  */
+	      if (cvt_type == NULL_TREE
+		  || maybe_ne (TYPE_VECTOR_SUBPARTS (cvt_type), nunits_in)
+		  || !supportable_convert_operation ((tree_code) code1,
+						     vectype_out,
+						     cvt_type, &tc1)
+		  || !supportable_convert_operation ((tree_code) codecvt1,
+						     cvt_type,
+						     vectype_in, &tc2))
+		continue;
+
+	      found_mode = true;
+	      break;
+	    }
+
+	  if (found_mode)
+	    {
+	      multi_step_cvt++;
+	      interm_types.safe_push (cvt_type);
+	      cvt_type = NULL_TREE;
+	      code1 = tc1;
+	      codecvt1 = tc2;
+	      break;
+	    }
+	}
       /* FALLTHRU */
     unsupported:
       if (dump_enabled_p ())
@@ -5510,7 +5564,18 @@ vectorizable_conversion (vec_info *vinfo,
       FOR_EACH_VEC_ELT (vec_oprnds0, i, vop0)
 	{
 	  /* Arguments are ready, create the new vector stmt.  */
-	  gimple *new_stmt = vect_gimple_build (vec_dest, code1, vop0);
+	  gimple* new_stmt;
+	  if (multi_step_cvt)
+	    {
+	      gcc_assert (multi_step_cvt == 1);
+	      new_stmt = vect_gimple_build (vec_dest, codecvt1, vop0);
+	      new_temp = make_ssa_name (vec_dest, new_stmt);
+	      gimple_assign_set_lhs (new_stmt, new_temp);
+	      vect_finish_stmt_generation (vinfo, stmt_info, new_stmt, gsi);
+	      vop0 = new_temp;
+	      vec_dest = vec_dsts[0];
+	    }
+	  new_stmt = vect_gimple_build (vec_dest, code1, vop0);
 	  new_temp = make_ssa_name (vec_dest, new_stmt);
 	  gimple_set_lhs (new_stmt, new_temp);
 	  vect_finish_stmt_generation (vinfo, stmt_info, new_stmt, gsi);
@@ -6528,8 +6593,8 @@ vectorizable_operation (vec_info *vinfo,
                              "no optab.\n");
 	  return false;
 	}
-      target_support_p = (optab_handler (optab, vec_mode)
-			  != CODE_FOR_nothing);
+      target_support_p = (optab_handler (optab, vec_mode) != CODE_FOR_nothing
+			  || optab_libfunc (optab, vec_mode));
     }
 
   bool using_emulated_vectors_p = vect_emulated_vector_p (vectype);
@@ -6823,8 +6888,8 @@ vectorizable_operation (vec_info *vinfo,
 	}
       else if (masked_loop_p && mask_out_inactive)
 	{
-	  tree mask = vect_get_loop_mask (gsi, masks, vec_num * ncopies,
-					  vectype, i);
+	  tree mask = vect_get_loop_mask (loop_vinfo, gsi, masks,
+					  vec_num * ncopies, vectype, i);
 	  auto_vec<tree> vops (5);
 	  vops.quick_push (mask);
 	  vops.quick_push (vop0);
@@ -6865,8 +6930,8 @@ vectorizable_operation (vec_info *vinfo,
 	      if (loop_vinfo->scalar_cond_masked_set.contains ({ op0,
 								 ncopies}))
 		{
-		  mask = vect_get_loop_mask (gsi, masks, vec_num * ncopies,
-					     vectype, i);
+		  mask = vect_get_loop_mask (loop_vinfo, gsi, masks,
+					     vec_num * ncopies, vectype, i);
 
 		  vop0 = prepare_vec_mask (loop_vinfo, TREE_TYPE (mask), mask,
 					   vop0, gsi);
@@ -6875,8 +6940,8 @@ vectorizable_operation (vec_info *vinfo,
 	      if (loop_vinfo->scalar_cond_masked_set.contains ({ op1,
 								 ncopies }))
 		{
-		  mask = vect_get_loop_mask (gsi, masks, vec_num * ncopies,
-					     vectype, i);
+		  mask = vect_get_loop_mask (loop_vinfo, gsi, masks,
+					     vec_num * ncopies, vectype, i);
 
 		  vop1 = prepare_vec_mask (loop_vinfo, TREE_TYPE (mask), mask,
 					   vop1, gsi);
@@ -8760,8 +8825,8 @@ vectorizable_store (vec_info *vinfo,
 
 	  tree final_mask = NULL;
 	  if (loop_masks)
-	    final_mask = vect_get_loop_mask (gsi, loop_masks, ncopies,
-					     vectype, j);
+	    final_mask = vect_get_loop_mask (loop_vinfo, gsi, loop_masks,
+					     ncopies, vectype, j);
 	  if (vec_mask)
 	    final_mask = prepare_vec_mask (loop_vinfo, mask_vectype,
 					   final_mask, vec_mask, gsi);
@@ -8814,7 +8879,7 @@ vectorizable_store (vec_info *vinfo,
 
 	      tree final_mask = NULL_TREE;
 	      if (loop_masks)
-		final_mask = vect_get_loop_mask (gsi, loop_masks,
+		final_mask = vect_get_loop_mask (loop_vinfo, gsi, loop_masks,
 						 vec_num * ncopies,
 						 vectype, vec_num * j + i);
 	      if (vec_mask)
@@ -10133,8 +10198,8 @@ vectorizable_load (vec_info *vinfo,
 
 	  tree final_mask = NULL_TREE;
 	  if (loop_masks)
-	    final_mask = vect_get_loop_mask (gsi, loop_masks, ncopies,
-					     vectype, j);
+	    final_mask = vect_get_loop_mask (loop_vinfo, gsi, loop_masks,
+					     ncopies, vectype, j);
 	  if (vec_mask)
 	    final_mask = prepare_vec_mask (loop_vinfo, mask_vectype,
 					   final_mask, vec_mask, gsi);
@@ -10184,7 +10249,7 @@ vectorizable_load (vec_info *vinfo,
 	      tree final_mask = NULL_TREE;
 	      if (loop_masks
 		  && memory_access_type != VMAT_INVARIANT)
-		final_mask = vect_get_loop_mask (gsi, loop_masks,
+		final_mask = vect_get_loop_mask (loop_vinfo, gsi, loop_masks,
 						 vec_num * ncopies,
 						 vectype, vec_num * j + i);
 	      if (vec_mask)
@@ -11208,7 +11273,7 @@ vectorizable_condition (vec_info *vinfo,
 	  if (masks)
 	    {
 	      tree loop_mask
-		= vect_get_loop_mask (gsi, masks, vec_num * ncopies,
+		= vect_get_loop_mask (loop_vinfo, gsi, masks, vec_num * ncopies,
 				      vectype, i);
 	      tree tmp2 = make_ssa_name (vec_cmp_type);
 	      gassign *g
diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h
index af25d20..a36974c 100644
--- a/gcc/tree-vectorizer.h
+++ b/gcc/tree-vectorizer.h
@@ -300,6 +300,13 @@ public:
 #define SLP_TREE_LANES(S)			 (S)->lanes
 #define SLP_TREE_CODE(S)			 (S)->code
 
+enum vect_partial_vector_style {
+    vect_partial_vectors_none,
+    vect_partial_vectors_while_ult,
+    vect_partial_vectors_avx512,
+    vect_partial_vectors_len
+};
+
 /* Key for map that records association between
    scalar conditions and corresponding loop mask, and
    is populated by vect_record_loop_mask.  */
@@ -591,12 +598,15 @@ is_a_helper <_bb_vec_info *>::test (vec_info *i)
 /* The controls (like masks or lengths) needed by rgroups with nV vectors,
    according to the description above.  */
 struct rgroup_controls {
-  /* The largest nS for all rgroups that use these controls.  */
+  /* The largest nS for all rgroups that use these controls.
+     For vect_partial_vectors_avx512 this is the constant nscalars_per_iter
+     for all members of the group.  */
   unsigned int max_nscalars_per_iter;
 
   /* For the largest nS recorded above, the loop controls divide each scalar
      into FACTOR equal-sized pieces.  This is useful if we need to split
-     element-based accesses into byte-based accesses.  */
+     element-based accesses into byte-based accesses.
+     For vect_partial_vectors_avx512 this records nV instead.  */
   unsigned int factor;
 
   /* This is a vector type with MAX_NSCALARS_PER_ITER * VF / nV elements.
@@ -605,6 +615,10 @@ struct rgroup_controls {
      specified number of elements; the type of the elements doesn't matter.  */
   tree type;
 
+  /* When there is no uniformly used LOOP_VINFO_RGROUP_COMPARE_TYPE this
+     is the rgroup specific type used.  */
+  tree compare_type;
+
   /* A vector of nV controls, in iteration order.  */
   vec<tree> controls;
 
@@ -613,7 +627,17 @@ struct rgroup_controls {
   tree bias_adjusted_ctrl;
 };
 
-typedef auto_vec<rgroup_controls> vec_loop_masks;
+struct vec_loop_masks
+{
+  bool is_empty () const { return mask_set.is_empty (); }
+
+  /* Set to record vectype, nvector pairs.  */
+  hash_set<pair_hash <nofree_ptr_hash <tree_node>,
+		      int_hash<unsigned, 0>>> mask_set;
+
+  /* rgroup_controls used for the partial vector scheme.  */
+  auto_vec<rgroup_controls> rgc_vec;
+};
 
 typedef auto_vec<rgroup_controls> vec_loop_lens;
 
@@ -741,6 +765,10 @@ public:
      LOOP_VINFO_USING_PARTIAL_VECTORS_P is true.  */
   tree rgroup_iv_type;
 
+  /* The style used for implementing partial vectors when
+     LOOP_VINFO_USING_PARTIAL_VECTORS_P is true.  */
+  vect_partial_vector_style partial_vector_style;
+
   /* Unknown DRs according to which loop was peeled.  */
   class dr_vec_info *unaligned_dr;
 
@@ -914,6 +942,7 @@ public:
 #define LOOP_VINFO_MASK_SKIP_NITERS(L)     (L)->mask_skip_niters
 #define LOOP_VINFO_RGROUP_COMPARE_TYPE(L)  (L)->rgroup_compare_type
 #define LOOP_VINFO_RGROUP_IV_TYPE(L)       (L)->rgroup_iv_type
+#define LOOP_VINFO_PARTIAL_VECTORS_STYLE(L) (L)->partial_vector_style
 #define LOOP_VINFO_PTR_MASK(L)             (L)->ptr_mask
 #define LOOP_VINFO_N_STMTS(L)		   (L)->shared->n_stmts
 #define LOOP_VINFO_LOOP_NEST(L)            (L)->shared->loop_nest
@@ -2302,7 +2331,8 @@ extern tree vect_halve_mask_nunits (tree, machine_mode);
 extern tree vect_double_mask_nunits (tree, machine_mode);
 extern void vect_record_loop_mask (loop_vec_info, vec_loop_masks *,
 				   unsigned int, tree, tree);
-extern tree vect_get_loop_mask (gimple_stmt_iterator *, vec_loop_masks *,
+extern tree vect_get_loop_mask (loop_vec_info, gimple_stmt_iterator *,
+				vec_loop_masks *,
 				unsigned int, tree, unsigned int);
 extern void vect_record_loop_len (loop_vec_info, vec_loop_lens *, unsigned int,
 				  tree, unsigned int);