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| author | Jakub Jelinek <jakub@redhat.com> | 2023-04-14 09:19:25 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2023-04-14 09:19:25 +0200 |
| commit | 2134fcfee8b338a6f10273457145fc071dc8f092 (patch) | |
| tree | 96704d59069083dbc3c203ecf2ab2e988e5af0ce /gcc | |
| parent | edc6659c97c4a747123b1150b372dc8e7a83a824 (diff) | |
| download | gcc-2134fcfee8b338a6f10273457145fc071dc8f092.zip gcc-2134fcfee8b338a6f10273457145fc071dc8f092.tar.gz gcc-2134fcfee8b338a6f10273457145fc071dc8f092.tar.bz2 | |
loop-iv: Fix up bounds computation
On Thu, Apr 13, 2023 at 06:35:07AM -0600, Jeff Law wrote:
> Bootstrap was successful with v3, but there's hundreds of testsuite failures
> due to the simplify-rtx hunk. compile/20070520-1.c for example when
> compiled with: -O3 -funroll-loops -march=rv64gc -mabi=lp64d
>
> Thursdays are my hell day. It's unlikely I'd be able to look at this at all
> today.
So, seems to me this is because loop-iv.cc asks for invalid RTL to be
simplified, it calls simplify_gen_binary (AND, SImode,
(subreg:SI (plus:DI (reg:DI 289 [ ivtmp_312 ])
(const_int 4294967295 [0xffffffff])) 0),
(const_int 4294967295 [0xffffffff]))
but 0xffffffff is not valid SImode CONST_INT, and unlike previously
we no longer on WORD_REGISTER_OPERATIONS targets which have DImode
word_mode optimize that into the op0, so the invalid constant is emitted
into the IL and checking fails.
The following patch fixes that (and we optimize that & -1 away even earlier
with that).
2023-04-14 Jakub Jelinek <jakub@redhat.com>
* loop-iv.cc (iv_number_of_iterations): Use gen_int_mode instead
of GEN_INT.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/loop-iv.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/loop-iv.cc b/gcc/loop-iv.cc index dfa4f76..6c40db9 100644 --- a/gcc/loop-iv.cc +++ b/gcc/loop-iv.cc @@ -2617,7 +2617,7 @@ iv_number_of_iterations (class loop *loop, rtx_insn *insn, rtx condition, d *= 2; size--; } - bound = GEN_INT (((uint64_t) 1 << (size - 1 ) << 1) - 1); + bound = gen_int_mode (((uint64_t) 1 << (size - 1) << 1) - 1, mode); tmp1 = lowpart_subreg (mode, iv1.base, comp_mode); tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode)); |