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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-10 07:33:25 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-10 09:08:13 +0800 |
| commit | 1fa7dde8d680f28ed66db47309ed5e8f2789054d (patch) | |
| tree | ebc037c7e8ca0b8c20578acc5a62715442d472b6 /gcc | |
| parent | 907603d4b117e82dbbde2d58a04e33f3021908e7 (diff) | |
| download | gcc-1fa7dde8d680f28ed66db47309ed5e8f2789054d.zip gcc-1fa7dde8d680f28ed66db47309ed5e8f2789054d.tar.gz gcc-1fa7dde8d680f28ed66db47309ed5e8f2789054d.tar.bz2 | |
RISC-V: Move cond_copysign from combine pattern to autovec pattern
Since cond_copysign has been support into match.pd (middle-end).
We don't need to support conditional copysign by RTL combine pass.
Instead, we can support it by direct explicit cond_copysign optab.
conditional copysign tests are already available in the testsuite.
No need to add tests.
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_copysign<mode>): Remove.
* config/riscv/autovec.md (cond_copysign<mode>): New pattern.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/autovec-opt.md | 22 | ||||
| -rw-r--r-- | gcc/config/riscv/autovec.md | 22 |
2 files changed, 22 insertions, 22 deletions
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 3c87e66..986ac6e 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -486,28 +486,6 @@ } [(set_attr "type" "vector")]) -;; Combine vfsgnj.vv + vcond_mask -(define_insn_and_split "*cond_copysign<mode>" - [(set (match_operand:V_VLSF 0 "register_operand") - (if_then_else:V_VLSF - (match_operand:<VM> 1 "register_operand") - (unspec:V_VLSF - [(match_operand:V_VLSF 2 "register_operand") - (match_operand:V_VLSF 3 "register_operand")] UNSPEC_VCOPYSIGN) - (match_operand:V_VLSF 4 "register_operand")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode); - rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; - riscv_vector::expand_cond_len_binop (icode, ops); - DONE; -} -[(set_attr "type" "vector")]) - ;; Combine vnsra + vcond_mask (define_insn_and_split "*cond_v<any_shiftrt:optab><any_extend:optab>trunc<mode>" [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand") diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 973dc4a..33722ea 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1809,6 +1809,28 @@ }) ;; ------------------------------------------------------------------------- +;; ---- [FP] Conditional copysign operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfsgnj +;; ------------------------------------------------------------------------- + +(define_expand "cond_copysign<mode>" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:<VM> 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand")] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4], + gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; + riscv_vector::expand_cond_len_binop (icode, ops); + DONE; +}) + +;; ------------------------------------------------------------------------- ;; ---- [INT] Conditional ternary operations ;; ------------------------------------------------------------------------- ;; Includes: |