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| author | prathamesh.kulkarni <prathamesh.kulkarni@linaro.org> | 2021-07-12 13:23:06 +0530 |
|---|---|---|
| committer | prathamesh.kulkarni <prathamesh.kulkarni@linaro.org> | 2021-07-12 13:23:41 +0530 |
| commit | 1e72c24d2f3b1427f5e117e371928e7af50d2036 (patch) | |
| tree | cb8d62515e6a53ea48823d7ba29d5edefd7c727c /gcc | |
| parent | 5f5fbb550af7d9d6cb56ae8f607fea0eccaa9295 (diff) | |
| download | gcc-1e72c24d2f3b1427f5e117e371928e7af50d2036.zip gcc-1e72c24d2f3b1427f5e117e371928e7af50d2036.tar.gz gcc-1e72c24d2f3b1427f5e117e371928e7af50d2036.tar.bz2 | |
arm/98435: Missed optimization in expanding vector constructor.
The patch moves vec_init pattern from neon.md to vec-common.md,
and adjusts the mode to VDQX to accomodate binary floats. Also,
the pattern is additionally gated on VALID_MVE_MODE.
gcc/ChangeLog:
PR target/98435
* config/arm/neon.md (vec_init): Move to ...
* config/arm/vec-common.md (vec_init): ... here.
Change the pattern's mode to VDQX and gate it on VALID_MVE_MODE.
gcc/testsuite/ChangeLog:
PR target/98435
* gcc.target/arm/simd/pr98435.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/neon.md | 9 | ||||
| -rw-r--r-- | gcc/config/arm/vec-common.md | 9 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/simd/pr98435.c | 15 |
3 files changed, 24 insertions, 9 deletions
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 81cc8d3..64365e0 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -458,15 +458,6 @@ [(set_attr "type" "neon_store1_one_lane_q,neon_to_gp_q")] ) -(define_expand "vec_init<mode><V_elem_l>" - [(match_operand:VDQ 0 "s_register_operand") - (match_operand 1 "" "")] - "TARGET_NEON || TARGET_HAVE_MVE" -{ - neon_expand_vector_init (operands[0], operands[1]); - DONE; -}) - ;; Doubleword and quadword arithmetic. ;; NOTE: some other instructions also support 64-bit integer diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index f90afa4..68de4f0 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -702,3 +702,12 @@ DONE; } ) + +(define_expand "vec_init<mode><V_elem_l>" + [(match_operand:VDQX 0 "s_register_operand") + (match_operand 1 "" "")] + "TARGET_NEON || (TARGET_HAVE_MVE && VALID_MVE_MODE (<MODE>mode))" +{ + neon_expand_vector_init (operands[0], operands[1]); + DONE; +}) diff --git a/gcc/testsuite/gcc.target/arm/simd/pr98435.c b/gcc/testsuite/gcc.target/arm/simd/pr98435.c new file mode 100644 index 0000000..0af8633 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/pr98435.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math" } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ +/* { dg-additional-options "-mfloat-abi=softfp -march=armv8.2-a+bf16+fp16" } */ + +#include <arm_neon.h> + +bfloat16x4_t f (bfloat16_t a) +{ + return (bfloat16x4_t) {a, a, a, a}; +} + +/* { dg-final { scan-assembler {\tvdup.16\td[0-9]+, r0} } } */ +/* { dg-final { scan-assembler {\tvmov\tr0, r1, d[0-9]+} } } */ |