sse.md (vgf2p8affineinvqb_<mode><mask_name>, [...]): Formatting fixes.

	* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
	vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>,
	vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
	vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
	vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
	vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1, vpdpbusd_<mode>,
	vpdpbusd_<mode>_mask, vpdpbusd_<mode>_maskz, vpdpbusd_<mode>_maskz_1,
	vpdpbusds_<mode>, vpdpbusds_<mode>_mask, vpdpbusds_<mode>_maskz,
	vpdpbusds_<mode>_maskz_1, vpdpwssd_<mode>, vpdpwssd_<mode>_mask,
	vpdpwssd_<mode>_maskz, vpdpwssd_<mode>_maskz_1, vpdpwssds_<mode>,
	vpdpwssds_<mode>_mask, vpdpwssds_<mode>_maskz,
	vpdpwssds_<mode>_maskz_1, vaesdec_<mode>, vaesdeclast_<mode>,
	vaesenc_<mode>, vpclmulqdq_<mode>,
	avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): Formatting fixes.

From-SVN: r256044

2 files changed, 171 insertions, 145 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c3a0ef3..18a92a9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2017-12-30  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
+	vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>,
+	vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
+	vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
+	vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
+	vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1, vpdpbusd_<mode>,
+	vpdpbusd_<mode>_mask, vpdpbusd_<mode>_maskz, vpdpbusd_<mode>_maskz_1,
+	vpdpbusds_<mode>, vpdpbusds_<mode>_mask, vpdpbusds_<mode>_maskz,
+	vpdpbusds_<mode>_maskz_1, vpdpwssd_<mode>, vpdpwssd_<mode>_mask,
+	vpdpwssd_<mode>_maskz, vpdpwssd_<mode>_maskz_1, vpdpwssds_<mode>,
+	vpdpwssds_<mode>_mask, vpdpwssds_<mode>_maskz,
+	vpdpwssds_<mode>_maskz_1, vaesdec_<mode>, vaesdeclast_<mode>,
+	vaesenc_<mode>, vpclmulqdq_<mode>,
+	avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>): Formatting fixes.
+
 2017-12-28  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	* builtins.def: (_Float<N> and _Float<N>X BUILT_IN_CEIL): Add
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index f4f68eb..105b5cf 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -20082,10 +20082,11 @@
 
 (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
-	(unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-			       (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
-			       (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
-			      UNSPEC_GF2P8AFFINEINV))]
+	(unspec:VI1_AVX512F
+	  [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+	   (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+	   (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
+	  UNSPEC_GF2P8AFFINEINV))]
   "TARGET_GFNI"
   "@
    gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
@@ -20099,10 +20100,11 @@
 
 (define_insn "vgf2p8affineqb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
-	(unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-			       (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
-			       (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
-			      UNSPEC_GF2P8AFFINE))]
+	(unspec:VI1_AVX512F
+	  [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+	   (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")
+	   (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")]
+	  UNSPEC_GF2P8AFFINE))]
   "TARGET_GFNI"
   "@
    gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
@@ -20116,9 +20118,10 @@
 
 (define_insn "vgf2p8mulb_<mode><mask_name>"
   [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v")
-	(unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
-			       (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
-			      UNSPEC_GF2P8MUL))]
+	(unspec:VI1_AVX512F
+	  [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v")
+	   (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm")]
+	  UNSPEC_GF2P8MUL))]
   "TARGET_GFNI"
   "@
    gf2p8mulb\t{%2, %0| %0, %2}
@@ -20134,9 +20137,9 @@
   [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
 	(unspec:VI248_VLBW
 	  [(match_operand:VI248_VLBW 1 "register_operand" "v")
-	(match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
-	(match_operand:SI 3 "const_0_to_255_operand" "n")
-] UNSPEC_VPSHRD))]
+	   (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
+	   (match_operand:SI 3 "const_0_to_255_operand" "n")]
+	  UNSPEC_VPSHRD))]
   "TARGET_AVX512VBMI2"
   "vpshrd<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20145,9 +20148,9 @@
   [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
 	(unspec:VI248_VLBW
 	  [(match_operand:VI248_VLBW 1 "register_operand" "v")
-	(match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
-	(match_operand:SI 3 "const_0_to_255_operand" "n")
-] UNSPEC_VPSHLD))]
+	   (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
+	   (match_operand:SI 3 "const_0_to_255_operand" "n")]
+	  UNSPEC_VPSHLD))]
   "TARGET_AVX512VBMI2"
   "vpshld<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20157,8 +20160,8 @@
 	(unspec:VI248_VLBW
 	  [(match_operand:VI248_VLBW 1 "register_operand" "0")
 	   (match_operand:VI248_VLBW 2 "register_operand" "v")
-	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
-] UNSPEC_VPSHRDV))]
+	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+	  UNSPEC_VPSHRDV))]
   "TARGET_AVX512VBMI2"
   "vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
    [(set_attr ("prefix") ("evex"))
@@ -20166,14 +20169,14 @@
 
 (define_insn "vpshrdv_<mode>_mask"
   [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
-	(vec_merge:VI248_VLBW (unspec:VI248_VLBW
-	  [(match_operand:VI248_VLBW 1 "register_operand" "0")
-	   (match_operand:VI248_VLBW 2 "register_operand" "v")
-	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPSHRDV)
-           (match_dup 1)
-           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
-)]
+	(vec_merge:VI248_VLBW
+	  (unspec:VI248_VLBW
+	    [(match_operand:VI248_VLBW 1 "register_operand" "0")
+	     (match_operand:VI248_VLBW 2 "register_operand" "v")
+	     (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPSHRDV)
+	  (match_dup 1)
+	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512VBMI2"
   "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))
@@ -20187,22 +20190,23 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VBMI2"
 {
-  emit_insn (gen_vpshrdv_<mode>_maskz_1 (
-    operands[0], operands[1], operands[2], operands[3],
-    CONST0_RTX (<MODE>mode), operands[4]));
+  emit_insn (gen_vpshrdv_<mode>_maskz_1 (operands[0], operands[1],
+					 operands[2], operands[3],
+					 CONST0_RTX (<MODE>mode),
+						     operands[4]));
   DONE;
 })
 
 (define_insn "vpshrdv_<mode>_maskz_1"
   [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
-	(vec_merge:VI248_VLBW (unspec:VI248_VLBW
-	  [(match_operand:VI248_VLBW 1 "register_operand" "0")
-	   (match_operand:VI248_VLBW 2 "register_operand" "v")
-	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPSHRDV)
+	(vec_merge:VI248_VLBW
+	  (unspec:VI248_VLBW
+	    [(match_operand:VI248_VLBW 1 "register_operand" "0")
+	     (match_operand:VI248_VLBW 2 "register_operand" "v")
+	     (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPSHRDV)
 	  (match_operand:VI248_VLBW 4 "const0_operand" "C")
-          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
-)]
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VBMI2"
   "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))
@@ -20213,8 +20217,8 @@
 	(unspec:VI248_VLBW
 	  [(match_operand:VI248_VLBW 1 "register_operand" "0")
 	   (match_operand:VI248_VLBW 2 "register_operand" "v")
-	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
-] UNSPEC_VPSHLDV))]
+	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+	  UNSPEC_VPSHLDV))]
   "TARGET_AVX512VBMI2"
   "vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
    [(set_attr ("prefix") ("evex"))
@@ -20222,14 +20226,14 @@
 
 (define_insn "vpshldv_<mode>_mask"
   [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
-	(vec_merge:VI248_VLBW (unspec:VI248_VLBW
-	  [(match_operand:VI248_VLBW 1 "register_operand" "0")
-	   (match_operand:VI248_VLBW 2 "register_operand" "v")
-	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPSHLDV)
-	   (match_dup 1)
-	   (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
-)]
+	(vec_merge:VI248_VLBW
+	  (unspec:VI248_VLBW
+	    [(match_operand:VI248_VLBW 1 "register_operand" "0")
+	     (match_operand:VI248_VLBW 2 "register_operand" "v")
+	     (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPSHLDV)
+	  (match_dup 1)
+	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512VBMI2"
   "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))
@@ -20243,22 +20247,23 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VBMI2"
 {
-  emit_insn (gen_vpshldv_<mode>_maskz_1 (
-    operands[0], operands[1], operands[2], operands[3],
-    CONST0_RTX (<MODE>mode), operands[4]));
+  emit_insn (gen_vpshldv_<mode>_maskz_1 (operands[0], operands[1],
+					 operands[2], operands[3],
+					 CONST0_RTX (<MODE>mode),
+						     operands[4]));
   DONE;
 })
 
 (define_insn "vpshldv_<mode>_maskz_1"
   [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
-	(vec_merge:VI248_VLBW (unspec:VI248_VLBW
-	  [(match_operand:VI248_VLBW 1 "register_operand" "0")
-	   (match_operand:VI248_VLBW 2 "register_operand" "v")
-	   (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPSHLDV)
+	(vec_merge:VI248_VLBW
+	  (unspec:VI248_VLBW
+	    [(match_operand:VI248_VLBW 1 "register_operand" "0")
+	     (match_operand:VI248_VLBW 2 "register_operand" "v")
+	     (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPSHLDV)
 	  (match_operand:VI248_VLBW 4 "const0_operand" "C")
-	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
-)]
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VBMI2"
   "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))
@@ -20269,22 +20274,22 @@
 	(unspec:VI4_AVX512VL
 	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
 	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-] UNSPEC_VPMADDUBSWACCD))]
+	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	  UNSPEC_VPMADDUBSWACCD))]
   "TARGET_AVX512VNNI"
   "vpdpbusd\t{%3, %2, %0|%0, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
 
 (define_insn "vpdpbusd_<mode>_mask"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDUBSWACCD)
-           (match_dup 1)
-           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
-)]
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDUBSWACCD)
+	  (match_dup 1)
+	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpbusd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20297,22 +20302,23 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VNNI"
 {
-  emit_insn (gen_vpdpbusd_<mode>_maskz_1 (
-    operands[0], operands[1], operands[2], operands[3],
-    CONST0_RTX (<MODE>mode), operands[4]));
+  emit_insn (gen_vpdpbusd_<mode>_maskz_1 (operands[0], operands[1],
+					  operands[2], operands[3],
+					  CONST0_RTX (<MODE>mode),
+						      operands[4]));
   DONE;
 })
 
 (define_insn "vpdpbusd_<mode>_maskz_1"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDUBSWACCD)
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
+	    ] UNSPEC_VPMADDUBSWACCD)
 	  (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
-          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
-)]
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20323,22 +20329,22 @@
 	(unspec:VI4_AVX512VL
 	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
 	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-] UNSPEC_VPMADDUBSWACCSSD))]
+	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	  UNSPEC_VPMADDUBSWACCSSD))]
   "TARGET_AVX512VNNI"
   "vpdpbusds\t{%3, %2, %0|%0, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
 
 (define_insn "vpdpbusds_<mode>_mask"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDUBSWACCSSD)
-           (match_dup 1)
-           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
-)]
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDUBSWACCSSD)
+	  (match_dup 1)
+	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpbusds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20351,22 +20357,23 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VNNI"
 {
-  emit_insn (gen_vpdpbusds_<mode>_maskz_1 (
-    operands[0], operands[1], operands[2], operands[3],
-    CONST0_RTX (<MODE>mode), operands[4]));
+  emit_insn (gen_vpdpbusds_<mode>_maskz_1 (operands[0], operands[1],
+					   operands[2], operands[3],
+					   CONST0_RTX (<MODE>mode),
+						       operands[4]));
   DONE;
 })
 
 (define_insn "vpdpbusds_<mode>_maskz_1"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDUBSWACCSSD)
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDUBSWACCSSD)
 	  (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
-          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
-)]
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20377,22 +20384,22 @@
 	(unspec:VI4_AVX512VL
 	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
 	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-] UNSPEC_VPMADDWDACCD))]
+	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	  UNSPEC_VPMADDWDACCD))]
   "TARGET_AVX512VNNI"
   "vpdpwssd\t{%3, %2, %0|%0, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
 
 (define_insn "vpdpwssd_<mode>_mask"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDWDACCD)
-           (match_dup 1)
-           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
-)]
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDWDACCD)
+	  (match_dup 1)
+	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpwssd\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20405,22 +20412,23 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VNNI"
 {
-  emit_insn (gen_vpdpwssd_<mode>_maskz_1 (
-    operands[0], operands[1], operands[2], operands[3],
-    CONST0_RTX (<MODE>mode), operands[4]));
+  emit_insn (gen_vpdpwssd_<mode>_maskz_1 (operands[0], operands[1],
+					  operands[2], operands[3],
+					  CONST0_RTX (<MODE>mode),
+						      operands[4]));
   DONE;
 })
 
 (define_insn "vpdpwssd_<mode>_maskz_1"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDWDACCD)
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDWDACCD)
 	  (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
-          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
-)]
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20431,22 +20439,22 @@
 	(unspec:VI4_AVX512VL
 	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
 	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-] UNSPEC_VPMADDWDACCSSD))]
+	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	  UNSPEC_VPMADDWDACCSSD))]
   "TARGET_AVX512VNNI"
   "vpdpwssds\t{%3, %2, %0|%0, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
 
 (define_insn "vpdpwssds_<mode>_mask"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDWDACCSSD)
-           (match_dup 1)
-           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
-)]
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDWDACCSSD)
+	  (match_dup 1)
+	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpwssds\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
@@ -20459,29 +20467,30 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512VNNI"
 {
-  emit_insn (gen_vpdpwssds_<mode>_maskz_1 (
-    operands[0], operands[1], operands[2], operands[3],
-    CONST0_RTX (<MODE>mode), operands[4]));
+  emit_insn (gen_vpdpwssds_<mode>_maskz_1 (operands[0], operands[1],
+					   operands[2], operands[3],
+					   CONST0_RTX (<MODE>mode),
+						       operands[4]));
   DONE;
 })
 
 (define_insn "vpdpwssds_<mode>_maskz_1"
   [(set (match_operand:VI4_AVX512VL 0 "register_operand" "=v")
-	(vec_merge:VI4_AVX512VL (unspec:VI4_AVX512VL
-	  [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
-	   (match_operand:VI4_AVX512VL 2 "register_operand" "v")
-	   (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
-	] UNSPEC_VPMADDWDACCSSD)
+	(vec_merge:VI4_AVX512VL
+	  (unspec:VI4_AVX512VL
+	    [(match_operand:VI4_AVX512VL 1 "register_operand" "0")
+	     (match_operand:VI4_AVX512VL 2 "register_operand" "v")
+	     (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
+	    UNSPEC_VPMADDWDACCSSD)
 	  (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
-          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
-)]
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
 
 (define_insn "vaesdec_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
-	  (unspec:VI1_AVX512VL_F
+	(unspec:VI1_AVX512VL_F
 	  [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
 	   (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
 	  UNSPEC_VAESDEC))]
@@ -20491,7 +20500,7 @@
 
 (define_insn "vaesdeclast_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
-	  (unspec:VI1_AVX512VL_F
+	(unspec:VI1_AVX512VL_F
 	  [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
 	   (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
 	  UNSPEC_VAESDECLAST))]
@@ -20501,7 +20510,7 @@
 
 (define_insn "vaesenc_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
-	  (unspec:VI1_AVX512VL_F
+	(unspec:VI1_AVX512VL_F
 	  [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
 	   (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
 	  UNSPEC_VAESENC))]
@@ -20511,7 +20520,7 @@
 
 (define_insn "vaesenclast_<mode>"
   [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
-	  (unspec:VI1_AVX512VL_F
+	(unspec:VI1_AVX512VL_F
 	  [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
 	   (match_operand:VI1_AVX512VL_F 2 "vector_operand" "vm")]
 	  UNSPEC_VAESENCLAST))]
@@ -20522,9 +20531,9 @@
 (define_insn "vpclmulqdq_<mode>"
   [(set (match_operand:VI8_FVL 0 "register_operand" "=v")
 	(unspec:VI8_FVL [(match_operand:VI8_FVL 1 "register_operand" "v")
-		      (match_operand:VI8_FVL 2 "vector_operand" "vm")
-		      (match_operand:SI 3 "const_0_to_255_operand" "n")]
-		     UNSPEC_VPCLMULQDQ))]
+			 (match_operand:VI8_FVL 2 "vector_operand" "vm")
+			 (match_operand:SI 3 "const_0_to_255_operand" "n")]
+			UNSPEC_VPCLMULQDQ))]
   "TARGET_VPCLMULQDQ"
   "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "mode" "DI")])
@@ -20534,7 +20543,7 @@
 	(unspec:<avx512fmaskmode>
 	  [(match_operand:VI48_AVX512VLBW 1 "register_operand" "v")
 	   (match_operand:VI48_AVX512VLBW 2 "nonimmediate_operand" "vm")]
-	UNSPEC_VPSHUFBIT))]
+	  UNSPEC_VPSHUFBIT))]
   "TARGET_AVX512BITALG"
   "vpshufbitqmb\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
   [(set_attr "prefix" "evex")