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| author | Venkataramanan Kumar <venkataramanan.kumar@amd.com> | 2016-10-11 11:49:32 +0000 |
|---|---|---|
| committer | Venkataramanan Kumar <vekumar@gcc.gnu.org> | 2016-10-11 11:49:32 +0000 |
| commit | 1d0eabee39af26125889437d3b796c6c2e68449f (patch) | |
| tree | 5b086bcd59e8f1f0e098b7ff2dbf96a1e66a0254 /gcc | |
| parent | 8e8c2744faa0cfa9697229b074b951e70bf50e1b (diff) | |
| download | gcc-1d0eabee39af26125889437d3b796c6c2e68449f.zip gcc-1d0eabee39af26125889437d3b796c6c2e68449f.tar.gz gcc-1d0eabee39af26125889437d3b796c6c2e68449f.tar.bz2 | |
Fix integer load reservation for -march=znver1
2016-10-11 Venkataramanan Kumar <Venkataramanan.kumar@amd.com>
* config/i386/znver1.md : Fix imov/imovx load type reservations.
From-SVN: r240990
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/i386/znver1.md | 8 |
2 files changed, 8 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b00cb2c..1a9cb5a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2016-10-11 Venkataramanan Kumar <Venkataramanan.kumar@amd.com> + + * config/i386/znver1.md : Fix imov/imovx load type reservations. + 2016-10-11 Eric Botcazou <ebotcazou@adacore.com> * config/sparc/sparc.opt (msubxc): New option. diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md index 7db0562..93a707a 100644 --- a/gcc/config/i386/znver1.md +++ b/gcc/config/i386/znver1.md @@ -228,18 +228,18 @@ (eq_attr "memory" "store"))) "znver1-direct,znver1-ieu,znver1-store") -(define_insn_reservation "znver1_load_imov_double_load" 6 +(define_insn_reservation "znver1_load_imov_double_load" 5 (and (eq_attr "cpu" "znver1") (and (eq_attr "znver1_decode" "double") (and (eq_attr "type" "imovx") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-ieu") + "znver1-double,znver1-load") -(define_insn_reservation "znver1_load_imov_direct_load" 5 +(define_insn_reservation "znver1_load_imov_direct_load" 4 (and (eq_attr "cpu" "znver1") (and (eq_attr "type" "imov,imovx") (eq_attr "memory" "load"))) - "znver1-direct,znver1-load,znver1-ieu") + "znver1-direct,znver1-load") ;; INTEGER/GENERAL instructions ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST |