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| author | Oleg Endo <olegendo@gcc.gnu.org> | 2014-05-03 11:50:38 +0000 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2014-05-03 11:50:38 +0000 |
| commit | 1b8da635dc58c4f2c6278fa1c18c7dad9d8fc239 (patch) | |
| tree | db13079bd93dd5aa02a6ec135f11e904f84055b5 /gcc | |
| parent | f6982a08ca633c0168be0b7700884a3ae7f161a3 (diff) | |
| download | gcc-1b8da635dc58c4f2c6278fa1c18c7dad9d8fc239.zip gcc-1b8da635dc58c4f2c6278fa1c18c7dad9d8fc239.tar.gz gcc-1b8da635dc58c4f2c6278fa1c18c7dad9d8fc239.tar.bz2 | |
sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.
* config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases.
From-SVN: r210033
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/sh/sh.h | 16 |
2 files changed, 20 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6464565..e6b5013 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2014-05-03 Oleg Endo <olegendo@gcc.gnu.org> + * config/sh/sh.h (SH_ASM_SPEC): Handle m1, m2*, m3* and m4* cases. + +2014-05-03 Oleg Endo <olegendo@gcc.gnu.org> + * config/sh/sh.h (ROUND_ADVANCE): Delete macro. (ROUND_REG, PASS_IN_REG_P): Move and rename macros to ... * config/sh/sh.c (sh_round_reg, sh_pass_in_reg_p): ... these new diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 0b6bd1b..00ee0ed 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -267,9 +267,25 @@ extern int code_for_indirect_jump_scratch; #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" #endif +/* Define which ISA type to pass to the assembler. + For SH4 we pass SH4A to allow using some instructions that are available + on some SH4 variants, but officially are part of the SH4A ISA. */ #define SH_ASM_SPEC \ "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ +%{m1:--isa=sh} \ +%{m2:--isa=sh2} \ +%{m2e:--isa=sh2e} \ +%{m3:--isa=sh3} \ +%{m3e:--isa=sh3e} \ +%{m4:--isa=sh4a} \ +%{m4-single:--isa=sh4a} \ +%{m4-single-only:--isa=sh4a} \ +%{m4-nofpu:--isa=sh4a-nofpu} \ +%{m4a:--isa=sh4a} \ +%{m4a-single:--isa=sh4a} \ +%{m4a-single-only:--isa=sh4a} \ +%{m4a-nofpu:--isa=sh4a-nofpu} \ %{m2a:--isa=sh2a} \ %{m2a-single:--isa=sh2a} \ %{m2a-single-only:--isa=sh2a} \ |