re PR target/10904 (invalid (misaligned) FP register at -O2)

	PR target/10904
	PR target/13058
	* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): New.
	Forbid mode changes from SImode for lower FP regs if ARCH64.

From-SVN: r76702

5 files changed, 82 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1e5bfa2..60d2990 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2004-01-27  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	PR target/10904
+	PR target/13058
+	* config/sparc/sparc.h (CANNOT_CHANGE_MODE_CLASS): New.
+	Forbid mode changes from SImode for lower FP regs if ARCH64.
+
 2004-01-27  J"orn Rennecke <joern.rennecke@superh.com>
 
 	* Makefile.in (bt-load.o): Depend on except.h.
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 06fd5ee..eeab3c6 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1264,6 +1264,20 @@ enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
    {-1, -1, -1, 0x20},	/* GENERAL_OR_EXTRA_FP_REGS */	\
    {-1, -1, -1, 0x3f}}	/* ALL_REGS */
 
+/* Defines invalid mode changes.  Borrowed from pa64-regs.h.
+
+   SImode loads to floating-point registers are not zero-extended.
+   The definition for LOAD_EXTEND_OP specifies that integer loads
+   narrower than BITS_PER_WORD will be zero-extended.  As a result,
+   we inhibit changes from SImode unless they are to a mode that is
+   identical in size.  */
+
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)		\
+  (TARGET_ARCH64						\
+   && (FROM) == SImode						\
+   && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)		\
+   ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
+
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 273fb42..475dd33 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2004-01-27  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* gcc.dg/20040127-1.c: New test.
+	* gcc.dg/20040127-2.c: New test.
+
 2004-01-26  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 
 	* objc.dg/stret-1.m (glob): Renamed to globa.
diff --git a/gcc/testsuite/gcc.dg/20040127-1.c b/gcc/testsuite/gcc.dg/20040127-1.c
new file mode 100644
index 0000000..0ea6062
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/20040127-1.c
@@ -0,0 +1,24 @@
+/* PR target/10904 */
+/* Origin: <kminola@eng.umd.edu> */
+
+/* Verify that the register allocator correctly aligns
+   floating-point registers on SPARC64.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+extern int foo1();
+extern int foo2();
+
+void foo(int n, int b)
+{
+  int i, a;
+
+  foo1();
+
+  a = (long)(b * ((double) 0.1));
+
+  for (i=0; i < n; i++) {
+    foo2(a);
+  }
+}
diff --git a/gcc/testsuite/gcc.dg/20040127-2.c b/gcc/testsuite/gcc.dg/20040127-2.c
new file mode 100644
index 0000000..6e56dd8
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/20040127-2.c
@@ -0,0 +1,32 @@
+/* PR target/13058 */
+/* Origin: Lloyd Parkes <lloyd@must-have-coffee.gen.nz> */
+/* Reduced testcase by  Falk Hueffner <falk@debian.org> */
+
+/* Verify that the register allocator correctly aligns
+   floating-point registers on SPARC64.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+typedef struct { int ThumbnailSize; } ImageInfo_t;
+
+double ConvertAnyFormat(void)
+{
+  return 0;
+}
+
+void ProcessExifDir(ImageInfo_t *ImageInfoP, int NumDirEntries)
+{
+  unsigned int ThumbnailSize;
+
+  for (; NumDirEntries;) {
+    Get16u();
+    switch (NumDirEntries) {
+      case 0x0201:
+      case 0x0202:
+        ThumbnailSize = ConvertAnyFormat();
+    }
+  }
+
+  ImageInfoP->ThumbnailSize = ThumbnailSize;
+}