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| author | zhengnannan <zhengnannan@huawei.com> | 2020-11-10 11:43:36 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-11-10 11:43:36 +0000 |
| commit | 1900707e56ae8c913f1d16426065e128b1abbb14 (patch) | |
| tree | 44a8e212bf62c7e19541eccc4106feac0ef9e85b /gcc | |
| parent | 9e6280242225587be256fdb80c41327736238e77 (diff) | |
| download | gcc-1900707e56ae8c913f1d16426065e128b1abbb14.zip gcc-1900707e56ae8c913f1d16426065e128b1abbb14.tar.gz gcc-1900707e56ae8c913f1d16426065e128b1abbb14.tar.bz2 | |
AArch64: Add FLAG for tbl/tbx intrinsics [PR94442]
2020-11-10 Zhiheng Xie <xiezhiheng@huawei.com>
Nannan Zheng <zhengnannan@huawei.com>
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def: Add proper FLAG
for tbl/tbx intrinsics.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 09f275c..cb05aad 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -545,28 +545,28 @@ VAR1 (BINOPP, crypto_pmull, 0, NONE, v2di) /* Implemented by aarch64_tbl3<mode>. */ - VAR1 (BINOP, tbl3, 0, ALL, v8qi) - VAR1 (BINOP, tbl3, 0, ALL, v16qi) + VAR1 (BINOP, tbl3, 0, NONE, v8qi) + VAR1 (BINOP, tbl3, 0, NONE, v16qi) /* Implemented by aarch64_qtbl3<mode>. */ - VAR1 (BINOP, qtbl3, 0, ALL, v8qi) - VAR1 (BINOP, qtbl3, 0, ALL, v16qi) + VAR1 (BINOP, qtbl3, 0, NONE, v8qi) + VAR1 (BINOP, qtbl3, 0, NONE, v16qi) /* Implemented by aarch64_qtbl4<mode>. */ - VAR1 (BINOP, qtbl4, 0, ALL, v8qi) - VAR1 (BINOP, qtbl4, 0, ALL, v16qi) + VAR1 (BINOP, qtbl4, 0, NONE, v8qi) + VAR1 (BINOP, qtbl4, 0, NONE, v16qi) /* Implemented by aarch64_tbx4<mode>. */ - VAR1 (TERNOP, tbx4, 0, ALL, v8qi) - VAR1 (TERNOP, tbx4, 0, ALL, v16qi) + VAR1 (TERNOP, tbx4, 0, NONE, v8qi) + VAR1 (TERNOP, tbx4, 0, NONE, v16qi) /* Implemented by aarch64_qtbx3<mode>. */ - VAR1 (TERNOP, qtbx3, 0, ALL, v8qi) - VAR1 (TERNOP, qtbx3, 0, ALL, v16qi) + VAR1 (TERNOP, qtbx3, 0, NONE, v8qi) + VAR1 (TERNOP, qtbx3, 0, NONE, v16qi) /* Implemented by aarch64_qtbx4<mode>. */ - VAR1 (TERNOP, qtbx4, 0, ALL, v8qi) - VAR1 (TERNOP, qtbx4, 0, ALL, v16qi) + VAR1 (TERNOP, qtbx4, 0, NONE, v8qi) + VAR1 (TERNOP, qtbx4, 0, NONE, v16qi) /* Builtins for ARMv8.1-A Adv.SIMD instructions. */ |