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| author | Segher Boessenkool <segher@kernel.crashing.org> | 2017-11-03 15:09:10 +0100 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2017-11-03 15:09:10 +0100 |
| commit | 187bd6cd5e46e3b51aecd537582b146ccb6f21bd (patch) | |
| tree | 403297c8347a87832d7bb492a995b7d645e19a29 /gcc | |
| parent | b15a4bc97246f8d6add88f26807291e0a4fe2711 (diff) | |
| download | gcc-187bd6cd5e46e3b51aecd537582b146ccb6f21bd.zip gcc-187bd6cd5e46e3b51aecd537582b146ccb6f21bd.tar.gz gcc-187bd6cd5e46e3b51aecd537582b146ccb6f21bd.tar.bz2 | |
rs6000: Improve *lt0 patterns
The rs6000 port currently has an *lt0_disi define_insn, setting the DI
result to whether the SI argument is negative or not. It turns out the
generic optimisers cannot always figure out in the other cases either
that this is just a shift for us. This patch adds patterns for all
four SI/DI combinations.
* config/rs6000/rs6000.md (*lt0_disi): Delete.
(*lt0_<mode>di, *lt0_<mode>si): New.
From-SVN: r254374
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 16 |
2 files changed, 17 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e8ebe14..561e3da 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-11-03 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (*lt0_disi): Delete. + (*lt0_<mode>di, *lt0_<mode>si): New. + +2017-11-03 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/rs6000.md (move_from_CR_ov_bit): Change condition to TARGET_PAIRED_FLOAT. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3ad702d..2ef028f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3829,11 +3829,19 @@ ; Special case for less-than-0. We can do it with just one machine ; instruction, but the generic optimizers do not realise it is cheap. -(define_insn "*lt0_disi" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (lt:DI (match_operand:SI 1 "gpc_reg_operand" "r") - (const_int 0)))] +(define_insn "*lt0_<mode>di" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lt:GPR (match_operand:DI 1 "gpc_reg_operand" "r") + (const_int 0)))] "TARGET_POWERPC64" + "srdi %0,%1,63" + [(set_attr "type" "shift")]) + +(define_insn "*lt0_<mode>si" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lt:GPR (match_operand:SI 1 "gpc_reg_operand" "r") + (const_int 0)))] + "" "rlwinm %0,%1,1,31,31" [(set_attr "type" "shift")]) |