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| author | Roger Sayle <roger@nextmovesoftware.com> | 2023-07-31 08:08:11 +0100 |
|---|---|---|
| committer | Roger Sayle <roger@nextmovesoftware.com> | 2023-07-31 08:08:11 +0100 |
| commit | 129feec0ba4f8ce74edf1fdf7da37b54968d3d37 (patch) | |
| tree | a5fdf14484cfaf7d7ab845e1378ab32dd700cdd9 /gcc | |
| parent | 1349f530753be963043d77c1d51da161133d5afe (diff) | |
| download | gcc-129feec0ba4f8ce74edf1fdf7da37b54968d3d37.zip gcc-129feec0ba4f8ce74edf1fdf7da37b54968d3d37.tar.gz gcc-129feec0ba4f8ce74edf1fdf7da37b54968d3d37.tar.bz2 | |
[Committed] PR target/110843: Check TARGET_AVX512VL for V2DI rotates in STV.
This patch resolves PR target/110843, an ICE caused by my enhancement to
support AVX512 DImode and SImode rotates in the scalar-to-vector (STV) pass.
Although the vprotate instructions are available on all TARGET_AVX512F
microarchitectures, the V2DI and V4SI variants are only available on the
TARGET_AVX512VL subset, leading to problems when command line options
enable AVX512 (i.e. AVX512F) but not the required AVX512VL functionality.
The simple fix is to update/correct the target checks.
2023-07-31 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR target/110843
* config/i386/i386-features.cc (compute_convert_gain): Check
TARGET_AVX512VL (not TARGET_AVX512F) when considering V2DImode
and V4SImode rotates in STV.
(general_scalar_chain::convert_rotate): Likewise.
gcc/testsuite/ChangeLog
PR target/110843
* gcc.target/i386/pr110843.c: New test case.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386-features.cc | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr110843.c | 20 |
2 files changed, 23 insertions, 3 deletions
diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index 6da8395..cead397 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -587,7 +587,7 @@ general_scalar_chain::compute_convert_gain () case ROTATE: case ROTATERT: igain += m * ix86_cost->shift_const; - if (TARGET_AVX512F) + if (TARGET_AVX512VL) igain -= ix86_cost->sse_op; else if (smode == DImode) { @@ -1230,7 +1230,7 @@ general_scalar_chain::convert_rotate (enum rtx_code code, rtx op0, rtx op1, emit_insn_before (pat, insn); result = gen_lowpart (V2DImode, tmp1); } - else if (TARGET_AVX512F) + else if (TARGET_AVX512VL) result = simplify_gen_binary (code, V2DImode, op0, op1); else if (bits == 16 || bits == 48) { @@ -1276,7 +1276,7 @@ general_scalar_chain::convert_rotate (enum rtx_code code, rtx op0, rtx op1, emit_insn_before (pat, insn); result = gen_lowpart (V4SImode, tmp1); } - else if (TARGET_AVX512F) + else if (TARGET_AVX512VL) result = simplify_gen_binary (code, V4SImode, op0, op1); else { diff --git a/gcc/testsuite/gcc.target/i386/pr110843.c b/gcc/testsuite/gcc.target/i386/pr110843.c new file mode 100644 index 0000000..b9bcddb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr110843.c @@ -0,0 +1,20 @@ +/* PR target/110843 */ +/* derived from gcc.target/i386/pr70007.c */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-Os -mavx512ifma -Wno-psabi" } */ + +typedef unsigned short v32u16 __attribute__ ((vector_size (32))); +typedef unsigned long long v32u64 __attribute__ ((vector_size (32))); +typedef unsigned __int128 u128; +typedef unsigned __int128 v32u128 __attribute__ ((vector_size (32))); + +u128 foo (v32u16 v32u16_0, v32u64 v32u64_0, v32u64 v32u64_1) +{ + do { + v32u16_0[13] |= v32u64_1[3] = (v32u64_1[3] >> 19) | (v32u64_1[3] << 45); + v32u64_1 %= ~v32u64_1; + v32u64_0 *= (v32u64) v32u16_0; + } while (v32u64_0[0]); + return v32u64_1[3]; +} + |