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| author | Richard Henderson <rth@cygnus.com> | 1998-03-18 08:21:14 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 1998-03-18 08:21:14 -0800 |
| commit | 10a25232267840b3347f75de6bac8f41c7052037 (patch) | |
| tree | 571569c3131dd4cd811e5ccce9a2def713ad3463 /gcc | |
| parent | 99d1a24c9b2e72fe14e20a783dc12bbd6a48d315 (diff) | |
| download | gcc-10a25232267840b3347f75de6bac8f41c7052037.zip gcc-10a25232267840b3347f75de6bac8f41c7052037.tar.gz gcc-10a25232267840b3347f75de6bac8f41c7052037.tar.bz2 | |
alpha.md (extzv): Don't reject register operands.
* alpha.md (extzv): Don't reject register operands. Fix
mode of operand 1.
From-SVN: r18676
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 27 |
2 files changed, 18 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2cfa62f..d42a14c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Wed Mar 18 16:20:30 1998 Richard Henderson <rth@cygnus.com> + + * alpha.md (extzv): Don't reject register operands. Fix + mode of operand 1. + Wed Mar 18 16:14:23 1998 Richard Henderson <rth@cygnus.com> * dbxout.c (dbxout_function_end): Fix last change. The correct diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 7c3ec52..ced647b 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -4873,28 +4873,27 @@ (define_expand "extzv" [(set (match_operand:DI 0 "register_operand" "") - (zero_extract:DI (match_operand:QI 1 "memory_operand" "") + (zero_extract:DI (match_operand:DI 1 "memory_operand" "") (match_operand:DI 2 "immediate_operand" "") (match_operand:DI 3 "immediate_operand" "")))] "" " { - /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ - if (INTVAL (operands[3]) % 8 != 0 - || (INTVAL (operands[2]) != 16 - && INTVAL (operands[2]) != 32 - && INTVAL (operands[2]) != 64)) + /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ + if (INTVAL (operands[2]) % 8 != 0 || INTVAL (operands[3]) % 8 != 0) FAIL; - /* From mips.md: extract_bit_field doesn't verify that our source - matches the predicate, so we force it to be a MEM here. */ - if (GET_CODE (operands[1]) != MEM) - FAIL; + if (GET_CODE (operands[1]) == MEM) + { + /* Fail 8 bit fields, falling back on a simple byte load. */ + if (INTVAL (operands[2]) == 8) + FAIL; - alpha_expand_unaligned_load (operands[0], operands[1], - INTVAL (operands[2]) / 8, - INTVAL (operands[3]) / 8, 0); - DONE; + alpha_expand_unaligned_load (operands[0], operands[1], + INTVAL (operands[2]) / 8, + INTVAL (operands[3]) / 8, 0); + DONE; + } }") (define_expand "insv" |