diff options
| author | Michael Meissner <meissner@gcc.gnu.org> | 1996-01-15 21:53:30 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1996-01-15 21:53:30 +0000 |
| commit | 0f6453027705a3eeafe0a6b521624a75d7a7f58b (patch) | |
| tree | 0668811a125606741b42987607beb4276bcf0d4c /gcc | |
| parent | 968ad7cfe21dc8a7b57fe5f23a95dd7fb2ee582a (diff) | |
| download | gcc-0f6453027705a3eeafe0a6b521624a75d7a7f58b.zip gcc-0f6453027705a3eeafe0a6b521624a75d7a7f58b.tar.gz gcc-0f6453027705a3eeafe0a6b521624a75d7a7f58b.tar.bz2 | |
Fix little endian adddi3/subdi3
From-SVN: r10997
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 40 |
1 files changed, 19 insertions, 21 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b2dec1a..8920c8a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3623,11 +3623,17 @@ (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] "! TARGET_POWERPC64" - "@ - {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 - {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1 - {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2 - {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1" + "* +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[2])) != CONST_INT + ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" + : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; + else + return (GET_CODE (operands[2])) != CONST_INT + ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" + : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; +}" [(set_attr "length" "8")]) (define_insn "subddi3" @@ -3635,24 +3641,16 @@ (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] "TARGET_POWER && ! TARGET_POWERPC64" - "@ - {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 - {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2 - {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 - {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1 - {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2" - [(set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r") - (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,0,r") - (match_operand:DI 2 "gpc_reg_operand" "r,r,0")))] - "! TARGET_POWER && ! TARGET_POWERPC64" "* { - return (WORDS_BIG_ENDIAN) - ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" - : \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"; + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[1]) != CONST_INT) + ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" + : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; + else + return (GET_CODE (operands[1]) != CONST_INT) + ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" + : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; }" [(set_attr "length" "8")]) |