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| author | Walter Lee <walt@tilera.com> | 2016-11-23 04:33:43 +0000 |
|---|---|---|
| committer | Walter Lee <walt@gcc.gnu.org> | 2016-11-23 04:33:43 +0000 |
| commit | 0f525c3e59929888046e686ec8375514b5c381f5 (patch) | |
| tree | 410cb308cfc4126288617deeef8a6e72cf1e25e6 /gcc | |
| parent | 3135d8fe8a2ac2a88c9681494c6f1ea68d3ae614 (diff) | |
| download | gcc-0f525c3e59929888046e686ec8375514b5c381f5.zip gcc-0f525c3e59929888046e686ec8375514b5c381f5.tar.gz gcc-0f525c3e59929888046e686ec8375514b5c381f5.tar.bz2 | |
TILE-Gx...
TILE-Gx: fixes the zero_extract/sign_extract patterns so that they
properly handle the case when pos + size > number of bits in a word.
* config/tilegx/tilegx.md (*zero_extract): Use
define_insn_and_split instead of define_insn; Handle pos +
size > 64.
(*sign_extract): Likewise.
From-SVN: r242734
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/tilegx/tilegx.md | 28 |
2 files changed, 33 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8d11c29..a7a776e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-11-22 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx.md (*zero_extract): Use + define_insn_and_split instead of define_insn; Handle pos + size > + 64. + (*sign_extract): Likewise. + 2016-11-22 Marek Polacek <polacek@redhat.com> PR tree-optimization/78455 diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 55c345c..3ad5a87 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1237,7 +1237,7 @@ "ld<four_s_if_si>_tls\t%0, %1, tls_ie_load(%2)" [(set_attr "type" "X1_2cycle")]) -(define_insn "*zero_extract<mode>" +(define_insn_and_split "*zero_extract<mode>" [(set (match_operand:I48MODE 0 "register_operand" "=r") (zero_extract:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "r") @@ -1245,6 +1245,18 @@ (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))] "" "bfextu\t%0, %r1, %3, %3+%2-1" + "&& reload_completed" + [(set (match_dup 0) (zero_extract:I48MODE + (match_dup 1) + (match_dup 2) + (match_dup 3)))] +{ + HOST_WIDE_INT bit_width = INTVAL (operands[2]); + HOST_WIDE_INT bit_offset = INTVAL (operands[3]); + + if (bit_offset + bit_width > 64) + operands[2] = GEN_INT (64 - bit_offset); +} [(set_attr "type" "X0")]) (define_insn "*sign_extract_low32" @@ -1256,7 +1268,7 @@ "INTVAL (operands[3]) == 0 && INTVAL (operands[2]) == 32" "addxi\t%0, %r1, 0") -(define_insn "*sign_extract" +(define_insn_and_split "*sign_extract" [(set (match_operand:I48MODE 0 "register_operand" "=r") (sign_extract:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "r") @@ -1264,6 +1276,18 @@ (match_operand:I48MODE 3 "u6bit_cint_operand" "n")))] "" "bfexts\t%0, %r1, %3, %3+%2-1" + "&& reload_completed" + [(set (match_dup 0) (sign_extract:I48MODE + (match_dup 1) + (match_dup 2) + (match_dup 3)))] +{ + HOST_WIDE_INT bit_width = INTVAL (operands[2]); + HOST_WIDE_INT bit_offset = INTVAL (operands[3]); + + if (bit_offset + bit_width > 64) + operands[2] = GEN_INT (64 - bit_offset); +} [(set_attr "type" "X0")]) |