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| author | Andrew Pinski <pinskia@gmail.com> | 2011-04-01 11:36:17 -0700 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2011-04-01 18:36:17 +0000 |
| commit | 08ae38e0f33eb78917983e36e335586518b07235 (patch) | |
| tree | b76accc9ba4ae8403021017ae17791498e86dac7 /gcc | |
| parent | bdb0b0f61c5af3ae2d7dbdeca6089bd6ad79d50e (diff) | |
| download | gcc-08ae38e0f33eb78917983e36e335586518b07235.zip gcc-08ae38e0f33eb78917983e36e335586518b07235.tar.gz gcc-08ae38e0f33eb78917983e36e335586518b07235.tar.bz2 | |
Fix 48262
Co-Authored-By: Michael Meissner <meissner@linux.vnet.ibm.com>
From-SVN: r171847
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 13 | ||||
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 16 | ||||
| -rw-r--r-- | gcc/config/rs6000/vector.md | 4 |
3 files changed, 23 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bfaf388..09091ea 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2011-04-01 Andrew Pinski <pinskia@gmail.com> + Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/48262 + * config/rs6000/vector.md (movmisalign<mode>): Allow for memory + operands, as per the specifications. + + * config/rs6000/altivec.md (vec_extract_evenv4si): Correct modes. + (vec_extract_evenv4sf): Ditto. + (vec_extract_evenv8hi): Ditto. + (vec_extract_evenv16qi): Ditto. + (vec_extract_oddv4si): Ditto. + 2011-03-31 Mark Wielaard <mjw@redhat.com> * dwarf2out.c (dwarf2out_finish): Don't add low_pc and/or diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index d507b86..5e803f6 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -2422,7 +2422,7 @@ (define_expand "vec_extract_evenv4si" [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") (match_operand:V4SI 2 "register_operand" "")] UNSPEC_EXTEVEN_V4SI))] "TARGET_ALTIVEC" @@ -2455,7 +2455,7 @@ (define_expand "vec_extract_evenv4sf" [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") (match_operand:V4SF 2 "register_operand" "")] UNSPEC_EXTEVEN_V4SF))] "TARGET_ALTIVEC" @@ -2487,7 +2487,7 @@ }") (define_expand "vec_extract_evenv8hi" - [(set (match_operand:V4SI 0 "register_operand" "") + [(set (match_operand:V8HI 0 "register_operand" "") (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "") (match_operand:V8HI 2 "register_operand" "")] UNSPEC_EXTEVEN_V8HI))] @@ -2520,9 +2520,9 @@ }") (define_expand "vec_extract_evenv16qi" - [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "")] + [(set (match_operand:V16QI 0 "register_operand" "") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "") + (match_operand:V16QI 2 "register_operand" "")] UNSPEC_EXTEVEN_V16QI))] "TARGET_ALTIVEC" " @@ -2554,7 +2554,7 @@ (define_expand "vec_extract_oddv4si" [(set (match_operand:V4SI 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "") (match_operand:V4SI 2 "register_operand" "")] UNSPEC_EXTODD_V4SI))] "TARGET_ALTIVEC" @@ -2587,7 +2587,7 @@ (define_expand "vec_extract_oddv4sf" [(set (match_operand:V4SF 0 "register_operand" "") - (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "") (match_operand:V4SF 2 "register_operand" "")] UNSPEC_EXTODD_V4SF))] "TARGET_ALTIVEC" diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index c5a7870..a3a8e12 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -871,8 +871,8 @@ ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned ;; since the load already handles it. (define_expand "movmisalign<mode>" - [(set (match_operand:VEC_N 0 "vfloat_operand" "") - (match_operand:VEC_N 1 "vfloat_operand" ""))] + [(set (match_operand:VEC_N 0 "nonimmediate_operand" "") + (match_operand:VEC_N 1 "any_operand" ""))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN" "") |