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| author | Christophe Lyon <christophe.lyon@linaro.org> | 2015-01-20 23:25:37 +0000 |
|---|---|---|
| committer | Christophe Lyon <clyon@gcc.gnu.org> | 2015-01-21 00:25:37 +0100 |
| commit | 07cdd01e28c7f49472c253693a0cd8b212966061 (patch) | |
| tree | b0240c336272939192aab002869a6bf7690adb1c /gcc | |
| parent | e20a3d0f5c08e73aab8f0ab7b06bae4cf7ed2eb4 (diff) | |
| download | gcc-07cdd01e28c7f49472c253693a0cd8b212966061.zip gcc-07cdd01e28c7f49472c253693a0cd8b212966061.tar.gz gcc-07cdd01e28c7f49472c253693a0cd8b212966061.tar.bz2 | |
[ARM/AArch64][testsuite] Add vmlal_n and vmlsl_n tests.
2015-01-20 Christophe Lyon <christophe.lyon@linaro.org>
* gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file.
* gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file.
From-SVN: r219922
Diffstat (limited to 'gcc')
4 files changed, 99 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4f56521..3157bc0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2015-01-20 Christophe Lyon <christophe.lyon@linaro.org> + * gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc: New file. + * gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c: New file. + * gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c: New file. + +2015-01-20 Christophe Lyon <christophe.lyon@linaro.org> + * gcc.target/aarch64/advsimd-intrinsics/vmlXl_lane.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vmlal_lane.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vmlsl_lane.c: New file. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc new file mode 100644 index 0000000..a968584 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_n.inc @@ -0,0 +1,61 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* vector_res = vmlxl_n(vector, vector2, val), + then store the result. */ +#define TEST_VMLXL_N1(INSN, T1, T2, W, W2, N, V) \ + VECT_VAR(vector_res, T1, W, N) = INSN##_##T2##W2(VECT_VAR(vector, T1, W, N), \ + VECT_VAR(vector2, T1, W2, N), \ + V); \ + vst1q_##T2##W(VECT_VAR(result, T1, W, N), VECT_VAR(vector_res, T1, W, N)) + +#define TEST_VMLXL_N(INSN, T1, T2, W, W2, N, V) \ + TEST_VMLXL_N1(INSN, T1, T2, W, W2, N, V) + + DECL_VARIABLE(vector, int, 32, 4); + DECL_VARIABLE(vector2, int, 16, 4); + DECL_VARIABLE(vector_res, int, 32, 4); + + DECL_VARIABLE(vector, int, 64, 2); + DECL_VARIABLE(vector2, int, 32, 2); + DECL_VARIABLE(vector_res, int, 64, 2); + + DECL_VARIABLE(vector, uint, 32, 4); + DECL_VARIABLE(vector2, uint, 16, 4); + DECL_VARIABLE(vector_res, uint, 32, 4); + + DECL_VARIABLE(vector, uint, 64, 2); + DECL_VARIABLE(vector2, uint, 32, 2); + DECL_VARIABLE(vector_res, uint, 64, 2); + + clean_results (); + + VLOAD(vector, buffer, q, int, s, 32, 4); + VLOAD(vector, buffer, q, int, s, 64, 2); + VLOAD(vector, buffer, q, uint, u, 32, 4); + VLOAD(vector, buffer, q, uint, u, 64, 2); + + VDUP(vector2, , int, s, 16, 4, 0x55); + VDUP(vector2, , int, s, 32, 2, 0x55); + VDUP(vector2, , uint, u, 16, 4, 0x55); + VDUP(vector2, , uint, u, 32, 2, 0x55); + + /* Choose multiplier arbitrarily. */ + TEST_VMLXL_N(INSN_NAME, int, s, 32, 16, 4, 0x11); + TEST_VMLXL_N(INSN_NAME, int, s, 64, 32, 2, 0x22); + TEST_VMLXL_N(INSN_NAME, uint, u, 32, 16, 4, 0x33); + TEST_VMLXL_N(INSN_NAME, uint, u, 64, 32, 2, 0x33); + + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c new file mode 100644 index 0000000..118068c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_n.c @@ -0,0 +1,14 @@ +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmlal_n +#define TEST_MSG "VMLAL_N" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0x595, 0x596, 0x597, 0x598 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0xb3a, 0xb3b }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0x10df, 0x10e0 }; + +#include "vmlXl_n.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c new file mode 100644 index 0000000..a26c69f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_n.c @@ -0,0 +1,18 @@ +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#define INSN_NAME vmlsl_n +#define TEST_MSG "VMLSL_N" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffa4b, 0xfffffa4c, + 0xfffffa4d, 0xfffffa4e }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffff4a6, + 0xfffffffffffff4a7 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffef01, 0xffffef02, + 0xffffef03, 0xffffef04 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xffffffffffffef01, + 0xffffffffffffef02 }; + +#include "vmlXl_n.inc" |