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| author | Michael Meissner <meissner@gcc.gnu.org> | 1995-05-20 21:22:28 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1995-05-20 21:22:28 +0000 |
| commit | 034c1be0fdf231cecab4424e638060370b0cd7a1 (patch) | |
| tree | 4d1a03dd1663b5b46539f3f7e410aca9bfb9e7b4 /gcc | |
| parent | d030f4b2d7c66c17ebf516b22d01cce27427670e (diff) | |
| download | gcc-034c1be0fdf231cecab4424e638060370b0cd7a1.zip gcc-034c1be0fdf231cecab4424e638060370b0cd7a1.tar.gz gcc-034c1be0fdf231cecab4424e638060370b0cd7a1.tar.bz2 | |
Do not do insv/extz on 1/2 byte structures
From-SVN: r9758
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f44883f..7e5f374 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1929,7 +1929,23 @@ ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. -(define_insn "insv" +(define_expand "insv" + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") + (match_operand:SI 1 "const_int_operand" "i") + (match_operand:SI 2 "const_int_operand" "i")) + (match_operand:SI 3 "gpc_reg_operand" "r"))] + "" + " +{ + /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since + the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the + compiler if the address of the structure is taken later. */ + if (GET_CODE (operands[0]) == SUBREG + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) + FAIL; +}") + +(define_insn "" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) @@ -2021,7 +2037,23 @@ return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\"; }") -(define_insn "extzv" +(define_expand "extzv" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i") + (match_operand:SI 3 "const_int_operand" "i")))] + "" + " +{ + /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since + the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the + compiler if the address of the structure is taken later. */ + if (GET_CODE (operands[0]) == SUBREG + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) + FAIL; +}") + +(define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") |