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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-09-20 16:22:24 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-09-20 16:22:24 +0000 |
| commit | 00cc7cbfb534eca268ddd53a113636b5cd64948c (patch) | |
| tree | 9a71906cf48d36954fc14b7e6540e66ca6a416d6 /gcc | |
| parent | c55b54403ea3a3e781eaf14d3057d103bd77ade3 (diff) | |
| download | gcc-00cc7cbfb534eca268ddd53a113636b5cd64948c.zip gcc-00cc7cbfb534eca268ddd53a113636b5cd64948c.tar.gz gcc-00cc7cbfb534eca268ddd53a113636b5cd64948c.tar.bz2 | |
rs6000.c (rs6000_expand_vector_init): For V4SF inits on power8 and above, use the VMRGEW instruction instead of a permute.
2016-09-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_init): For V4SF
inits on power8 and above, use the VMRGEW instruction instead of a
permute.
* config/rs6000/altivec.md (UNSPEC_VMRGEW_DIRECT): New unspec.
(p8_vmrgew_v4sf_direct): New VMRGEW insn for V4SF floating
initialization.
From-SVN: r240272
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 25 |
3 files changed, 40 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9bab58d7..92370d1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-09-20 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/rs6000.c (rs6000_expand_vector_init): For V4SF + inits on power8 and above, use the VMRGEW instruction instead of a + permute. + + * config/rs6000/altivec.md (UNSPEC_VMRGEW_DIRECT): New unspec. + (p8_vmrgew_v4sf_direct): New VMRGEW insn for V4SF floating + initialization. + 2016-09-20 Tamar Christina <tamar.christina@arm.com> * config/aarch64/arm_neon.h diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 857f257..541c449 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -141,6 +141,7 @@ UNSPEC_VMRGH_DIRECT UNSPEC_VMRGL_DIRECT UNSPEC_VSPLT_DIRECT + UNSPEC_VMRGEW_DIRECT UNSPEC_VSUMSWS_DIRECT UNSPEC_VADDCUQ UNSPEC_VADDEUQM @@ -1340,6 +1341,15 @@ } [(set_attr "type" "vecperm")]) +(define_insn "p8_vmrgew_v4sf_direct" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] + UNSPEC_VMRGEW_DIRECT))] + "TARGET_P8_VECTOR" + "vmrgew %0,%1,%2" + [(set_attr "type" "vecperm")]) + (define_expand "vec_widen_umult_even_v16qi" [(use (match_operand:V8HI 0 "register_operand" "")) (use (match_operand:V16QI 1 "register_operand" "")) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ed24d96..7dd7ee5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6821,11 +6821,26 @@ rs6000_expand_vector_init (rtx target, rtx vals) rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2)); rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3)); - emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1)); - emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3)); - emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even)); - emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd)); - rs6000_expand_extract_even (target, flt_even, flt_odd); + /* Use VMRGEW if we can instead of doing a permute. */ + if (TARGET_P8_VECTOR) + { + emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2)); + emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3)); + emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even)); + emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd)); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd)); + else + emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even)); + } + else + { + emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1)); + emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3)); + emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even)); + emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd)); + rs6000_expand_extract_even (target, flt_even, flt_odd); + } } return; } |