mn10300.md (movXX patterns): Make sure the destination is an ADDRESS_REG when...

        * mn10300.md (movXX patterns): Make sure the destination is an
        ADDRESS_REG when substituting "zero_areg" for (const_int 0).
        (logical patterns): Split into expanders + patterns
        (zero and sign extension patterns): Similarly.
        (shift patterns): Similarly.

From-SVN: r21214

2 files changed, 110 insertions, 15 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a630afd..0162da6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+Thu Jul 16 14:48:47 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.md (movXX patterns): Make sure the destination is an
+	ADDRESS_REG when substituting "zero_areg" for (const_int 0).
+	(logical patterns): Split into expanders + patterns
+	(zero and sign extension patterns): Similarly.
+	(shift patterns): Similarly.
+
 Thu Jul 16 01:17:44 1998  Richard Henderson  <rth@cygnus.com>
 
 	* loop.c (emit_iv_add_mult): Scan the entire insn list generated
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index 6b56fd7..01cec17 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -410,7 +410,9 @@
 	      {
 		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
 		  output_asm_insn (\"clr %L0\", operands);
-	        else if (zero_areg)
+	        else if (zero_areg
+			 && (REGNO_REG_CLASS (REGNO (operands[0]))
+			     == ADDRESS_REGS))
 		  {
 		    rtx xoperands[2];
 
@@ -433,7 +435,9 @@
 	      {
 		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
 		  output_asm_insn (\"clr %H0\", operands);
-		else if (zero_areg)
+	        else if (zero_areg
+			 && (REGNO_REG_CLASS (REGNO (operands[0]))
+			     == ADDRESS_REGS))
 		  {
 		    rtx xoperands[2];
 
@@ -571,7 +575,9 @@
 	      {
 		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
 		  output_asm_insn (\"clr %L0\", operands);
-	        else if (zero_areg)
+	        else if (zero_areg
+			 && (REGNO_REG_CLASS (REGNO (operands[0]))
+			     == ADDRESS_REGS))
 		  {
 		    rtx xoperands[2];
 
@@ -594,7 +600,9 @@
 	      {
 		if (REGNO_REG_CLASS (REGNO (operands[0])) == DATA_REGS)
 		  output_asm_insn (\"clr %H0\", operands);
-		else if (zero_areg)
+	        else if (zero_areg
+			 && (REGNO_REG_CLASS (REGNO (operands[0]))
+			     == ADDRESS_REGS))
 		  {
 		    rtx xoperands[2];
 
@@ -821,7 +829,14 @@
 ;; AND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "andsi3"
+(define_expand "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx,dx")
 	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
 		(match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
@@ -856,7 +871,14 @@
 ;; OR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "iorsi3"
+(define_expand "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ior:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(ior:SI (match_operand:SI 1 "register_operand" "%0")
 		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
@@ -868,7 +890,14 @@
 ;; XOR INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "xorsi3"
+(define_expand "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(xor:SI (match_operand:SI 1 "register_operand" "%0")
 		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
@@ -880,7 +909,13 @@
 ;; NOT INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "one_cmplsi2"
+(define_expand "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(not:SI (match_operand:SI 1 "register_operand" "")))]
+  ""
+  "")
+ 
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(not:SI (match_operand:SI 1 "register_operand" "0")))]
   ""
@@ -1271,7 +1306,14 @@
 ;; EXTEND INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "zero_extendqisi2"
+(define_expand "zero_extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(zero_extend:SI
+	 (match_operand:QI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
 	(zero_extend:SI
 	 (match_operand:QI 1 "general_operand" "0,d,m")))]
@@ -1282,7 +1324,14 @@
   movbu %1,%0"
   [(set_attr "cc" "none_0hit")])
 
-(define_insn "zero_extendhisi2"
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(zero_extend:SI
+	 (match_operand:HI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
 	(zero_extend:SI
 	 (match_operand:HI 1 "general_operand" "0,dx,m")))]
@@ -1295,7 +1344,14 @@
 
 ;;- sign extension instructions
 
-(define_insn "extendqisi2"
+(define_expand "extendqisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(sign_extend:SI
+	 (match_operand:QI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=dx,dx")
 	(sign_extend:SI
 	 (match_operand:QI 1 "general_operand" "0,dx")))]
@@ -1305,7 +1361,14 @@
   mov %1,%0\;extb %0"
   [(set_attr "cc" "none_0hit")])
 
-(define_insn "extendhisi2"
+(define_expand "extendhisi2"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(sign_extend:SI
+	 (match_operand:HI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=dx,dx")
 	(sign_extend:SI
 	 (match_operand:HI 1 "general_operand" "0,dx")))]
@@ -1319,7 +1382,15 @@
 ;; SHIFTS
 ;; ----------------------------------------------------------------------
 
-(define_insn "ashlsi3"
+(define_expand "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashift:SI
+	 (match_operand:SI 1 "register_operand" "")
+	 (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
 	(ashift:SI
 	 (match_operand:SI 1 "register_operand" "0,0,0,0,0")
@@ -1333,7 +1404,15 @@
   asl %S2,%0"
   [(set_attr "cc" "set_zn")])
 
-(define_insn "lshrsi3"
+(define_expand "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI
+	 (match_operand:SI 1 "register_operand" "")
+	 (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(lshiftrt:SI
 	 (match_operand:SI 1 "register_operand" "0")
@@ -1342,7 +1421,15 @@
   "lsr %S2,%0"
   [(set_attr "cc" "set_zn")])
 
-(define_insn "ashrsi3"
+(define_expand "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashiftrt:SI
+	 (match_operand:SI 1 "register_operand" "")
+	 (match_operand:QI 2 "nonmemory_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(ashiftrt:SI
 	 (match_operand:SI 1 "register_operand" "0")