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| author | Richard Earnshaw <rearnsha@arm.com> | 2005-11-16 22:14:38 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2005-11-16 22:14:38 +0000 |
| commit | f7657ed3d6d901f34228e20df4a02b091ea24126 (patch) | |
| tree | 847864649c8b132410c338227298aaa46b0947ff /gcc | |
| parent | 60aef23e3893b32703adcfbd49037b72ca6b21f2 (diff) | |
| download | gcc-f7657ed3d6d901f34228e20df4a02b091ea24126.zip gcc-f7657ed3d6d901f34228e20df4a02b091ea24126.tar.gz gcc-f7657ed3d6d901f34228e20df4a02b091ea24126.tar.bz2 | |
re PR target/24861 (internal compiler error when building gcc with --with-cpu=ep9312 --with-fpu=maverick)
PR target/24861
* arm.md (split for movsf with immediate): Restrict split to insns
that set a general register.
From-SVN: r107104
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 5 |
2 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d0ef8fc..5c7ce8e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-11-16 Richard Earnshaw <richard.earnshaw@arm.com> + + PR target/24861 + * arm.md (split for movsf with immediate): Restrict split to insns + that set a general register. + 2005-11-16 Daniel Jacobowitz <dan@codesourcery.com> * config/ia64/unwind-ia64.c (uw_advance_context): New. Call diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 1b671fa..aa28c3f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5137,11 +5137,12 @@ " ) +;; Transform a floating-point move of a constant into a core register into +;; an SImode operation. (define_split - [(set (match_operand:SF 0 "nonimmediate_operand" "") + [(set (match_operand:SF 0 "arm_general_register_operand" "") (match_operand:SF 1 "immediate_operand" ""))] "TARGET_ARM - && !(TARGET_HARD_FLOAT && TARGET_FPA) && reload_completed && GET_CODE (operands[1]) == CONST_DOUBLE" [(set (match_dup 2) (match_dup 3))] |