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authorBernd Schmidt <bernds@cygnus.co.uk>1999-12-30 12:43:51 +0000
committerBernd Schmidt <crux@gcc.gnu.org>1999-12-30 12:43:51 +0000
commitd22ce03d6e4106c647e11eba966929dd20662359 (patch)
tree1c422daa5df515669ec565ecc8ca50d2969a5847 /gcc
parent3fe5b1438ea8fd281aac816f328e791bd63a2ba1 (diff)
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Fix FP GT comparisons on i386 with -ffast-math
From-SVN: r31138
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/i386/i386.c4
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a26dfd2..1282eb0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+1999-12-30 Bernd Schmidt <bernds@cygnus.co.uk>
+
+ * i386.c (ix86_expand_fp_compare): In non-sahf non-TARGET_IEEE
+ case, expand GT comparisons correctly. Fix a comment before this
+ part of the code.
+
1999-12-30 Gabriel Dos Reis <dosreis@cmla.ens-cachan.fr>
* dwarfout.c: Include "frame.h"
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 18124b4..7952118 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4077,7 +4077,7 @@ ix86_expand_fp_compare (code, op0, op1, unordered)
{
/*
* The numbers below correspond to the bits of the FPSW in AH.
- * C3, C2, and C0 are in bits 0x40, 0x40, and 0x01 respectively.
+ * C3, C2, and C0 are in bits 0x40, 0x4, and 0x01 respectively.
*
* cmp C3 C2 C0
* > 0 0 0
@@ -4091,7 +4091,7 @@ ix86_expand_fp_compare (code, op0, op1, unordered)
switch (code)
{
case GT:
- mask = 0x01;
+ mask = 0x41;
code = EQ;
break;
case LT: