h8300.c (two_insn_adds_subs_operand): Fix a typo.

        * h8300.c (two_insn_adds_subs_operand): Fix a typo.
        * h8300.h (OK_FOR_T): New.
        (EXTRA_CONSTRAINT): Support OK_FOR_T.
        * h8300.md: Use inc/dec.[wl] for increment/decrement
        by 1 and 2 in HI and SI modes.

From-SVN: r35155

4 files changed, 38 insertions, 16 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6d316d2..6c7c6a3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2000-07-20  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300.c (two_insn_adds_subs_operand): Fix a typo.
+	* h8300.h (OK_FOR_T): New.
+	(EXTRA_CONSTRAINT): Support OK_FOR_T.
+	* h8300.md: Use inc/dec.[wl] for increment/decrement
+	by 1 and 2 in HI and SI modes.
+
 2000-07-20  Jim Wilson  <wilson@cygnus.com>
 
 	* config/ia64/ia64.h (ASM_OUTPUT_MI_THUNK): Handle DELTA values
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index ba46d04..2688714 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -648,7 +648,7 @@ two_insn_adds_subs_operand (op, mode)
 	  /* A constant addition/subtraction takes 2 states in QImode,
 	     4 states in HImode, and 6 states in SImode.  Thus, the
 	     only case we can win is when SImode is used, in which
-	     case, two adds/subs is used, taking 4 states.  */
+	     case, two adds/subs are used, taking 4 states.  */
 	  if (mode == SImode
 	      && (value == 2 + 1
 		  || value == 4 + 1
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 5d35d27..941a8ad 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -828,9 +828,17 @@ struct cum_arg
 
 #endif
 
-/* Extra constraints - 'U' if for an operand valid for a bset
-   destination; i.e. a register, register indirect, or the
-   eightbit memory region (a SYMBOL_REF with an SYMBOL_REF_FLAG set). 
+/* Extra constraints.  */
+
+/* 'T' if valid for dec.[wl] on H8/300H and H8/S.  Note that, for
+   inc.[wl], we can use 'K', which has already been defined.  */
+#define OK_FOR_T(OP)				\
+  (GET_CODE (OP) == CONST_INT			\
+   && (INTVAL (OP) == -1 || INTVAL (OP) == -2))
+
+/* 'U' if valid for a bset destination;
+   i.e. a register, register indirect, or the eightbit memory region
+   (a SYMBOL_REF with an SYMBOL_REF_FLAG set).
 
    On the H8/S 'U' can also be a 16bit or 32bit absolute.  */
 #define OK_FOR_U(OP) \
@@ -845,8 +853,10 @@ struct cum_arg
         && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT) \
         && (TARGET_H8300S || SYMBOL_REF_FLAG (XEXP (XEXP (OP, 0), 0)))))
 
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'U' ? OK_FOR_U (OP) : 0)
+#define EXTRA_CONSTRAINT(OP, C)			\
+  ((C) == 'T' ? OK_FOR_T (OP) :			\
+   (C) == 'U' ? OK_FOR_U (OP) :			\
+   0)
 
 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
    that is a valid memory address for an instruction.
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 91cafa5..e005368 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -629,17 +629,19 @@
    (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
 
 (define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
-	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
-		 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
+	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
+		 (match_operand:HI 2 "nonmemory_operand" "K,T,L,N,n,r")))]
   "TARGET_H8300H || TARGET_H8300S"
   "@
+   inc.w	%2,%T0
+   dec.w	%G2,%T0
    adds	%2,%A0
    subs	%G2,%A0
    add.w	%T2,%T0
    add.w	%T2,%T0"
-  [(set_attr "length" "2,2,4,2")
-   (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
+  [(set_attr "length" "2,2,2,2,4,2")
+   (set_attr "cc" "set_znv,set_znv,none_0hit,none_0hit,set_zn,set_zn")])
 
 (define_split
   [(set (match_operand:HI 0 "register_operand" "")
@@ -669,17 +671,19 @@
    (set_attr "cc" "clobber")])
 
 (define_insn "addsi_h8300h"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
-		 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
+		 (match_operand:SI 2 "nonmemory_operand" "K,T,L,N,i,r")))]
   "TARGET_H8300H || TARGET_H8300S"
   "@
+   inc.l	%2,%S0
+   dec.l	%G2,%S0
    adds	%2,%A0
    subs	%G2,%A0
    add.l	%S2,%S0
    add.l	%S2,%S0"
-  [(set_attr "length" "2,2,6,2")
-   (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
+  [(set_attr "length" "2,2,2,2,6,2")
+   (set_attr "cc" "set_znv,set_znv,none_0hit,none_0hit,set_zn,set_zn")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")