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| author | Jeffrey A Law <law@cygnus.com> | 1999-12-29 17:54:29 +0000 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 1999-12-29 10:54:29 -0700 |
| commit | b1f107272c6604f9b5d26be785cd8d4ec071e3dd (patch) | |
| tree | 9692c753a06d26b78084a5b8d0a053b02a010d5c /gcc | |
| parent | 1fc69a8a429b038f26c691683a14fb5b2f83e723 (diff) | |
| download | gcc-b1f107272c6604f9b5d26be785cd8d4ec071e3dd.zip gcc-b1f107272c6604f9b5d26be785cd8d4ec071e3dd.tar.gz gcc-b1f107272c6604f9b5d26be785cd8d4ec071e3dd.tar.bz2 | |
pa.md (conditional zero): If op1 is a register, force it into the same register as op0.
* pa.md (conditional zero): If op1 is a register, force it into
the same register as op0.
From-SVN: r31118
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 23 |
2 files changed, 19 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e220843..aa1d9cd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Wed Dec 29 10:53:21 1999 Jeffrey A Law (law@cygnus.com) + + * pa.md (conditional zero): If op1 is a register, force it into + the same register as op0. + 1999-12-28 Mark Mitchell <mark@codesourcery.com> * tree.h (BINFO_BASETYPES): Improve documentation. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index d342764..a3ef9c5 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -862,25 +862,30 @@ operands[5] = hppa_compare_op1; }") -; We need the first constraint alternative in order to avoid -; earlyclobbers on all other alternatives. +;; We used to accept any register for op1. +;; +;; However, it loses sometimes because the compiler will end up using +;; different registers for op0 and op1 in some critical cases. local-alloc +;; will not tie op0 and op1 because op0 is used in multiple basic blocks. +;; +;; If/when global register allocation supports tying we should allow any +;; register for op1 again. (define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (if_then_else:SI (match_operator 5 "comparison_operator" - [(match_operand:SI 3 "register_operand" "r,r,r,r,r") - (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI")]) - (match_operand:SI 1 "reg_or_cint_move_operand" "0,r,J,N,K") + [(match_operand:SI 3 "register_operand" "r,r,r,r") + (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")]) + (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K") (const_int 0)))] "" "@ {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi 0,%0 - {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;copy %1,%0 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldi %1,%0 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldil L'%1,%0 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0" - [(set_attr "type" "multi,multi,multi,multi,nullshift") - (set_attr "length" "8,8,8,8,8")]) + [(set_attr "type" "multi,multi,multi,nullshift") + (set_attr "length" "8,8,8,8")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r") |