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| author | Uros Bizjak <ubizjak@gmail.com> | 2017-08-27 20:01:46 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-08-27 20:01:46 +0200 |
| commit | a5df209084512242c037f1d35f0b2e4969b04519 (patch) | |
| tree | 20a665db55c7a7e8956d8ffc7c17d7d6ebeb171a /gcc | |
| parent | 86e03ef911346681949ae6812d64569008936fb4 (diff) | |
| download | gcc-a5df209084512242c037f1d35f0b2e4969b04519.zip gcc-a5df209084512242c037f1d35f0b2e4969b04519.tar.gz gcc-a5df209084512242c037f1d35f0b2e4969b04519.tar.bz2 | |
re PR target/81995 (gcc/reg-stack.c:2073:1: error: unrecognizable insn:)
PR target/81995
* config/i386/i386.md (*<btsc><mode>): Change operand 2
predicate to register_operand. Reorder operands.
(*btr<mode>): Ditto.
(*<btsc><mode>_mask): Change operand 3 predicate to register_operand.
(*btr<mode>_mask): Ditto.
testsuite/ChangeLog:
PR target/81995
* gcc.target/i386/pr46091-4.c: Add -mregparm=2 for 32bit targets.
* gcc.target/i386/pr46091-4a.c: Ditto.
From-SVN: r251369
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 16 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr46091-4.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr46091-4a.c | 1 |
5 files changed, 25 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5a425e3..b1070d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-08-27 Uros Bizjak <ubizjak@gmail.com> + + PR target/81995 + * config/i386/i386.md (*<btsc><mode>): Change operand 2 + predicate to register_operand. Reorder operands. + (*btr<mode>): Ditto. + (*<btsc><mode>_mask): Change operand 3 predicate to register_operand. + (*btr<mode>_mask): Ditto. + 2017-08-25 Steven Munroe <munroesj@gcc.gnu.org> * config.gcc (powerpc*-*-*): Add xmmintrin.h and mm_malloc.h. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f984060..7465848 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -11011,11 +11011,11 @@ [(set (match_operand:SWI48 0 "register_operand" "=r") (any_or:SWI48 (ashift:SWI48 (const_int 1) - (match_operand:QI 1 "register_operand" "r")) - (match_operand:SWI48 2 "nonimmediate_operand" "0"))) + (match_operand:QI 2 "register_operand" "r")) + (match_operand:SWI48 1 "register_operand" "0"))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT" - "<btsc>{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}" + "<btsc>{<imodesuffix>}\t{%<k>2, %0|%0, %<k>2}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") (set_attr "znver1_decode" "double") @@ -11031,7 +11031,7 @@ (and:SI (match_operand:SI 1 "register_operand") (match_operand:SI 2 "const_int_operand")) 0)) - (match_operand:SWI48 3 "nonimmediate_operand"))) + (match_operand:SWI48 3 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "(INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) == GET_MODE_BITSIZE (<MODE>mode)-1 @@ -11051,11 +11051,11 @@ [(set (match_operand:SWI48 0 "register_operand" "=r") (and:SWI48 (rotate:SWI48 (const_int -2) - (match_operand:QI 1 "register_operand" "r")) - (match_operand:SWI48 2 "nonimmediate_operand" "0"))) + (match_operand:QI 2 "register_operand" "r")) + (match_operand:SWI48 1 "register_operand" "0"))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT" - "btr{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}" + "btr{<imodesuffix>}\t{%<k>2, %0|%0, %<k>2}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") (set_attr "znver1_decode" "double") @@ -11071,7 +11071,7 @@ (and:SI (match_operand:SI 1 "register_operand") (match_operand:SI 2 "const_int_operand")) 0)) - (match_operand:SWI48 3 "nonimmediate_operand"))) + (match_operand:SWI48 3 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "(INTVAL (operands[2]) & (GET_MODE_BITSIZE (<MODE>mode)-1)) == GET_MODE_BITSIZE (<MODE>mode)-1 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f80aaf2..d4bcd42 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-08-27 Uros Bizjak <ubizjak@gmail.com> + + PR target/81995 + * gcc.target/i386/pr46091-4.c: Add -mregparm=2 for 32bit targets. + * gcc.target/i386/pr46091-4a.c: Ditto. + 2017-08-27 Thomas Koenig <tkoenig@gcc.gnu.org> PR fortran/81974 diff --git a/gcc/testsuite/gcc.target/i386/pr46091-4.c b/gcc/testsuite/gcc.target/i386/pr46091-4.c index af2cfae..f88ff5e 100644 --- a/gcc/testsuite/gcc.target/i386/pr46091-4.c +++ b/gcc/testsuite/gcc.target/i386/pr46091-4.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ +/* { dg-additional-options "-mregparm=2" { target ia32 } } */ int test_1 (int x, int n) { diff --git a/gcc/testsuite/gcc.target/i386/pr46091-4a.c b/gcc/testsuite/gcc.target/i386/pr46091-4a.c index 5874aee..debbdaa 100644 --- a/gcc/testsuite/gcc.target/i386/pr46091-4a.c +++ b/gcc/testsuite/gcc.target/i386/pr46091-4a.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ +/* { dg-additional-options "-mregparm=2" { target ia32 } } */ int test_1 (int x, int n) { |