Add a no_register_allocation target hook.

	* target.def (no_register_allocation): New data hook.
	* doc/tm.texi.in: Add @hook TARGET_NO_REGISTER_ALLOCATION.
	* doc/tm.texi: Regenerate.
	* ira.c (gate_ira): New function.
	(pass_data_ira): Set has_gate.
	(pass_ira): Add a gate function.
	(pass_data_reload): Likewise.
	(pass_reload): Add a gate function.
	(pass_ira): Use it.
	* reload1.c (eliminate_regs): If reg_eliminate_is NULL, assert that
	no register allocation happens on the target and return.
	* final.c (alter_subreg): Ensure register is not a pseudo before
	calling simplify_subreg.
	(output_operand): Assert that x isn't a pseudo only if doing
	register allocation.

From-SVN: r217122

7 files changed, 52 insertions, 6 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bb2b59e..ff9ead6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,21 @@
 2014-11-05  Bernd Schmidt  <bernds@codesourcery.com>
 
+	* target.def (no_register_allocation): New data hook.
+	* doc/tm.texi.in: Add @hook TARGET_NO_REGISTER_ALLOCATION.
+	* doc/tm.texi: Regenerate.
+	* ira.c (gate_ira): New function.
+	(pass_data_ira): Set has_gate.
+	(pass_ira): Add a gate function.
+	(pass_data_reload): Likewise.
+	(pass_reload): Add a gate function.
+	(pass_ira): Use it.
+	* reload1.c (eliminate_regs): If reg_eliminate_is NULL, assert that
+	no register allocation happens on the target and return.
+	* final.c (alter_subreg): Ensure register is not a pseudo before
+	calling simplify_subreg.
+	(output_operand): Assert that x isn't a pseudo only if doing
+	register allocation.
+
 	* dbxout.c (dbxout_symbol): Don't call eliminate_regs on decls for
 	global vars.
 
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 0d1f149..dbca62d 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -9323,11 +9323,19 @@ True if the @code{DW_AT_comp_dir} attribute should be emitted for each  compilat
 @end deftypevr
 
 @deftypevr {Target Hook} bool TARGET_DELAY_SCHED2
-True if sched2 is not to be run at its normal place.  This usually means it will be run as part of machine-specific reorg.
+True if sched2 is not to be run at its normal place.
+This usually means it will be run as part of machine-specific reorg.
 @end deftypevr
 
 @deftypevr {Target Hook} bool TARGET_DELAY_VARTRACK
-True if vartrack is not to be run at its normal place.  This usually means it will be run as part of machine-specific reorg.
+True if vartrack is not to be run at its normal place.
+This usually means it will be run as part of machine-specific reorg.
+@end deftypevr
+
+@deftypevr {Target Hook} bool TARGET_NO_REGISTER_ALLOCATION
+True if register allocation and the passes
+following it should not be run.  Usually true only for virtual assembler
+targets.
 @end deftypevr
 
 @defmac ASM_OUTPUT_DWARF_DELTA (@var{stream}, @var{size}, @var{label1}, @var{label2})
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 679b3d1..b732f1f 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -6948,6 +6948,8 @@ tables, and hence is desirable if it works.
 
 @hook TARGET_DELAY_VARTRACK
 
+@hook TARGET_NO_REGISTER_ALLOCATION
+
 @defmac ASM_OUTPUT_DWARF_DELTA (@var{stream}, @var{size}, @var{label1}, @var{label2})
 A C statement to issue assembly directives that create a difference
 @var{lab1} minus @var{lab2}, using an integer of the given @var{size}.
diff --git a/gcc/final.c b/gcc/final.c
index f7ede57d..e958a52 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -3189,7 +3189,7 @@ alter_subreg (rtx *xp, bool final_p)
       else
 	*xp = adjust_address_nv (y, GET_MODE (x), offset);
     }
-  else
+  else if (REG_P (y) && HARD_REGISTER_P (y))
     {
       rtx new_rtx = simplify_subreg (GET_MODE (x), y, GET_MODE (y),
 				     SUBREG_BYTE (x));
@@ -3857,7 +3857,8 @@ output_operand (rtx x, int code ATTRIBUTE_UNUSED)
     x = alter_subreg (&x, true);
 
   /* X must not be a pseudo reg.  */
-  gcc_assert (!x || !REG_P (x) || REGNO (x) < FIRST_PSEUDO_REGISTER);
+  if (!targetm.no_register_allocation)
+    gcc_assert (!x || !REG_P (x) || REGNO (x) < FIRST_PSEUDO_REGISTER);
 
   targetm.asm_out.print_operand (asm_out_file, x, code);
 
diff --git a/gcc/ira.c b/gcc/ira.c
index 630df40..9c9e71d 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -5498,6 +5498,10 @@ public:
   {}
 
   /* opt_pass methods: */
+  virtual bool gate (function *)
+    {
+      return !targetm.no_register_allocation;
+    }
   virtual unsigned int execute (function *)
     {
       ira (dump_file);
@@ -5537,6 +5541,10 @@ public:
   {}
 
   /* opt_pass methods: */
+  virtual bool gate (function *)
+    {
+      return !targetm.no_register_allocation;
+    }
   virtual unsigned int execute (function *)
     {
       do_reload ();
diff --git a/gcc/reload1.c b/gcc/reload1.c
index dab8a75..7d5bad5 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2968,6 +2968,11 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
 rtx
 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
 {
+  if (reg_eliminate == NULL)
+    {
+      gcc_assert (targetm.no_register_allocation);
+      return x;
+    }
   return eliminate_regs_1 (x, mem_mode, insn, false, false);
 }
 
diff --git a/gcc/target.def b/gcc/target.def
index 23cae25..de203c3 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -5421,15 +5421,21 @@ DEFHOOKPOD
  bool, false)
 
 DEFHOOKPOD
-(delay_sched2, "True if sched2 is not to be run at its normal place.  \
+(delay_sched2, "True if sched2 is not to be run at its normal place.\n\
 This usually means it will be run as part of machine-specific reorg.",
 bool, false)
 
 DEFHOOKPOD
-(delay_vartrack, "True if vartrack is not to be run at its normal place.  \
+(delay_vartrack, "True if vartrack is not to be run at its normal place.\n\
 This usually means it will be run as part of machine-specific reorg.",
 bool, false)
 
+DEFHOOKPOD
+(no_register_allocation, "True if register allocation and the passes\n\
+following it should not be run.  Usually true only for virtual assembler\n\
+targets.",
+bool, false)
+
 /* Leave the boolean fields at the end.  */
 
 /* Functions related to mode switching.  */