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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2017-02-07 10:34:47 +0000 |
|---|---|---|
| committer | Toma Tabacu <tomtab@gcc.gnu.org> | 2017-02-07 10:34:47 +0000 |
| commit | a4166fe55334f1d4e1c2615792fca5b5ebc23eee (patch) | |
| tree | e7dda8125e655d4fbed0778af7368dbd690e6bfe /gcc | |
| parent | d95c2fc7b304314a03409f6e7cb7f7dd534b10a8 (diff) | |
| download | gcc-a4166fe55334f1d4e1c2615792fca5b5ebc23eee.zip gcc-a4166fe55334f1d4e1c2615792fca5b5ebc23eee.tar.gz gcc-a4166fe55334f1d4e1c2615792fca5b5ebc23eee.tar.bz2 | |
MIPS: Fix mode mismatch error between Loongson builtin arguments and insn
operands.
gcc/
* config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode
argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
builtins to SImode and emit a zero-extend, if necessary.
From-SVN: r245243
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 18 |
2 files changed, 24 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 38f1971..8affcab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-02-07 Toma Tabacu <toma.tabacu@imgtec.com> + + * config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode + argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw + builtins to SImode and emit a zero-extend, if necessary. + 2017-02-06 Palmer Dabbelt <palmer@dabbelt.com> * docs/invoke.texi (RISC-V Options): Alphabetize. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index da7fa8f..7974a16 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -16571,9 +16571,27 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops, { machine_mode imode; int rangelo = 0, rangehi = 0, error_opno = 0; + rtx sireg; switch (icode) { + /* The third operand of these instructions is in SImode, so we need to + bring the corresponding builtin argument from QImode into SImode. */ + case CODE_FOR_loongson_pshufh: + case CODE_FOR_loongson_psllh: + case CODE_FOR_loongson_psllw: + case CODE_FOR_loongson_psrah: + case CODE_FOR_loongson_psraw: + case CODE_FOR_loongson_psrlh: + case CODE_FOR_loongson_psrlw: + gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode); + sireg = gen_reg_rtx (SImode); + emit_insn (gen_zero_extendqisi2 (sireg, + force_reg (QImode, ops[2].value))); + ops[2].value = sireg; + ops[2].mode = SImode; + break; + case CODE_FOR_msa_addvi_b: case CODE_FOR_msa_addvi_h: case CODE_FOR_msa_addvi_w: |